A server switching system, method, electronic device and storage medium

Abstract

Embodiments of the present application provide a server switching system and method, electronic equipment and a storage medium, wherein the system comprises a computing node module and a network node module connected to each other; the network node module comprises not less than one BMC module, a selection module, a switching module and a PHY interface module; by setting the switching module and the node selection module, the node selection module can control the node of the current input signal of the switching module according to the node selection instruction of the user, without switching the signal debugging circuit in the debugging process of the node, thereby reducing the test period; by setting the switching module and the node selection module, one output signal is realized for multiple input signals, the number of the PHY interface module is reduced, which is conducive to optimizing the structure space allocation of the PCIE equipment and conducive to the reuse of the outer frame structure of the case.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server management, and in particular to a server switching system and method, an electronic device and a storage medium. BACKGROUND

[0002] With the increasing demand of computer computing power, multi-node servers have emerged. Multi-node servers refer to servers with multiple nodes, one node being equivalent to a server. Multi-node servers are composed of multiple node servers and management devices as a whole, and are centrally deployed in a certain range of space.

[0003] In existing multi-node servers, each node usually has an independent BMC (Baseboard Management Controller) module and PHY interface (Physical Layer) module, which often has the following shortcomings: first, the data exchange between the various BMC modules is impossible, resulting in a longer test cycle and increased test cost when physically switching lines to test other nodes after testing any node; second, since each node has an independent BMC module and PHY interface module, it greatly occupies the front window space of the case, increases the number of network interfaces that need to be configured, and is not conducive to the structural space allocation of PCIE (Peripheral Component Interconnect Express) devices, nor is it conducive to the reuse of the case outer frame structure. SUMMARY

[0004] In view of the above problems, one of the purposes of the present application is to provide a server switching system to solve the problems of complex node debugging switching, high test cost, and redundant front window space of the case, and a large number of network interfaces in the prior art; the second purpose is to provide a server switching method; the third purpose is to provide an electronic device; and the fourth purpose is to provide a storage medium.

[0005] In a first aspect, a server switching system is provided, comprising a computing node module and a network node module connected to each other;

[0006] The network node module comprises at least one BMC module, a selection module, a switching module and a PHY interface module;

[0007] The computing node module and the network node module are connected, used for computing the node, generating a first node management signal and sending it to the BMC module;

[0008] The BMC module is configured to process the first node management signal when received, and send a second node management signal to the switching module;

[0009] The first end of the selection module is connected to the switching module, and the second end of the selection module is connected to the PHY interface module, configured to send a node selection signal to the switching module, the node selection signal containing a target node;

[0010] The first end of the switching module is connected to the BMC module, and the second end of the switching module is connected to the PHY interface module, configured to control the input end where the target node is located to be connected to the PHY interface module when the node selection signal is received, and send the second node management signal to the PHY interface module;

[0011] The PHY interface module is configured to process the second node management signal when received, and output a third node management signal.

[0012] In one embodiment, the number of the computing node modules is the same as the number of the BMC modules.

[0013] In one embodiment, the switching module is a multi-way selection switch chip; the selection module is a logic control chip, and the selection module is further configured to control the lighting state of the PHY interface module.

[0014] In one embodiment, a connector is further included, the first end of the connector is connected to the PHY interface module, and the second end of the connector is connected to the selection module.

[0015] In one embodiment, the second node management signal includes an RGMII signal and an MDIO signal; and the third node management signal is an MDI signal.

[0016] In one embodiment, the computing node module is a central processing unit.

[0017] In one embodiment, the network node modules are integrated and installed on an IO board, and the computing node modules and the network node modules interact through a cable and / or a board-to-board connector.

[0018] In a second aspect, a server switching method is provided, and the main steps include:

[0019] The computing node module performs computation on the nodes, generates a first node management signal, and sends the first node management signal to the BMC module;

[0020] The BMC module processes the first node management signal when received, and sends a second node management signal to the switching module;

[0021] The first end of the selection module sends a node selection signal to the switching module, and the node selection signal contains a target node;

[0022] The switching module controls the input end where the target node is located to be connected with the PHY interface module when receiving the node selection signal, and sends a second node management signal to the PHY interface module.

[0023] The PHY interface module processes the second node management signal when receiving the second node management signal, and outputs a third node management signal.

[0024] In a third aspect, an electronic device is provided, which includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and the computer program is executed by the processor to implement the server switching method as described in the above embodiments.

[0025] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the server switching method as described in the above embodiments.

[0026] The embodiments of the present application have the following advantages:

[0027] 1. By setting the switching module and the selection module, the selection module can control the node of the current input signal of the switching module according to the node selection instruction of the user, and the node debugging process does not need to switch the signal debugging line, thereby reducing the test period.

[0028] 2. By setting the switching module and the selection module, a plurality of input signals are realized to correspond to one output signal, the number of PHY interface modules is reduced, which is conducive to optimizing the structure space distribution of the PCIE (Peripheral Component Interconnect Express high-speed serial computer expansion bus standard) device and conducive to the reuse of the outer frame structure of the case. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the description of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] Figure 1 It is a structural diagram of the server switching system of the present application.

[0031] Figure 2 It is a structural diagram of the multi-node server in the prior art.

[0032] Figure 3 The structure diagram of the server switching system provided in a preferred embodiment of the present application.

[0033] Figure 4 The flow chart of the server switching method in the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0035] The embodiments of the present application are only used for explaining the present application, and are not used for limiting the scope of the present application. The present application will be described in more detail in the following paragraphs with reference to the drawings in an exemplary manner. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, and are only used for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0036] As shown in the prior art, a conventional multi-node server includes a computing node module, a BMC (Baseboard Management Controller) module, a PHY (Physical Layer) interface module and a frame, and the frame can be assembled with a single or multiple computing nodes; in the prior art, taking a dual-node server as an example, two management network interfaces are exported from the front panel, which are used for the external network device management of the two nodes, and only a single node can be switched at a time, which cannot meet the requirement of corresponding management of each node in the production and test links; therefore, each time the switching to any one node needs to be performed again, which not only prolongs the test period, but also increases the test cost. Figure 2 To solve the problems in the prior art, as shown in the present application, a server switching system is provided, which includes a computing node module and a network node module connected with each other;

[0037] Figure 1 The network node module includes not less than one BMC module, a selection module, a switching module and a PHY interface module;

[0038] The computing node module and the network node module are connected, and are used for computing the nodes, generating a first node management signal and sending the first node management signal to the BMC module;

[0039] The BMC module is used for processing the first node management signal when the first node management signal is received, and sending a second node management signal to the switching module;

[0040] The switching module is used for receiving the second node management signal, and sending a third node management signal to the PHY interface module according to the second node management signal;

[0041] ​The first end of the selection module is connected with the switching module, and the second end of the selection module is connected with the PHY interface module, for sending a node selection signal to the switching module, and the node selection signal contains a target node;

[0042] The first end of the switching module is connected with the BMC module, and the second end of the switching module is connected with the PHY interface module, for controlling the input end where the target node is located to be connected with the PHY interface module when the node selection signal is received, and sending a second node management signal to the PHY interface module;

[0043] The PHY interface module is used for processing the second node management signal when the second node management signal is received, and outputting a third node management signal.

[0044] The BMC module is a special microcontroller embedded on a server mainboard, responsible for managing the interface between system management software and platform hardware; the server generally uses BMC instructions for large-scale unattended operation, including remote management, monitoring, installation, and restart of the server.

[0045] The PHY interface module, i.e., the physical layer interface module, defines the electrical and optical signals, line states, clock references, data coding, and circuits required for data transmission and reception; the PHY interface module is used for receiving data transmitted by the physical layer, encoding the data according to the coding rules of the physical layer, and then converting the data into analog signals to send out.

[0046] In the above embodiment, by setting the switching module and the selection module, the selection module can control the node of the current input signal of the switching module according to the node selection instruction of the user, and the debugging process of the node does not need to switch the signal debugging circuit, thereby reducing the test period; by setting the switching module and the selection module, a plurality of input signals are corresponded to one output signal, thereby reducing the number of PHY interface modules, which is conducive to optimizing the structure space distribution of the PCIE (Peripheral Component Interconnect Express high-speed serial computer expansion bus standard) device and conducive to the reuse of the outer frame structure of the case.

[0047] As shown in FIG. Figure 3 In a preferred embodiment, the BMC module is provided with an RGMII (Reduced Gigabit Media Independent Interface) interface and an MDIO (Management Data Input / Output) interface, and the second node management signal includes an RGMII signal and an MDIO signal.

[0048] Specifically, there are two BMC modules on the IO board, the MAC (Media Access Control) interface of the chip of which is RGMII interface, and each BMC module provides MDIO interface for management of the PHY interface module.

[0049] The RGMII interface adopts 4-bit data, the working clock is 125MHz, and data is transmitted at the rising and falling edges simultaneously, so the transmission rate can reach 1000Mbps; the RGMII data structure conforms to the IEEE Ethernet standard; the purpose of adopting the RGMII interface is to reduce the circuit cost, so that the pin number of the device implementing this interface is reduced from 25 to 14.

[0050] In the above embodiment, the MDIO bus interface is adopted, and the main purpose is to complete the register configuration of the PHY interface module.

[0051] As shown in Figure 3 In a preferred embodiment, the BMC module is provided with RGMII (Reduced Gigabit Media Independent Interface) interface and MDIO (Management Data Input / Output) interface, and the second node management signal includes RGMII signal and MDIO signal.

[0052] Specifically, there are two BMC modules on the IO board, the MAC4 interface of the chip of which is RGMII interface, and each BMC module provides MDIO interface for management of the PHY interface module.

[0053] The RGMII interface adopts 4-bit data, the working clock is 125MHz, and data is transmitted at the rising and falling edges simultaneously, so the transmission rate can reach 1000Mbps; the RGMII data structure conforms to the IEEE Ethernet standard; the purpose of adopting the RGMII interface is to reduce the circuit cost, so that the pin number of the device implementing this interface is reduced from 25 to 14.

[0054] In the above embodiment, the MDIO bus interface is adopted, and the main purpose is to complete the register configuration of the PHY interface module.

[0055] In this embodiment, the switching module is a SWITCH chip, and the model of the SWITCH chip is PI3PCIE3412.

[0056] Specifically, the RGMII and MDIO interfaces of the two BMC modules are connected to the input optional 1 output of the SWITCH chip of the high-speed bus 2, and the SWITCH is PI3PCIE3412.

[0057] In the embodiment, an RJ45 (Registered Jack 45) connector is further included, and the RJ45 connector is connected to the PHY interface module and the selection module respectively.

[0058] In the embodiment, the selection module is a CPLD (Complex Programmable Logic Device) logic control chip, and the selection module is further used to control the light-on state of the PHY interface module.

[0059] Specifically, the CPLD logic control chip completes the switching of the currently signal input BMC module through double-click of the front window UID; and a UID integrated double-color lamp is selected to indicate the switching of the two BMC modules.

[0060] In the embodiment, the PHY interface module includes a PHY chip, and the model of the PHY chip is RTL8211FD-CG, and the third node management signal is an MDI (Medium Dependent Interface) signal.

[0061] Specifically, when the PHY interface module receives the RGMII and MDIO signals sent from the SWITCH chip, the RGMII and MDIO signals are modulated into MDI signals and output to the RJ45 network interface of the front window of the case.

[0062] In the embodiment, the RGMII signal includes RGMII_TX_CLK, RGMII_TX_CTRL, RGMII_TXD[3:0], RGMII_RX_CLK, RGMII_RX_CTRL, RGMII_RXD[3:0] and MDIO / MDC.

[0063] Specifically, the SWITCH chip PI3PCIE3412 is a 4-channel Mux (Multiple selector switch) multiplexer chip, the RGMII signals include: RGMII_TX_CLK, RGMII_TX_CTRL, RGMII_TXD[3:0], RGMII_RX_CLK, RGMII_RX_CTRL, RGMII_RXD[3:0] and MDIO / MDC, a total of 14 signals; using 4 SWITCH chips PI3PCIE3412 can simultaneously switch the RGMII signal and the MDIO signal source; using 4 SWITCH chips PI3PCIE3412, defining the CPLD output 4 SEL settings as shown in the following table to complete the switching of the RGMII signal and the MDIO source of the two BMC modules.

[0064] No SEL RGMII home 1 L BMC0 2 H BMC1

[0065] In the embodiment, the network node module is integrated and installed on the IO board, and the computing node module and the network node module interact through a cable or a board-to-board connector.

[0066] A second aspect, as shown in the figure, a server switching method is proposed, and the main steps include: Figure 4

[0067] The computing node module performs computation on the node, generates a first node management signal and sends it to the BMC module;

[0068] When the BMC receives the first node management signal, it processes the first node management signal and sends a second node management signal to the switching module;

[0069] The first end of the selection module sends a node selection signal to the switching module, and the node selection signal contains a target node;

[0070] When the switching module receives the node selection signal, it controls the input end where the target node is located to be connected with the PHY interface module, and sends the second node management signal to the PHY interface module;

[0071] When the PHY interface module receives the second node management signal, it processes the second node management signal and outputs a third node management signal.

[0072] ​In the above embodiment, by setting the switching module and the selection module, the selection module can control the switching module to select the node of the current input signal according to the node selection instruction of the user, without switching the signal debugging circuit in the debugging process of the node, thereby reducing the test period; by setting the switching module and the selection module, one output signal is realized for multiple input signals, thereby reducing the number of PHY interface modules, which is beneficial to optimizing the structure space distribution of the PCIE (Peripheral Component Interconnect Express high-speed serial computer expansion bus standard) equipment and the reuse of the outer frame structure of the case.

[0073] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present application are not limited to the action sequence described, because according to the embodiments of the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of the present application.

[0074] In a third aspect, an electronic device is provided, which includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the server switching method described in the above embodiments is realized.

[0075] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and when the computer program is executed by a processor, the server switching method described in the above embodiments is realized.

[0076] For the method embodiments, since they are basically similar to the system embodiments, the description is relatively simple, and the relevant parts are described in the part of the system embodiments.

[0077] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between the embodiments can be referred to each other.

[0078] Those skilled in the art should know that the embodiments of the present application can be provided as a system, a method, or a computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0079] The embodiments of the present application are described with reference to the flowchart and / or block diagram of the method, terminal device (system) and computer program product according to the embodiments of the present application. It is understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0080] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, such that a series of operational steps are performed on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0082] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to the described embodiments without departing from the inventive concepts disclosed in the present application. Accordingly, the appended claims are intended to cover all such modifications and variations as falling within the scope of the present application.

[0083] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the aforesaid element.

[0084] The above provides a kind of server switching system, method, electronic equipment and storage medium, detailed introduction is carried out, the principle and implementation of the present application are described in this paper with specific examples, the above example is only for helping to understand the method of the present application and its core idea;For the general technical personnel in the art, according to the idea of the present application, there will be changes in specific implementation and application range, in view of the above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A server switching system, characterized by, The network node module comprises at least one BMC baseboard management controller module, a selection module, a switching module and a PHY physical layer interface module. The network node module comprises at least one BMC baseboard management controller module, a selection module, a switching module and a PHY physical layer interface module. The computing node module and the network node module are connected to perform node calculation, generate a first node management signal and send it to the BMC baseboard management controller module. The BMC baseboard management controller module processes the first node management signal and sends a second node management signal to the switching module upon receiving the first node management signal. The first end of the selection module is connected to the switching module, and the second end of the selection module is connected to the PHY physical layer interface module, for sending a node selection signal to the switching module, the node selection signal containing a target node. The first end of the switching module is connected to the BMC baseboard management controller module, and the second end of the switching module is connected to the PHY physical layer interface module, for controlling the input end where the target node is located to be connected to the PHY physical layer interface module upon receiving the node selection signal, and sending the second node management signal to the PHY physical layer interface module. The PHY physical layer interface module processes the second node management signal upon receiving the second node management signal and outputs a third node management signal.

2. The system of claim 1, wherein, The number of the computing node modules is the same as the number of the BMC baseboard management controller modules.

3. The system of claim 2, wherein, The switching module is a multi-channel selection switch chip, and the selection module is a logic control chip, which is also used to control the lighting state of the PHY physical layer interface module.

4. The system of claim 2, wherein, A connector is further included, with the first end of the connector being connected to the PHY physical layer interface module and the second end of the connector being connected to the selection module.

5. The system of claim 2, wherein, The second node management signal comprises a RGMII gigabit medium independent signal and an MDIO management data input / output signal, and the third node management signal is an MDI media independent interface signal.

6. The system of claim 2, wherein, The computing node module is a central processing unit.

7. The system of any of claims 1-6, wherein, The network node module is integrated and installed on an IO board, and the computing node module and the network node module interact through a cable and / or a board-to-board connector.

8. A server switching method, characterized by, The main steps include: The computing node module performs node calculation, generates a first node management signal and sends it to the BMC baseboard management controller module. The BMC baseboard management controller module processes the first node management signal upon receiving the first node management signal and sends a second node management signal to the switching module. The first end of the selection module sends a node selection signal to the switching module, the node selection signal containing a target node. The switching module controls the input end where the target node is located to be connected to the PHY physical layer interface module upon receiving the node selection signal and sends the second node management signal to the PHY physical layer interface module. The PHY physical layer interface module processes the second node management signal when receiving the second node management signal, and outputs a third node management signal; The network node module includes no less than one BMC baseboard management controller module, a selection module, a switching module and a PHY physical layer interface module; The first end of the selection module is connected with the switching module, the second end of the selection module is connected with the PHY physical layer interface module, the first end of the switching module is connected with the BMC baseboard management controller module, and the second end of the switching module is connected with the PHY physical layer interface module.

9. An electronic device, comprising: The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the server switching method of claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the server switching method of claim 8.

Images