Display driving circuit, display driving method, and display device

Abstract

This application belongs to the field of display, and specifically relates to a display driving circuit, a display driving method, and a display device. The display driving circuit includes a level conversion chip, a plurality of cascaded gate driving modules, a delay module, a comparison module, and a power management chip. The level conversion chip is connected to at least the gate driving module of the first stage. The gate driving module outputs a scan signal to the scan line and the next-stage gate driving module. The delay module is connected to a gate driving module through a feedback signal line. The comparison module is connected to the feedback signal line and the delay module, and is used to compare the voltage of the feedback signal line with a reference voltage. The power management chip is connected to the comparison module and the level conversion chip, and is used to adjust the high-level signal according to the comparison result and output it to the level conversion chip. Since the level conversion chip outputs a scan driving signal to drive the gate driving module according to the high-level signal, adjusting the high-level signal can adjust the driving ability of the scan signal and reduce the risk of display anomalies.

Description

Technical Field

[0001] This application belongs to the field of displays, and particularly relates to a display driving circuit, a display driving method, and a display device. Background Art

[0002] With the development of display technology, thin film transistor liquid crystal displays (TFT-LCDs) have been widely used in various consumer electronic products due to their advantages of high image quality, power saving, thin body, and mature and stable manufacturing processes, and have become the mainstream in display devices.

[0003] A liquid crystal display can adopt GDL (gate driverless) technology to drive a pixel array. After the GDL circuit provides a scan signal on the corresponding gate line, all TFTs connected to the gate line are switched to the on state, so that each pixel on this gate line receives a data signal from its respective connected data line, and controls the light transmittance of the liquid crystal in different pixels according to the data signal, thereby realizing the display of a row of pixels. Then, after the gate driving chip sends an initial driving signal to the first several GDL circuits, the cascaded GDL circuits will sequentially receive the driving signal of the next-level GDL circuit from the previous-level GDL circuit, thereby realizing the scan driving of all GDL circuits.

[0004] Due to panel characteristics, the conduction ability of TFTs decreases at low temperatures, resulting in distortion of the scan signal generated by the GDL circuit at low temperatures, thereby causing a decrease in the charging ability of panel pixels, or even inability to drive the pixels, resulting in abnormal display; the conduction ability of TFTs increases at high temperatures, resulting in an increase in GDL current at high temperatures, making the temperature of WOA (Wire on Array) very high, with a risk of liquid crystal polarization, resulting in abnormal display. Summary of the Invention

[0005] The purpose of this application is to provide a display driving circuit, a display driving method, and a display device to adjust the driving ability of the GDL circuit and reduce the risk of abnormal display.

[0006] To achieve the above purpose, this application provides a display driving circuit, including a plurality of cascaded gate driving modules, where the gate driving modules are configured to output a scan signal to a scan line of a display panel and the next-level gate driving module in response to a scan driving signal, and the display driving circuit further includes:

[0007] A delay module, connected to one of the gate driving modules through a feedback signal line, configured to delay and output a control signal after receiving a signal;

[0008] A comparison module, connected to the feedback signal line and the delay module, for comparing the voltage of the feedback signal line with a reference voltage;

[0009] A level conversion chip, connected to at least the gate driving module of the first stage, and the level conversion chip can output the corresponding scan driving signal according to the level of the high-level signal;

[0010] A power management chip, connected to the comparison module and the level conversion chip, for adjusting the high-level signal according to the comparison result of the comparison module and outputting it to the level conversion chip. Adjusting the high-level signal can adjust the scan driving signal to adjust the driving ability of the scan signal.

[0011] Optionally, the display driving circuit further includes a voltage trigger, the voltage trigger is connected to the feedback signal line and the delay module, and the voltage trigger is used to receive the scan signal of the feedback signal line and output a trigger signal to the delay module when the voltage of the feedback signal line is greater than a preset voltage.

[0012] Optionally, the display driving circuit includes n of the gate driving modules, each of the gate driving modules includes a GDL unit, and the n GDL units are cascaded in sequence, and the GDL units are arranged on the display panel;

[0013] The display panel includes n rows of the scan lines, the n GDL units are respectively connected to the n rows of the scan lines, and the level conversion chip is connected to the GDL unit of the first stage, and n is an integer greater than 1.

[0014] Optionally, the feedback signal line is connected to the GDL unit of the first stage or the feedback signal line is connected to the GDL unit of the nth stage.

[0015] Optionally, the gate driving module of the first stage further includes a sampling unit, the sampling unit and the GDL unit of the gate driving module of the first stage are both connected to the level conversion chip, the sampling unit is connected to the feedback signal line, and the sampling unit is a GDL unit.

[0016] Optionally, the display driving circuit further includes: a timing controller and a control module. The comparison module, the control module, the timing controller, and the level conversion chip are connected in sequence. The control module is further connected to the power management chip. The control module is configured to control at least one of the timing controller and the power management chip to adjust the driving ability of the scan signal according to the comparison result. The scan driving signal includes a clock signal. The timing controller adjusts the driving ability of the scan signal by adjusting the clock signal output by the level conversion chip. The power management chip adjusts the driving ability of the scan signal by adjusting the high-level signal.

[0017] The present application further provides a display driving method for controlling a display driving circuit. The display driving circuit includes a gate driving module, a delay module, a comparison module, a timing controller, a level conversion chip, and a power management chip. A plurality of the gate driving modules are connected in cascade. The gate driving module is configured to output a scan signal to the scan line of the display panel and the next-level gate driving module in response to a scan driving signal. The timing controller and the power management chip are both connected to the level conversion chip. The level conversion chip is at least connected to the first-level gate driving module. The level conversion chip can output the corresponding scan driving signal according to the level of the high-level signal. The delay module is connected to one of the gate driving modules through a feedback signal line and is configured to delay the output of a control signal after receiving a signal. The comparison module is connected to the delay module and the feedback signal line and is configured to compare the voltage of the feedback signal line with a reference voltage. The display driving method includes:

[0018] Obtaining a comparison result of the comparison module comparing the voltage of the feedback signal line with the reference voltage;

[0019] Controlling at least one of the timing controller and the power management chip to adjust the driving ability of the scan signal according to the comparison result. The power management chip can adjust the high-level signal according to the comparison result. By adjusting the high-level signal, the scan driving signal can be adjusted to adjust the driving ability of the scan signal. The timing controller can adjust the scan driving signal output by the level conversion chip according to the comparison result to adjust the driving ability of the scan signal.

[0020] Optionally, the scan driving signal includes a clock signal. Controlling the timing controller to adjust the driving ability of the scan signal includes:

[0021] When it is confirmed that the voltage of the feedback signal line is less than the reference voltage, controlling the timing controller to increase the duty cycle of the clock signal output by the level conversion chip;

[0022] When it is confirmed that the voltage of the feedback signal line is greater than the reference voltage, control the timing controller to reduce the duty cycle of the clock signal output by the level conversion chip.

[0023] Optionally, the power management chip is at least used to output the high-level signal to the level conversion chip. Controlling the power management chip to adjust the driving ability of the scanning signal includes:

[0024] When it is confirmed that the voltage of the feedback signal line is less than the reference voltage, control the power management chip to increase the high-level signal;

[0025] When it is confirmed that the voltage of the feedback signal line is greater than the reference voltage, control the power management chip to reduce the high-level signal.

[0026] This application also provides a display device, including:

[0027] The display driving circuit;

[0028] A display panel, the scanning lines of the display panel are connected to the gate driving module of the display driving circuit.

[0029] The display driving circuit, display driving method, and display device disclosed in this application have the following beneficial effects:

[0030] In this application, the level conversion chip is connected to at least the first-stage gate driving module. The delay module is connected to a gate driving module through the feedback signal line and is used to delay the output of the control signal after receiving the signal. The comparison module is connected to the feedback signal line and the delay module and is used to compare the voltage of the feedback signal line with the reference voltage. The power management chip is connected to the comparison module and the level conversion chip and is used to adjust the high-level signal according to the comparison result of the comparison module and output it to the level conversion chip. Since the level conversion chip outputs a scanning driving signal to drive the gate driving module according to the high-level signal, adjusting the high-level signal can adjust the driving ability of the scanning signal. When the conduction ability of the TFT decreases at low temperature, the driving ability of the scanning signal can be enhanced by increasing the high-level signal VGH, which can enhance the charging ability of the panel pixels. When the conduction ability of the TFT increases at high temperature, the driving ability of the scanning signal is reduced by reducing the high-level signal VGH. At the same time, when the electrical properties of the TFT change, the driving ability of the scanning signal is also adjusted accordingly to compensate for the change in driving ability caused by the electrical property change of the TFT and reduce the risk of display abnormality.

[0031] Other features and advantages of this application will become apparent through the following detailed description, or will be learned in part through the practice of this application.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this disclosure. Brief Description of the Drawings

[0033] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0034] Figure 1 It is a schematic structural diagram of a display driving circuit in Embodiment 1 of the present application.

[0035] Figure 2 It is a schematic diagram of a scan signal in Embodiment 1 of the present application.

[0036] Figure 3 It is a schematic diagram of a gate driving circuit of a display panel in Embodiment 1 of the present application.

[0037] Figure 4 It is a schematic structural diagram of a display driving circuit in Embodiment 2 of the present application.

[0038] Figure 5 It is a schematic diagram of a gate driving circuit of a display panel in Embodiment 2 of the present application.

[0039] Figure 6 It is a schematic structural diagram of a display driving circuit in Embodiment 3 of the present application.

[0040] Figure 7 It is a schematic diagram of adjusting a clock signal in Embodiment 3 of the present application.

[0041] Figure 8 It is a flowchart of a display driving method in Embodiment 4 of the present application.

[0042] Figure 9 It is a schematic structural diagram of a display device in Embodiment 3 of the present application.

[0043] Description of Reference Numerals:

[0044] 100, main board; 110, level conversion chip; 120, gate driving module; 130, delay module; 140, comparison module; 150, power management chip; 160, feedback signal line; 170, voltage trigger; 180, timing controller; 190, control module;

[0045] 200, display panel. Detailed Description of the Embodiments

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0047] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of this application. However, those skilled in the art will realize that the technical solutions of this application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of this application.

[0048] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation of the present application.

[0049] Embodiment 1

[0050] Referring to Figure 1 As shown, in this embodiment, the driving circuit is shown to include a level shift chip 110 (Levelshift integrated circuit, LSIC) and a plurality of cascaded gate driving modules 120. The level shift chip 110 is connected to at least the first-stage gate driving module 120. The level shift chip 110 is used to output a scan driving signal, and the gate driving module 120 is used to output a scan signal to the scan lines of the display panel and the next-stage gate driving module 120 in response to the scan driving signal. The scan signal output to the scan lines controls the on or off of a row of pixel driving circuits, and the scan signal output to the next-stage gate driving module 120 serves as the scan driving signal of the next-stage gate driving module 120, that is, the previous-stage gate driving module 120 in the cascade provides the scan driving signal for the next-stage gate driving module 120, thereby realizing the scan driving of all gate driving modules 120. The scan driving signal includes a clock signal CK, a frame start signal STV, a low-level signal VSS, and a low-frequency clock signal LC. In addition, the scan driving signal of some gate driving modules 120 further includes a high-level signal VGH.

[0051] The display driving circuit further includes at least: a delay module 130, a comparison module 140, and a power management chip 150. The delay module 130 is connected to a gate driving module 120 through a feedback signal line 160, and is configured to delay and output a control signal after receiving a signal. The gate driving module 120 connected to the feedback signal line 160 can be any one of the cascaded gate driving modules 120. The delay module 130 may include a Delay Gate (DG). The comparison module 140 is connected to the feedback signal line 160 and the delay module 130, and is configured to compare the voltage of the feedback signal line 160 with a reference voltage Vr. The comparison module 140 may include a comparator (COMP), and the reference voltage Vr may be a constant that is always less than the high-level signal VGH.

[0052] The power management chip 150 (power management integrated circuit, PMIC) is connected to the comparison module 140 and the level conversion chip 110, and is configured to adjust the high-level signal VGH according to the comparison result of the comparison module 140 and output it to the level conversion chip 110, so as to adjust the driving ability of the scan signal. The level conversion chip 110 can output a scan driving signal according to the high-level signal VGH to drive the gate driving module 120.

[0053] Specifically, when a scan signal is input on the feedback signal line 160, the delay module 130 delays and outputs a control signal to the comparison module 140 after a set time. The comparison module 140 compares the scan signal on the feedback signal line 160 with the reference voltage Vr. If the voltage of the scan signal on the feedback signal line 160 after delaying the preset time is less than the reference voltage Vr, as shown in Figure 2 shown, after the scan signal Gi1 is delayed by the preset time t, the voltage of the scan signal Gi1 is less than the reference voltage Vr, then the comparison module 140 outputs a control signal to the power management chip 150, and the power management chip 150 will increase the high-level signal VGH. Since the level conversion chip 110 outputs a scan driving signal according to the high-level signal VGH to drive the gate driving module 120, increasing the high-level signal VGH can enhance the driving ability of the scan signal, that is, the next frame of scan signal becomes Gi; if the voltage of the scan signal on the feedback signal line 160 after delaying the preset time is greater than the reference voltage Vr, as shown in Figure 2 shown, after the scan signal Gi2 is delayed by the preset time t, the voltage of the scan signal Gi2 is greater than the reference voltage Vr, then the comparison module 140 outputs a control signal to the power management chip 150, and the power management chip 150 will decrease the high-level signal VGH. Since the level conversion chip 110 outputs a scan driving signal according to the high-level signal VGH to drive the gate driving module 120, decreasing the high-level signal VGH can reduce the driving ability of the scan signal, that is, the next frame of scan signal becomes Gi.

[0054] Due to the characteristics of the panel, the conduction ability of the TFT decreases at low temperatures, and the scan signal output by the gate driving module 120 may be distorted, resulting in a decrease in the charging ability of the panel pixels, or even an inability to drive the pixels, leading to abnormal display; at high temperatures, the conduction ability of the TFT increases, and the temperature of the configured traces on the array substrate is very high, posing a risk of liquid crystal polarization, resulting in abnormal display.

[0055] When the scan signal voltage on the feedback signal line 160 after a preset delay is less than the reference voltage Vr, it indicates that the driving ability of the gate driving module 120 is insufficient, which may lead to a decrease in the charging ability of the panel pixels, or even an inability to drive the pixels. At this time, by increasing the high-level signal VGH to enhance the driving ability of the scan signal, the charging ability of the panel pixels can be enhanced, and the risk of abnormal display can be reduced; when the scan signal voltage on the feedback signal line 160 after a preset delay is greater than the reference voltage Vr, it indicates that the temperature of the configured traces on the array substrate is very high, posing a risk of liquid crystal polarization. At this time, by reducing the high-level signal VGH to reduce the driving ability of the scan signal, the temperature of the configured traces on the array substrate can be reduced, and the risk of abnormal display can be reduced.

[0056] In addition, during the operation of the display panel, the electrical properties of the TFT are also prone to change. For example, due to the long-term action of the gate voltage bias stress and the leakage voltage stress on the TFT, the threshold voltage of the TFT is prone to drift, and at the same time, the mobility is also prone to decrease. The change in the electrical properties of the TFT will also lead to abnormal display. The abnormal display of the display panel caused by temperature can usually be restored, but the abnormal display caused by the change in the electrical properties of the TFT is difficult to restore.

[0057] When the scan signal voltage on the feedback signal line 160 after a preset delay is less than the reference voltage Vr, the driving ability of the scan signal is enhanced by increasing the high-level signal VGH; when the scan signal voltage on the feedback signal line 160 after a preset delay is greater than the reference voltage Vr, the driving ability of the scan signal is reduced by reducing the high-level signal VGH, compensating for the change in the driving ability caused by the change in the electrical properties of the TFT, and reducing the risk of abnormal display.

[0058] In this embodiment, the display driving circuit includes a level conversion chip 110, a plurality of cascaded gate driving modules 120, a delay module 130, a comparison module 140, and a power management chip 150. The level conversion chip 110 is connected to at least the first-stage gate driving module 120. The delay module 130 is connected to a gate driving module 120 through a feedback signal line 160 and is configured to delay the output of a control signal after receiving a signal. The comparison module 140 is connected to the feedback signal line 160 and the delay module 130 and is configured to compare the voltage of the feedback signal line 160 with a reference voltage Vr. The power management chip 150 is connected to the comparison module 140 and the level conversion chip 110 and is configured to adjust the high-level signal VGH according to the comparison result of the comparison module 140 and output it to the level conversion chip 110. Since the level conversion chip 110 outputs a scan driving signal to drive the gate driving module 120 according to the high-level signal VGH, adjusting the high-level signal VGH can adjust the driving ability of the scan signal. When the conduction ability of the TFT decreases at low temperature, the driving ability of the scan signal can be enhanced by increasing the high-level signal VGH, and the charging ability of the panel pixels can be enhanced. When the conduction ability of the TFT increases at high temperature, the driving ability of the scan signal can be reduced by decreasing the high-level signal VGH. At the same time, when the electrical properties of the TFT change, the driving ability of the scan signal is also adjusted accordingly to compensate for the change in driving ability caused by the change in the electrical properties of the TFT and reduce the risk of display anomalies.

[0059] It should be noted that the reference voltage Vr can be a constant that is always less than the high-level signal VGH, but is not limited thereto. The reference voltage Vr can also be a voltage range. The scan signal voltage on the feedback signal line 160 after a preset delay time is within this range, and the high-level signal VGH remains unchanged, which can be determined according to the specific situation.

[0060] In some embodiments, the display driving circuit further includes a voltage flip-flop 170 (FF). The voltage flip-flop 170 is connected to the feedback signal line 160 and the delay module 130. The voltage flip-flop 170 is configured to receive the scan signal of the feedback signal line 160 and output a trigger signal to the delay module 130 when the voltage of the feedback signal line 160 is greater than a preset voltage Vt. The delay module 130 delays a preset time t after receiving the trigger signal and then outputs a control signal to the comparison module 140. The preset voltage Vt can be set to about 5V. For example, the preset voltage Vt is 4V, 5V, 6V, etc.

[0061] The display driving circuit further includes a voltage flip-flop 170. The voltage flip-flop 170 outputs a trigger signal to the delay module 130 when the voltage of the feedback signal line 160 is greater than the preset voltage Vt, thereby avoiding fluctuations in the high-level signal VGH caused by voltage fluctuations of the feedback signal line 160.

[0062] In some embodiments, the power management chip 150 is configured such that when the voltage on the feedback signal line 160 is greater than the reference voltage Vr, the power management chip 150 increases the high-level signal VGH by 1V, and when the voltage on the feedback signal line 160 is less than the reference voltage Vr, the power management chip 150 decreases the high-level signal by 1V. Specifically, a counter can be set inside the power management chip 150. Whenever the comparison module 140 determines that the voltage on the feedback signal line 160 is greater than the reference voltage Vr, the counter is incremented by 1, and the power management chip 150 increases the high-level signal VGH by 1V; whenever the comparison module 140 determines that the voltage on the feedback signal line 160 is less than the reference voltage Vr, the counter is decremented by 1, and the power management chip 150 decreases the high-level signal VGH by 1V.

[0063] When the voltage on the feedback signal line 160 is greater than the reference voltage Vr, the power management chip 150 increases the high-level signal VGH by 1V, and when the voltage on the feedback signal line 160 is less than the reference voltage Vr, the power management chip 150 decreases the high-level signal by 1V, controlling the high-level signal VGH to gradually increase or gradually decrease to avoid abnormal display caused by the high-level signal VGH being too large or too small.

[0064] It should be noted that the high-level signal VGH can be increased or decreased by 1V each time, but it is not limited to this. The high-level signal VGH can also be increased or decreased by 0.5V, 1.5V, etc. each time, depending on the specific situation.

[0065] Exemplarily, referring to Figure 3 As shown, the gate driving module 120 includes GDL units, and the GDL units are provided on the display panel. The GDL unit A1, the GDL unit A2, and the GDL unit An, etc. are cascaded in sequence, where n is an integer greater than 1. The GDL unit A1 outputs the scan signal G1, the GDL unit A2 outputs the scan signal G2, and the GDL unit An outputs the scan signal Gn. The feedback signal line 160 can be connected to any one of the GDL unit A1, the GDL unit A2, and the GDL unit An.

[0066] The gate driving module 120 is a GDL unit, that is, the gate driving adopts GDL technology, thereby reducing the use of gate driving chips and lowering the manufacturing cost of the display driving circuit.

[0067] It should be noted that the gate driving module 120 can be a GDL unit, but it is not limited to this. The gate driving module 120 can also be a gate driving chip, depending on the specific situation.

[0068] Referring to Figure 3As shown, the display driving circuit includes n gate driving modules 120, and each gate driving module 120 includes a GDL unit. The display panel includes n rows of scan lines. The n GDL units are respectively connected to the n rows of scan lines. The scan signal G1 of the GDL unit A1 is output to the first row of scan lines, the scan signal G2 of the GDL unit A2 is output to the second row of scan lines, and the scan signal Gn of the GDL unit An is output to the nth row of scan lines. The level conversion chip 110 is connected to the GDL unit A1 of the first stage.

[0069] The level conversion chip 110 is connected to the GDL unit A1 of the first stage. The GDL unit A1 of the first stage outputs a scan signal to the scan line corresponding to its row to control the on or off of a row of pixel driving circuits. The GDL unit A1 of the first stage outputs a scan signal to the next-stage GDL unit A2, that is, the previous-stage GDL unit in the cascade provides the scan driving signal for the next-stage GDL unit, thereby realizing the scan driving of all gate driving modules 120.

[0070] The level conversion chip 110 is connected to the GDL unit A1 of the first stage, and the gate driving circuit structure of the display panel is simpler, which can reduce the manufacturing cost of the display driving circuit.

[0071] It should be noted that the level conversion chip 110 is connected to the GDL unit A1 of the first stage, but not limited to this. The level conversion chip 110 can also be connected to multiple GDL units, which can be determined according to the specific situation.

[0072] In some embodiments, the feedback signal line 160 is connected to the GDL unit An of the nth stage.

[0073] The GDL unit of the nth stage does not need to cascade the scan signal anymore. The feedback signal line 160 is connected to the GDL unit An of the nth stage, which can avoid the attenuation of the scan signal output by the GDL unit An of the nth stage and affect the driving ability of the scan signal. At the same time, the GDL unit of the nth stage drives the pixel driving circuit of the nth row of the display panel. Even if the GDL unit An of the nth stage is additionally connected with the feedback signal line 160, resulting in a certain attenuation of the scan signal output by the GDL unit An, since the pixel driving circuit of the nth row is at the outermost edge of the display panel, the influence on the display picture is also small.

[0074] It should be noted that the feedback signal line 160 can be connected to the GDL unit An of the nth stage, but not limited to this. The feedback signal line 160 can also be connected to the GDL unit A1 of the first stage, which can be determined according to the specific situation.

[0075] Embodiment 2

[0076] The difference between Embodiment 2 and Embodiment 1 is that the gate driving module 120 of the first stage in Embodiment 2 is different.

[0077] See Figure 4 and Figure 5 As shown, the gate driving module 120 of the first stage may further include a sampling unit A0. The sampling unit A0 of the gate driving module 120 of the first stage and the GDL unit A1 are both connected to the level conversion chip 110, and the sampling unit A0 is connected to the feedback signal line 160.

[0078] The GDL unit outputting the scan signal to the feedback signal line 160 may cause attenuation of the scan signal, thereby affecting the driving ability of the scan signal. The gate driving module 120 of the first stage may further include a sampling unit A0. The sampling unit A0 of the gate driving module 120 of the first stage and the GDL unit A1 are both connected to the level conversion chip 110. The scan signal G1 output by the GDL unit A1 is output to the first row scan line and the next-stage GDL unit A2, and the scan signal G0 output by the sampling unit A0 is output to the feedback signal line 160. The input signals of the sampling unit A0 and the GDL unit A1 are the same, and the changing trends of the scan signal G0 output by the sampling unit A0 are the same. By using the scan signal G0 output by the sampling unit A0 to adjust the high-level signal VGH, it is possible to avoid the connection between the feedback signal line 160 and the GDL unit, resulting in attenuation of the scan signal output by the GDL unit.

[0079] See Figure 4 and Figure 5 As shown, the sampling unit A0 is a GDL unit, and the sampling unit A0 is not cascaded with the GDL unit A1. The input signals of the sampling unit A0 and the GDL unit A1 are the same, and the output signals of the sampling unit A0 and the GDL unit A1 are also the same.

[0080] The sampling unit A0 is a GDL unit, the structure of the gate driving circuit is simpler, and the output signals of the sampling unit A0 and the GDL unit A1 can be made the same.

[0081] Embodiment III

[0082] See Figure 6 As shown, the main difference between Embodiment III and Embodiment I is that the display driving circuit in Embodiment III further includes a timing controller 180 (TCON) and a control module 190 (CON).

[0083] See Figure 6As shown, the display driving circuit further includes: a timing controller 180 and a control module 190. The comparison module 140, the control module 190, the timing controller 180, and the level conversion chip 110 are connected in sequence. The control module 190 is further connected to the power management chip 150. The control module 190 is configured to control at least one of the timing controller 180 and the power management chip 150 to adjust the driving ability of the scan signal according to the comparison result. That is to say, the control module 190 can control the power management chip 150 to adjust the driving ability of the scan signal, that is, the solution disclosed in the embodiment. The control module 190 can also control the timing controller 180. The timing controller 180 adjusts the driving ability of the scan signal by adjusting the clock signal CK output by the level conversion chip 110. The control module 190 can also control the power management chip 150 and the timing controller 180 simultaneously to adjust the high-level signal VGH and the clock signal CK simultaneously.

[0084] When the control module 190 controls the power management chip 150 to adjust the driving ability of the scan signal:

[0085] If the voltage of the scan signal on the feedback signal line 160 after a preset delay time is less than the reference voltage Vr, as shown in Figure 2 As shown, if the voltage of the scan signal Gi1 is less than the reference voltage Vr, the comparison module 140 outputs a control signal to the control module 190. The control module 190 controls the power management chip 150, and the power management chip 150 raises the high-level signal VGH. Since the level conversion chip 110 outputs a scan driving signal according to the high-level signal VGH to drive the gate driving module 120, raising the high-level signal VGH can enhance the driving ability of the scan signal, that is, the next-frame scan signal becomes Gi; if the voltage of the scan signal on the feedback signal line 160 after a preset delay time is greater than the reference voltage Vr, as shown in Figure 2 As shown, if the voltage of the scan signal Gi2 is greater than the reference voltage Vr, the comparison module 140 outputs a control signal to the control module 190. The control module 190 controls the power management chip 150, and the power management chip 150 reduces the high-level signal VGH. Since the level conversion chip 110 outputs a scan driving signal according to the high-level signal VGH to drive the gate driving module 120, reducing the high-level signal VGH can reduce the driving ability of the scan signal, that is, the next-frame scan signal becomes Gi.

[0086] When the control module 190 controls the timing controller 180 to adjust the driving ability of the scan signal:

[0087] As shown in Figure 2 As shown, if the voltage of the scan signal on the feedback signal line 160 after a preset delay time is less than the reference voltage Vr, as shown in Figure 2As shown, if the voltage of the scan signal Gi1 is less than the reference voltage Vr, the comparison module 140 outputs a control signal to the control module 190. The control module 190 controls the timing controller 180, and the timing controller 180 controls the level conversion chip 110 to increase the duty cycle of the clock signal CK. The high level of the scan signal rises relatively faster, enhancing the driving ability of the scan signal, that is, the next frame of the scan signal becomes Gi; if the voltage of the scan signal on the feedback signal line 160 after a preset delay is greater than the reference voltage Vr, see Figure 2 As shown, if the voltage of the scan signal Gi2 is greater than the reference voltage Vr, the comparison module 140 outputs a control signal to the control module 190. The control module 190 controls the timing controller 180, and the timing controller 180 controls the level conversion chip 110 to decrease the duty cycle of the clock signal CK. The high level of the scan signal rises relatively slower, reducing the driving ability of the scan signal, that is, the next frame of the scan signal becomes Gi.

[0088] Exemplarily, see Figure 2 and Figure 7 As shown, the period of a clock signal CK is 10H, where H is the time when a line of data signals is turned on. If the voltage of the scan signal on the feedback signal line 160 after a preset delay is less than the reference voltage Vr, it indicates that the driving ability of the gate driving module 120 is insufficient, which may lead to a decrease in the charging ability of the panel pixels or even an inability to drive the pixels. At this time, the duty cycle of the clock signal CK can be increased from 3H to enhance the driving ability of the scan signal, enhance the charging ability of the panel pixels, and reduce the risk of display anomalies; if the voltage of the scan signal on the feedback signal line 160 after a preset delay is greater than the reference voltage Vr, it indicates that the temperature of the configured trace on the array substrate is very high, with a risk of liquid crystal polarization. At this time, the duty cycle of the clock signal CK can be decreased from 5H to reduce the driving ability of the scan signal, reduce the temperature of the configured trace on the array substrate, and reduce the risk of display anomalies.

[0089] The display driving circuit further includes a timing controller 180 and a control module 190. The control module 190 can control the timing controller 180 and the power management chip 150 to jointly adjust the driving ability of the scan signal according to the comparison result, which can make the adjustment range of the scan signal larger and avoid the high level signal VGH from being too high at the same time.

[0090] Embodiment 4

[0091] In this embodiment, the display driving method is used to control the display driving circuit, and the display driving circuit includes the display driving circuits in Embodiment 1 and Embodiment 2. This embodiment is described by taking the display driving method for controlling the display driving circuit in Embodiment 2 as an example, and the control module 190 is used to execute the display driving method.

[0092] See Figure 8 As shown, the display driving method includes:

[0093] S100: Obtain the comparison result of the voltage of the comparison feedback signal line 160 of the comparison module 140 and the reference voltage Vr;

[0094] S200: At least control one of the timing controller 180 and the power management chip 150 to adjust the driving ability of the scan signal according to the comparison result.

[0095] It should be noted that the driving ability of the scan signal can be adjusted by controlling the power management chip 150, or the timing controller 180 can be controlled, and the timing controller 180 controls the level conversion chip 110 to adjust the driving ability of the scan signal. It is also possible to control both the power management chip 150 and the timing controller 180 to adjust the driving ability of the scan signal simultaneously. It depends on the specific situation.

[0096] The control module 190 controls the timing controller 180 and the power management chip 150 according to the comparison result to jointly adjust the driving ability of the scan signal, which can make the adjustment range of the scan signal larger.

[0097] Exemplarily, controlling the timing controller 180 to adjust the driving ability of the scan signal includes:

[0098] When it is confirmed that the voltage of the feedback signal line 160 is less than the reference voltage Vr, control the timing controller 180 to increase the duty cycle of the clock signal CK output by the level conversion chip 110;

[0099] When it is confirmed that the voltage of the feedback signal line 160 is greater than the reference voltage Vr, control the timing controller 180 to decrease the duty cycle of the clock signal CK output by the level conversion chip 110.

[0100] By controlling the level conversion chip 110 through the timing controller 180 to adjust the duty cycle of the clock signal CK, and then adjusting the driving ability of the scan signal, it is possible to avoid the high-level signal VGH being too high or too low.

[0101] Controlling the power management chip 150 to adjust the driving ability of the scan signal includes:

[0102] When it is confirmed that the voltage of the feedback signal line 160 is less than the reference voltage Vr, control the power management chip 150 to increase the high-level signal VGH;

[0103] When it is confirmed that the voltage of the feedback signal line 160 is greater than the reference voltage Vr, control the power management chip 150 to decrease the high-level signal VGH.

[0104] By adjusting the high-level signal VGH through the power management chip 150, and then adjusting the driving ability of the scan signal, it is possible to avoid the adjustment range of the scan signal being limited by only adjusting the clock signal CK.

[0105] Embodiment 5

[0106] The present application also provides a display device. As shown in Figure 9 , the display device includes a display driving circuit and a display panel 200. The scanning lines of the display panel 200 are connected to the gate driving module 120 of the display driving circuit. The display driving circuit includes the display driving circuits disclosed in Embodiment 1 and Embodiment 2.

[0107] The display device includes a display driving circuit. In the display driving circuit, the level conversion chip 110 is connected to at least the first-stage gate driving module 120. The delay module 130 is connected to a gate driving module 120 through a feedback signal line 160 and is used for delaying the output of a control signal after receiving a signal. The comparison module 140 is connected to the feedback signal line 160 and the delay module 130 and is used for comparing the voltage of the feedback signal line 160 with a reference voltage Vr. The power management chip 150 is connected to the comparison module 140 and the level conversion chip 110 and is used for adjusting the high-level signal VGH according to the comparison result of the comparison module 140 and outputting it to the level conversion chip 110. Since the level conversion chip 110 drives the gate driving module 120 by outputting a scanning driving signal according to the high-level signal VGH, adjusting the high-level signal VGH can adjust the driving ability of the scanning signal and reduce the risk of abnormal display.

[0108] As shown in FIG. 9, the level conversion chip 110, the delay module 130, the comparison module 140, and the power management chip 150 are all disposed on the main board 100. When the gate driving module 120 of the display driving circuit includes a GDL unit, the GDL unit is disposed on the display panel 200.

[0109] The gate driving module 120 includes a GDL unit, that is, the gate driving adopts GDL technology, thereby reducing the use of gate driving chips, reducing the manufacturing cost of the display driving circuit, and further reducing the manufacturing cost of the display device.

[0110] It should be noted that the level conversion chip 110, the delay module 130, the comparison module 140, and the power management chip 150 may all be disposed on the main board 100, but are not limited thereto. The level conversion chip 110, the delay module 130, the comparison module 140, and the power management chip 150 may also all be disposed on a horizontal circuit board, which can be determined according to the specific situation.

[0111] The terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0112] In this application, unless otherwise clearly specified or limited, terms such as "assembly" and "connection" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0113] In the description of this specification, the descriptions referring to terms such as "some embodiments" and "exemplarily" mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0114] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and the description of this application shall fall within the scope covered by the patent of this application.

Claims

1. A display driving circuit includes a plurality of cascaded gate driving modules. The gate driving modules are configured to output a scan signal to a scan line of a display panel and a next-stage gate driving module in response to a scan driving signal, characterized in that The display driving circuit further includes: a delay module, connected to one of the gate driving modules through a feedback signal line, for delaying the output of a control signal after receiving a signal; a comparison module, connected to the feedback signal line and the delay module, for comparing the voltage of the feedback signal line with a reference voltage; a level conversion chip, connected to at least the first-stage gate driving module, and the level conversion chip can output the corresponding scan driving signal according to the level of the high-level signal; a power management chip, connected to the comparison module and the level conversion chip, for adjusting the high-level signal according to the comparison result of the comparison module and outputting it to the level conversion chip, and adjusting the high-level signal can adjust the scan driving signal to adjust the driving ability of the scan signal.

2. The display driving circuit according to claim 1, wherein The display driving circuit further includes a voltage trigger, the voltage trigger is connected to the feedback signal line and the delay module, and the voltage trigger is used for receiving the scan signal of the feedback signal line and outputting a trigger signal to the delay module when the voltage of the feedback signal line is greater than a preset voltage.

3. The display driving circuit according to claim 1 or 2, characterized in that The display driving circuit includes n gate driving modules, each gate driving module includes a GDL unit, and the n GDL units are cascaded in sequence, and the GDL units are arranged on the display panel; The display panel includes n rows of scan lines, and the n GDL units are respectively connected to the n rows of scan lines one by one, and the level conversion chip is connected to the first-stage GDL unit, and n is an integer greater than 1.

4. The display driving circuit according to claim 3, wherein The feedback signal line is connected to the first-stage GDL unit or the feedback signal line is connected to the nth-stage GDL unit.

5. The display driving circuit according to claim 3, wherein The first-stage gate driving module further includes a sampling unit, the sampling unit and the GDL unit of the first-stage gate driving module are both connected to the level conversion chip, the sampling unit is connected to the feedback signal line, and the sampling unit is a GDL unit.

6. The display driving circuit according to claim 1, wherein The display driving circuit further includes: a timing controller and a control module, the comparison module, the control module, the timing controller and the level conversion chip are connected in sequence, the control module is further connected to the power management chip, and the control module is used for controlling at least one of the timing controller and the power management chip to adjust the driving ability of the scan signal according to the comparison result. The scan driving signal includes a clock signal, the timing controller adjusts the driving ability of the scan signal by adjusting the clock signal output by the level conversion chip, and the power management chip adjusts the driving ability of the scan signal by adjusting the high-level signal.

7. A display driving method, characterized in that, For controlling a display driving circuit, the display driving circuit includes a gate driving module, a delay module, a comparison module, a timing controller, a level conversion chip, and a power management chip. A plurality of the gate driving modules are cascaded. The gate driving module is configured to output a scan signal to a scan line of a display panel and a next-stage gate driving module in response to a scan driving signal. The timing controller and the power management chip are both connected to the level conversion chip. The level conversion chip is connected to at least a first-stage gate driving module. The level conversion chip can output the corresponding scan driving signal according to the level of a high-level signal. The delay module is connected to a gate driving module through a feedback signal line and is configured to delay and output a control signal after receiving a signal. The comparison module is connected to the delay module and the feedback signal line and is configured to compare the voltage of the feedback signal line with a reference voltage. The display driving method includes: Obtaining a comparison result of the comparison module comparing the voltage of the feedback signal line with the reference voltage; At least controlling one of the timing controller and the power management chip to adjust the driving ability of the scan signal according to the comparison result. The power management chip can adjust the high-level signal according to the comparison result. By adjusting the high-level signal, the scan driving signal can be adjusted to adjust the driving ability of the scan signal. The timing controller can adjust the scan driving signal output by the level conversion chip according to the comparison result to adjust the driving ability of the scan signal.

8. The display driving method according to claim 7, wherein, The scan driving signal includes a clock signal. Controlling the timing controller to adjust the driving ability of the scan signal includes: When it is confirmed that the voltage of the feedback signal line is less than the reference voltage, controlling the timing controller to increase the duty cycle of the clock signal output by the level conversion chip; When it is confirmed that the voltage of the feedback signal line is greater than the reference voltage, controlling the timing controller to decrease the duty cycle of the clock signal output by the level conversion chip.

9. The display driving method according to claim 8, wherein The power management chip is at least configured to output the high-level signal to the level conversion chip. Controlling the power management chip to adjust the driving ability of the scan signal includes: When it is confirmed that the voltage of the feedback signal line is less than the reference voltage, controlling the power management chip to increase the high-level signal; When it is confirmed that the voltage of the feedback signal line is greater than the reference voltage, controlling the power management chip to decrease the high-level signal.

10. A display device, characterized in that, Including: The display driving circuit according to any one of claims 1 to 6; A display panel, wherein a scan line of the display panel is connected to the gate driving module of the display driving circuit.

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