A method of manufacturing a semiconductor device

Abstract

The application provides a manufacturing method of a semiconductor device, which comprises the following steps: forming a self-aligned metal silicide on the surface of a semiconductor substrate by a silicide process; and forming a high-k dielectric layer and a metal gate, so that the high-k dielectric layer and the metal gate can avoid all high-temperature steps in the previous process, thereby solving the problems of reliability and mobility degradation of the high-k dielectric layer and the metal gate after high-temperature treatment; and the metal silicide TiSi2 with lower resistivity and higher thermal stability is used as the local interconnection of the semiconductor device, which is helpful to improve the reliability of the semiconductor device. Compared with the mainstream post-gate process (the post-gate needs to be matched with a post-metal silicide process, and a contact hole process needs to be changed into a groove and hole process of a metal layer) of the current advanced process, the application does not need a post-metal silicide process, and uses a common contact hole process in a mature process, so the process complexity is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and more specifically to a method for manufacturing a semiconductor device. Background Technology

[0002] As the feature size of CMOS devices continues to shrink, traditional silicon dioxide dielectric layers suffer from problems such as large gate leakage current. Therefore, high-k metal gate (HKMG) has been proposed to replace the traditional gate structure with silicon dioxide as the dielectric layer.

[0003] In existing technologies, the fabrication of 28nm feature size devices generally employs a high-k first, gate last process. This involves first forming a high-k gate oxide layer and a dummy gate electrode on the substrate, followed by source / drain ion doping, high-temperature annealing, and self-aligned metal silicide processes. Finally, the dummy gate electrode is etched away to form a trench, which is then filled with a suitable metal to form the metal gate. However, in this method, the high-k gate dielectric layer experiences reliability and mobility degradation after high-temperature annealing, thus affecting the stability of the device. For the fabrication of 20nm and smaller feature size devices, a high-k last, gate last process is generally used. This involves placing the formation of the high-k gate dielectric layer and the metal gate after the removal of the dummy gate electrode. Furthermore, the necessary high-temperature annealing process for the high-k gate dielectric layer significantly impacts the thermal stability of the self-aligned metal silicide. Therefore, the metal silicide process is placed after the metal gate formation (all last process, i.e., High-k last, Gate Last, Salicide last), which significantly increases the process complexity. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention provides a method for manufacturing a semiconductor device. A dummy gate electrode is formed on a substrate, and after ion doping and high-temperature annealing of the source / drain electrodes, a self-aligned metal silicide is first formed on the surface of the semiconductor substrate using a silicide process. Then, the dummy gate electrode is removed, forming a post-high-k gate dielectric layer and a metal gate. This avoids all the high-temperature processes in the preceding stages of the high-k gate dielectric layer and metal gate, thereby solving the problem of reliability and mobility degradation that occurs after high-temperature processing of the high-k gate dielectric layer and metal gate. Using TiSi2, a metal silicide with low resistivity and high thermal stability, as the local interconnect of the semiconductor device helps improve the reliability of the semiconductor device. Furthermore, compared with the post-high-k process in the prior art, the present invention does not require placing the metal silicide process after the metal gate formation, simplifying the process flow.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] S1: A semiconductor substrate is provided, on which a dummy gate structure is formed;

[0007] S2: A self-aligned metal silicide is formed on the surface of the semiconductor substrate;

[0008] S3: Remove the dummy gate structure to expose the semiconductor substrate to form a groove;

[0009] S4: A gate structure is formed in the groove.

[0010] Optionally, the semiconductor substrate is a Si substrate.

[0011] Optionally, between step S1 and step S2, the semiconductor substrate may be pre-amorphized by bombarding its surface with heavy ions.

[0012] Optionally, the heavy ion is selected from one of Xe ions, Ge ions, Si ions, and Ar ions.

[0013] Optionally, step S2 includes the following steps:

[0014] S21: A Ti metal layer is deposited on the surface of the semiconductor substrate;

[0015] S22: Perform a first annealing process to form TiSi2 on the surface of the semiconductor substrate;

[0016] S23: Wet etching removes unreacted Ti metal.

[0017] Optionally, the temperature of the first annealing treatment is 450℃~650℃.

[0018] Optionally, between step S2 and step S3, an interlayer dielectric layer is further formed on the surface of the semiconductor substrate, the interlayer dielectric layer covering the sidewalls of the dummy gate structure.

[0019] Optionally, after step S4, the method further includes: forming a contact hole in the interlayer dielectric layer and filling the contact hole with a metallic material to form a contact.

[0020] Optionally, step S4 includes the following steps:

[0021] A high-k gate dielectric layer is formed at the bottom of the groove;

[0022] A gate is formed by filling the groove with conductive material, and the gate covers the gate dielectric layer.

[0023] Optionally, after forming the high-k gate dielectric layer, a second annealing process is also performed at a temperature of 750℃ to 950℃.

[0024] Optionally, after step S2, a third annealing process is performed at a temperature of 750℃ to 950℃.

[0025] Optionally, the gate is a metal gate.

[0026] The semiconductor device manufacturing method provided by this invention has at least the following technical effects:

[0027] The semiconductor device manufacturing method provided by this invention first uses a silicide process to form a self-aligned metal silicide on the surface of a semiconductor substrate, and then forms a high-k gate dielectric layer and a metal gate. This avoids the high-temperature steps in the previous process for the high-k gate dielectric layer and the metal gate, thereby solving the problem of reliability and mobility degradation that occurs after the high-k gate dielectric layer and the metal gate are exposed to high temperatures. Using TiSi2 metal silicide, which has low resistivity and high thermal stability, as the local interconnect of the semiconductor device helps to improve the reliability of the semiconductor device. In addition, compared with the post-high-k process in the prior art, this invention does not require the metal silicide process to be placed after the metal gate formation, and uses the contact hole process commonly used in mature processes, making the process flow simple. Attached Figure Description

[0028] Figure 1 The flowchart shown is a process for manufacturing a semiconductor device provided in Example 1.

[0029] Figure 2 The diagram shows a schematic of the substrate provided in step S1 of Example 1.

[0030] Figure 3 Displayed as in Figure 2 The diagram shows a structure in which a metal layer is formed on the substrate surface.

[0031] Figure 4 Displayed as in Figure 3 The diagram shows a structure in which metal silicides are formed on the substrate surface.

[0032] Figure 5 Displayed as in Figure 4 The diagram shows a structure with an interlayer dielectric layer formed on top of the structure shown.

[0033] Figure 6 The diagram shows a structural schematic of the groove formed in step S3 of Embodiment 1.

[0034] Figure 7 Displayed as in Figure 6 The diagram shows a structure in which a gate dielectric layer is formed in the groove.

[0035] Figure 8 Displayed as in Figure 7 A schematic diagram of the structure in which the gate is formed.

[0036] Figure 9 Displayed as in Figure 8 The diagram shows a structure in which contact holes are formed and filled.

[0037] Component designation explanation

[0038] 10 Semiconductor substrate

[0039] 11 Source / Leakage Zone

[0040] 12 STI Structure

[0041] 13. Pseudo-gate structure

[0042] 14 Side walls

[0043] 15 Metal Layers

[0044] 16 Metal silicides

[0045] 17 Interlayer dielectric layer

[0046] 18 Gate dielectric layer

[0047] 19 Gate

[0048] 100 grooves

[0049] 200 contact hole Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0052] Example 1

[0053] This embodiment provides a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it includes the following steps:

[0054] S1: A semiconductor substrate is provided, on which a dummy gate structure is formed;

[0055] like Figure 2 As shown, a semiconductor substrate 10 is provided. In this embodiment, the semiconductor substrate 10 is a Si substrate. Source / drain regions 11 and an STI structure 12 are formed in the semiconductor substrate 10. The N-type / P-type of the source / drain regions can be selected according to the type of semiconductor device formed. A dummy gate structure 13 is formed on the semiconductor substrate 10. A gate oxide layer (not shown) is also present between the dummy gate structure 13 and the semiconductor substrate 10. A sacrificial protection layer (not shown) is present on the upper surface of the dummy gate 13. As an example, the material of the dummy gate structure can be polycrystalline silicon or amorphous silicon, and the sacrificial protection layer can be SiN or SiO2. Sidewalls 14 are formed on both sides of the dummy gate structure 13. As an example, the material of the sidewalls can be SiN, SiO2, SiCN, and other low-dielectric-constant dielectric materials.

[0056] Next, the surface of the semiconductor substrate 10 is bombarded with heavy ions to perform a pre-amorphization treatment, transforming the Si substrate from a single-crystal state to an amorphous state, which helps to improve the linewidth effect of the subsequently formed metal silicide. As an example, the heavy ions are selected from Xe ions, Ge ions, Si ions, and Ar ions.

[0057] S2: A self-aligned metal silicide is formed on the surface of the semiconductor substrate;

[0058] like Figure 3 As shown, a metal layer 15 is deposited on the surface of the semiconductor substrate 10 to serve as a precursor for forming metal silicides. In this embodiment, the metal layer 15 is a Ti metal layer with a thickness of 7 nm to 15 nm, and the metal layer 15 can be formed using a physical vapor deposition (PVD) method.

[0059] Next, a first annealing process is performed, in which the metal layer 15 reacts with the Si substrate exposed by the source / drain regions 11 in a self-aligned manner to form metal silicide TiSi2, while the metal layer 15 does not react with the sidewalls 14, the STI structure 12, and the dummy gate structure 13. As an example, the temperature of the first annealing process is controlled to be between 450°C and 650°C. The metal silicide TiSi2 formed after this first annealing process is a C49 crystal phase with a high resistivity (70 μΩ·cm to 100 μΩ·cm).

[0060] Finally, the unreacted metal layer 15 is removed by wet etching, ultimately forming metal silicide 16 on the source / drain region 11, such as... Figure 4 As shown.

[0061] S3: Remove the dummy gate structure to expose the semiconductor substrate to form a groove;

[0062] First, such as Figure 5 As shown, an interlayer dielectric layer 17 is deposited on the surface of the semiconductor substrate 10, and the interlayer dielectric layer 17 is planarized by methods such as chemical mechanical polishing (CMP). This planarization process stops at the surface of the dummy gate structure 13, exposing the top of the dummy gate structure 13. Similarly... Figure 5 As shown, the interlayer dielectric layer 17 covers the sidewall of the sidewall 14. As an example, the interlayer dielectric layer 17 can be formed by depositing a layer of doped or undoped silicon oxide, spin-coating an insulating dielectric, or depositing a low-k material using a chemical vapor deposition (CVD) method. As examples, doped silicon oxide includes materials such as borosilicate glass (BSG), phosphosilicate glass (PSG), and borosilicate-phosphosilicate glass (BPSG); low-k materials include, but are not limited to, organic low-k materials, inorganic low-k materials, and porous low-k materials, etc. The specific material selection depends on the technology node and requirements of the device.

[0063] Next, as Figure 6 As shown, the dummy gate structure 13 in the interlayer dielectric layer 17 is removed, while the sidewalls 14 on both sides of the dummy gate structure 13 are retained, exposing the semiconductor substrate 10 and forming a recess 100. As an example, the dummy gate structure 13 can be removed using dry etching, wet etching, or a combination of both. For example, dry etching can be performed using F-based and Cl-based gases or HBr / Cl2-based gases, or wet etching can be performed using TMAH. As an example, the gate oxide layer (not shown in the figure) between the dummy gate structure 13 and the semiconductor substrate 10 also needs to be removed, using SiCoNi or Cetas or a wet process to avoid damaging the substrate.

[0064] S4: A gate structure is formed in the groove.

[0065] First, a gate oxide layer is grown on the surface of the above structure to improve the surface quality of the gate dielectric layer 18 grown in subsequent processes. The gate oxide layer can be made of SiO2. As an example, for the 28nm process node, the ISSG process is used for growth, and for the 14nm and below process nodes, the wet process is used for growth.

[0066] Next, as Figure 7 As shown, a gate dielectric layer 18 is deposited on the surface of the above structure. In this embodiment, the gate dielectric layer 18 is a high-k gate dielectric layer, such as silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminum oxide.

[0067] Next, a second annealing process is performed at a temperature between 750°C and 950°C. This annealing process improves the quality of the high-k gate dielectric layer and transforms the C49 phase TiSi2 metal silicide into the C54 phase TiSi2. The resistivity of the C54 phase TiSi2 metal silicide is significantly reduced (15 μΩ·cm to 25 μΩ·cm). Using a two-step annealing method (first and second annealing) to form TiSi2 avoids the problem of excessive lateral growth of TiSi2 caused by excessive lateral growth in a single annealing temperature, which can lead to bridging and short circuits between the gate and source / drain regions. Furthermore, the final C54 phase TiSi2 metal silicide exhibits lower resistivity and higher thermal stability, contributing to improved reliability of semiconductor devices.

[0068] Next, a conductive material is deposited on the surface of the above structure, and the conductive material is planarized by methods such as chemical mechanical polishing (CMP) to form a gate 19 in the groove 100, as shown below. Figure 8 As shown.

[0069] Finally, contact holes 200 are formed in the interlayer dielectric layer 17 by photolithography. Metal material is then filled into the contact holes 200 to form contacts, followed by subsequent conventional processes. As an example, the contact holes 200 expose the surface of the metal silicide 16. Ti / TiN / W stacked layer material is filled into the contact holes 200 to form contacts, followed by planarization to ultimately form… Figure 9 The structure shown.

[0070] This embodiment provides a method for manufacturing a semiconductor device. First, a self-aligned metal silicide is formed on the surface of a semiconductor substrate using a silicide process. Then, a high-k gate dielectric layer and a metal gate are formed. This avoids the high-temperature steps in the previous process for the high-k gate dielectric layer and the metal gate, thus solving the problem of reliability and mobility degradation that occurs after the high-k gate dielectric layer and the metal gate reach high temperatures. Using TiSi2, a metal silicide with low resistivity and high thermal stability, as the local interconnect of the semiconductor device helps improve its reliability. Furthermore, compared to the post-high-k process in the prior art, this invention does not require placing the metal silicide process after the metal gate formation and uses the contact hole process commonly used in mature processes, resulting in a simpler process flow.

[0071] Example 2

[0072] This embodiment also provides a method for manufacturing a semiconductor device. The similarities between this embodiment and Embodiment 1 will not be repeated here. The differences are:

[0073] Following step S2, a third annealing process is performed. The temperature of the third annealing process is controlled to be higher than that of the first annealing process, and is kept between 750°C and 950°C. Adding a third annealing process after the first annealing process transforms the C49 phase TiSi2 metal silicide into the C54 phase. The C54 phase TiSi2 metal silicide has lower resistivity (15 μΩ·cm~25 μΩ·cm) and higher thermal stability, which helps improve the reliability of semiconductor devices. Furthermore, the two-step annealing method of first and third annealing processes avoids the problem of excessive lateral growth of TiSi2 caused by excessively high annealing temperature in a single step, which can lead to bridging and short circuits between the gate and source / drain regions. Performing a second annealing process during the subsequent formation of the gate dielectric layer helps ensure that all the final TiSi2 metal silicide is formed in the C54 phase, thus guaranteeing the reliability of the semiconductor device.

[0074] This invention provides a method for manufacturing a semiconductor device. First, a self-aligned metal silicide is formed on the surface of a semiconductor substrate using a silicide process. Then, a high-k gate dielectric layer and a metal gate are formed. This avoids the high-temperature steps in the preceding processes, thus solving the reliability and mobility degradation problems that occur after high-temperature processing of the high-k gate dielectric layer and metal gate. Using TiSi2, a metal silicide with low resistivity and high thermal stability, as the local interconnect of the semiconductor device helps improve its reliability. Furthermore, compared to the post-high-k processes in existing technologies, this invention eliminates the need to place the metal silicide process after the metal gate formation and employs the commonly used contact hole process in mature technologies, resulting in a simpler process flow.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: S1: A semiconductor substrate is provided, on which a dummy gate structure is formed; S2: A self-aligned metal silicide is formed on the surface of the semiconductor substrate; Step S2 includes: S21: depositing a Ti metal layer on the surface of the semiconductor substrate; S22: Perform a first annealing process to form TiSi2 on the surface of the semiconductor substrate. The temperature of the first annealing process is 450 ℃~650 ℃. S23: Wet etching removes unreacted Ti metal; S3: Remove the dummy gate structure to expose the semiconductor substrate to form a groove; S4: Forming a gate structure in the groove, wherein step S4 includes: A high-k gate dielectric layer is formed at the bottom of the groove, and a second annealing process is performed at a temperature of 750 ℃ ​​to 950 ℃. A gate is formed by filling the groove with conductive material, and the gate covers the high-k gate dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The semiconductor substrate is a Si substrate.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Between step S1 and step S2, the process further includes: bombarding the surface of the semiconductor substrate with heavy ions to perform a pre-amorphization treatment on the semiconductor substrate.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The heavy ion is selected from one of Xe ions, Ge ions, Si ions, and Ar ions.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Between steps S2 and S3, an additional step is taken: forming an interlayer dielectric layer on the surface of the semiconductor substrate, the interlayer dielectric layer covering the sidewalls of the dummy gate structure.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, Step S4 is followed by: forming a contact hole in the interlayer dielectric layer and filling the contact hole with a metallic material to form a contact.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Step S2 is followed by a third annealing process, with an annealing temperature of 750℃~950℃.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The gate is a metal gate.

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