Encapsulation substrate and manufacturing method thereof

Abstract

A packaging substrate and its manufacturing method include wrapping a circuit layer and conductive pillars on the circuit layer with an insulating layer, then forming grooves in the insulating layer corresponding to the conductive pillars to form a wiring layer in the grooves. Therefore, there is no need to drill blind holes, thereby avoiding the alignment problem of existing circuits and conductive blind holes.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and more particularly to a packaging substrate with embedded traces and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, electronic products are becoming thinner, lighter, and smaller, while their functionality is being developed towards higher performance, greater functionality, and higher speed. Therefore, to meet the demands for high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] like Figure 1 As shown, the conventional packaging substrate 1 includes a core layer 10 having a plurality of conductive pillars 100, a plurality of dielectric layers 11 respectively arranged on opposite sides of the core layer 10, and a circuit layer 12 arranged on each of the dielectric layers 11, so that the circuit layers 12 located on opposite sides of the core layer 10 are electrically connected through the plurality of conductive pillars 100, wherein the circuit layer 12 is electrically connected to the conductive pillars 100 through conductive blind vias 120.

[0004] However, in the conventional packaging substrate 1, the conductive blind vias 120 are first formed on the dielectric layer 11 by laser, drilling, or other methods, and then the conductive material is filled into these holes. Therefore, during the process of forming the holes, the holes are often offset due to working errors, resulting in the holes not being formed at the intended locations. As a result, the conductive blind vias 120 cannot effectively connect the conductive pillars 100 and the circuit layer 12, resulting in poor electrical connection of the packaging substrate 1.

[0005] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0006] In view of the above-mentioned deficiencies in the prior art, the present invention provides a packaging substrate and a manufacturing method thereof, which can avoid the alignment problem of the existing circuits and conductive blind vias.

[0007] The packaging substrate of the present invention includes: an insulating layer having a groove formed on one side thereof; a circuit layer embedded in the other side of the insulating layer; a conductive column embedded in the insulating layer to connect to the circuit layer; and a wiring layer formed in the groove to connect to the conductive column.

[0008] The present invention also provides a method for manufacturing a packaging substrate, comprising: sequentially forming a circuit layer and at least one conductive column on a carrier; forming an insulating layer on the carrier so that the insulating layer covers the circuit layer and the conductive column; forming a stopping layer having multiple hollow areas on the insulating layer so that part of the surface of the insulating layer is exposed in the hollow areas; forming grooves on the surface of the insulating layer corresponding to the hollow areas so that each conductive column is correspondingly exposed in each groove; removing the stopping layer; and forming a wiring layer in the groove.

[0009] In the aforementioned manufacturing method, the stopping layer is a metal layer.

[0010] The aforementioned manufacturing method further includes performing a build-up operation on the wiring layer.

[0011] The aforementioned packaging substrate and its manufacturing method further include forming an alignment portion on the insulating layer to cover the wiring layer when forming the wiring layer in the groove. For example, the alignment portion and the wiring layer are formed integrally.

[0012] In the aforementioned packaging substrate and its manufacturing method, the wiring layer is flush with the surface of the insulating layer.

[0013] As can be seen from the above, in the packaging substrate and its manufacturing method of the present invention, a groove is formed mainly by forming the insulating layer corresponding to the conductive column to form a wiring layer in the groove. Therefore, compared with the existing technology, the present invention does not need to drill holes to form blind holes, thereby avoiding the alignment problem of the existing circuit and conductive blind holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a cross-sectional schematic diagram of an existing packaging substrate.

[0015] Figures 2A to 2I It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0016] Figure 2J for Figure 2I A cross-sectional schematic diagram of another method of manufacturing the present invention.

[0017] Figure 2K for Figure 2I A partially enlarged top view of the diagram.

[0018] Figures 3A to 3B for Figure 2I A cross-sectional schematic diagram of the subsequent process.

[0019] The description of the accompanying drawings is as follows:

[0020] 1, 2, 2a, 3 package substrate

[0021] 10 core layers

[0022] 100, 22 conductive columns

[0023] 11 Dielectric layer

[0024] 12, 21 circuit layers

[0025] 120 conductive blind vias

[0026] 20 bearing parts

[0027] 23, 33 insulation layer

[0028] 230, 330 grooves

[0029] 24 stop layers

[0030] 240 hollow area

[0031] 25, 35 wiring layers

[0032] 25a Metal materials

[0033] 25b seed layer

[0034] 250 blind hole

[0035] Route 251

[0036] 26 Positioning Department

[0037] 27 photoresist

[0038] 38 insulation protection layer

[0039] 380 openings

[0040] 39 pad

[0041] 390 surface treatment layer. DETAILED DESCRIPTION

[0042] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0043] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those familiar with this technology, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose of the present invention. At the same time, the terms such as "upper", "lower" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be considered as the scope of the implementation of the present invention without substantially changing the technical content.

[0044] Figures 2A to 2I Schematic cross-sectional view of a method for manufacturing a package substrate 2 of the present invention. In this embodiment, the package substrate 2 is an embodiment with a core layer (core) or a coreless layer (coreless).

[0045] like Figure 2A As shown, a circuit layer 21 and at least one conductive pillar 22 are sequentially formed on the carrier 20 .

[0046] In this embodiment, the carrier 20 is a consumable material such as a temporary carrier, and the circuit layer 21 and the conductive pillars 22 can be formed by electroplating copper. For example, the circuit layer 21 is first formed on the carrier 20, and then a patterned photoresist (not shown) is formed on the carrier 20 and the circuit layer 21, so that a portion of the circuit layer 21 is exposed by the patterned photoresist. The conductive pillars 22 are then formed on the exposed surface of the circuit layer 21, and finally, the patterned photoresist is removed.

[0047] like Figure 2B As shown, an insulating layer 23 is formed on the carrier 20 so that the insulating layer 23 covers the circuit layer 21 and the conductive pillar 22 .

[0048] In this embodiment, the insulating layer 23 is formed of a material such as Ajinomoto Build-up Film (ABF) or other suitable dielectric materials. For example, the insulating layer 23 is formed on the carrier 20 by lamination.

[0049] like Figure 2C As shown, a stopping layer 24 having a plurality of hollow regions 240 is formed on the insulating layer 23 , so that a portion of the surface of the insulating layer 23 is exposed in the hollow regions 240 .

[0050] In this embodiment, the material forming the stopping layer 24 is copper or other suitable metal materials. For example, copper is first formed on the entire top surface of the insulating layer 23 by sputtering. Then, a patterned photoresist (not shown) is formed on the copper material. An exposure and development process is performed to partially expose the copper material through the patterned photoresist. The copper material exposed through the patterned photoresist is then etched away to form the hollow region 240. Finally, the patterned photoresist is stripped, leaving the remaining copper material as the stopping layer 24.

[0051] like Figure 2D As shown, a groove 230 is formed on the surface of the insulating layer 23 corresponding to the hollow area 240 , so that each of the conductive pillars 22 is exposed in a portion of the groove 230 .

[0052] In this embodiment, plasma or chemical etching is used to remove a portion of the insulating layer 23 to form the groove 230 .

[0053] like Figure 2E As shown, the stop layer 24 is removed by etching to expose the insulating layer 23 , and then a desmearing operation is performed on the surfaces of the insulating layer 23 and the groove 230 .

[0054] like Figures 2F to 2G As shown, a metal material 25 a is formed on the insulating layer 23 , and the metal material 25 a is filled into the groove 230 to contact the conductive pillar 22 .

[0055] In this embodiment, a seed layer 25b made of copper, for example, may be formed on the surface of the insulating layer 23 and the surface of the groove 230. Figure 2F As shown, the metal material 25a is formed by electroplating copper material through the seed layer 25b, as shown in FIG. Figure 2G shown.

[0056] like Figure 2H As shown, at least a portion of the metal material 25 a and the seed layer 25 b thereunder on the surface of the insulating layer 23 are removed, while the metal material 25 a and the seed layer 25 b in the groove 230 are retained to serve as the wiring layer 25 .

[0057] In this embodiment, when forming the wiring layer 25 in the groove 230, at least a portion of the metal material 25a and the seed layer 25b thereunder on the surface of the insulating layer 23 may be retained to form an alignment portion 26 on the insulating layer 23 that covers the wiring layer 25. For example, a patterned photoresist 27 may be first formed on a portion of the surface of the metal material 25a, and then the metal material 25a and the seed layer 25b thereunder surrounding the photoresist 27 are removed, so that the metal material 25a and the seed layer 25b below the photoresist 27 form a ring-shaped alignment portion 26. Thus, the alignment portion 26 and the wiring layer 25 are integrally formed.

[0058] Furthermore, the wiring layer 25 is flush with the surface of the insulation layer 23 .

[0059] like Figure 2I As shown, the photoresist 27 is removed to expose the alignment portion 26. In subsequent processes, the carrier 20 can be removed to expose the circuit layer 21 and flush with the surface of the insulating layer 23, as shown in FIG. Figure 2J shown.

[0060] In this embodiment, if the wiring layer 25 is the outermost circuit configuration, the alignment portion 26 can be omitted. Figure 2G After the metal material 25a is formed as shown, the metal material 25a on the surface of the insulating layer 23 is removed to obtain the Figure 2J The package substrate 2a is shown.

[0061] Therefore, the manufacturing method of the present invention uses the conductive pillar 22 to raise the circuit structure, and then forms the groove 230 and the embedded circuit (ie, the wiring layer 25) on the insulating layer 23 by plasma or chemical etching, thereby eliminating the traditional laser drilling process.

[0062] Furthermore, the manufacturing method of the present invention first forms the groove 230 by using the stop layer 24 so that the wiring layer 25 can be embedded in the insulating layer 23, which is beneficial for the design of fine pitch / fine circuit.

[0063] Furthermore, the wiring layer 25 and the blind hole portion 250 (which is connected to the conductive pillar 22) are formed in the same layer. Figure 2K As shown, the position tolerance problem of the circuit 251 and the blind hole portion 250 can be avoided, so the design landless specification (such as Figure 2J As shown, the width of the blind hole portion 250 is smaller than the width of the conductive pillar 22 to improve the wiring density.

[0064] In addition, in other embodiments, the Figure 2I Repeat the process shown Figures 2B to 2I The process is to perform a layer-building operation to form a plurality of wiring layers 35, such as Figure 3A As shown, an insulating protection layer 38 having a plurality of openings 380 may be formed on the outermost insulating layer 33, as shown in FIG. Figure 3B The package substrate 3 shown in FIG. For example, the metal material originally intended to form the alignment portion on the outermost wiring layer 35 can be designed to form a plurality of pads 39 exposed in the openings 380 to serve as contacts. Furthermore, a surface treatment layer 390 can be formed on the pads 39 in the openings 380.

[0065] Therefore, the manufacturing method of the present invention can accurately form the groove 330 of the insulating layer 33 at a predetermined position during the build-up operation by designing the alignment portion 26 , thereby avoiding the problem of misalignment caused by working errors.

[0066] Furthermore, embedded circuits (ie, the wiring layer 35 ) can be fabricated in any layer of the build-up operation, thereby improving the adhesion of the wiring layer 35 to avoid scratches during the manufacturing process and enhance reliability.

[0067] It should be understood that the present invention can form the alignment portion 26 according to the requirements of the build-up operation without any particular limitation.

[0068] The present invention provides a packaging substrate 2, 2a, 3, comprising: an insulating layer 23 having two opposite sides, a circuit layer 21 embedded in the insulating layer 23, at least one conductive column 22 embedded in the insulating layer 23, and at least one wiring layer 25 embedded in the insulating layer 23.

[0069] The insulating layer 23 has a groove 230 formed on one side thereof.

[0070] The circuit layer 21 is embedded in the other side of the insulating layer 23 .

[0071] The conductive pillars 22 are embedded in the insulating layer 21 to connect to the circuit layer 21 .

[0072] The wiring layer 25 is formed in the groove 230 to connect the conductive pillar 22 .

[0073] In one embodiment, the package substrates 2 and 3 further include at least one alignment portion 26 disposed on the insulating layer 21 to cover the wiring layer 25. For example, the alignment portion 26 and the wiring layer 25 are integrated.

[0074] In one embodiment, the wiring layer 25 is flush with the surface of the insulation layer 23 .

[0075] In summary, the packaging substrate and its manufacturing method of the present invention, through the design of the groove, enables the wiring layer to be embedded in the insulating layer, thereby eliminating the existing drilling process. Therefore, the present invention is not only conducive to the design of fine pitch / fine lines, but also avoids the alignment problem of existing lines and conductive blind vias.

[0076] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. A packaging substrate, comprising: an insulating layer having a groove formed on one side thereof; a circuit layer embedded in and flush with the other side of the insulating layer; at least one conductive pillar embedded in the insulating layer to connect to the circuit layer; and A wiring layer includes a blind hole portion and a circuit formed in the groove, wherein the blind hole portion is connected to the circuit layer embedded and flush with the other side of the insulating layer through the conductive column, the circuit is not connected to the conductive column, and the circuit, the blind hole portion and the conductive column are formed on the same layer to present a pad-free specification, so that the width of the blind hole portion is smaller than the width of the conductive column.

2. The packaging substrate according to claim 1, wherein: The packaging substrate further comprises an alignment portion arranged on the insulating layer and covering the blind hole portion of the wiring layer.

3. The packaging substrate according to claim 2, wherein: The alignment portion and the blind hole portion of the wiring layer are integrated.

4. The packaging substrate according to claim 1, wherein The wiring layer is flush with the surface of the insulating layer.

5. A method for manufacturing a packaging substrate, comprising: forming a circuit layer and at least one conductive column in sequence on the carrier; forming an insulating layer on the carrier so that the insulating layer covers the circuit layer and the conductive pillar; forming a stopper layer having a plurality of hollow regions on the insulating layer so that a portion of the surface of the insulating layer is exposed in the hollow regions; A groove is formed on the surface of the insulating layer corresponding to the hollow area, so that each conductive pillar is exposed in a portion of the groove, and the circuit layer is embedded in the other side of the insulating layer; removing the stopper layer; and A wiring layer is formed in the groove, wherein the wiring layer includes a blind hole portion formed in the groove corresponding to each exposed conductive pillar and a circuit formed in the groove not connected to each conductive pillar, and the blind hole portion is connected to the circuit layer embedded in the other side of the insulating layer through the conductive pillar, and the circuit, the blind hole portion and the conductive pillar are formed on the same layer to present a pad-free specification, so that the width of the blind hole portion is smaller than the width of the conductive pillar.

6. The method for manufacturing a package substrate according to claim 5, wherein: The stopping layer is a metal layer.

7. The method for manufacturing a package substrate according to claim 5, wherein: The manufacturing method further comprises forming an alignment portion covering the blind hole portion of the wiring layer on the insulating layer when forming the wiring layer in the groove.

8. The method for manufacturing a package substrate according to claim 7, wherein: The alignment portion and the blind hole portion of the wiring layer are formed as one piece.

9. The method for manufacturing a package substrate according to claim 5, wherein: The wiring layer is flush with the surface of the insulating layer.

10. The method for manufacturing a package substrate according to claim 5, wherein: The manufacturing method further includes performing a build-up operation on the wiring layer.

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