A wideband high linearity mixer

Abstract

This invention discloses a wideband high-linearity mixer for use in radio frequency transceiver integrated circuits. The invention comprises a transconductance stage, a switching stage, a load stage, and an output stage. The wideband high-linearity mixer adopts a folded double-balanced architecture to reduce the requirements on the supply voltage. The transconductance stage uses a PMOS differential input pair structure, utilizing the source-level inductor negative feedback effect to improve the third-order intermodulation product and operating bandwidth. The switching stage uses cascode input technology to improve port isolation and mitigate second-order intermodulation, and utilizes resonance technology to improve linearity. The load stage uses long-channel active transistors to achieve high gain. The output stage uses a common-source amplifier structure to increase the driving capability for subsequent circuits. This invention features wide operating bandwidth and high linearity, and can be used in wireless communication radio frequency integrated circuits such as navigation transceivers, satellite communication transceivers, and Bluetooth transceivers.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design, and more specifically to wideband high linearity mixers. Background Technology

[0002] Wireless communication technology is developing rapidly, and people are placing higher demands on the quality of wireless communication, making the need for high-bandwidth and high-transmission-rate technologies increasingly urgent. Ultra-wideband (UWB) wireless systems can carry large amounts of data and have strong anti-interference capabilities, thus the development of UWB wireless communication systems is bound to become a new trend. As the frequency conversion device in a transceiver system, the mixer plays a crucial role. Therefore, mixers with wide bandwidth, high linearity, and low loss characteristics are receiving increasing attention.

[0003] Traditional Gilbert mixers use multiple stacked MOSFETs, which require high power supply voltage. However, the power supply voltage of advanced CMOS processes is concentrated at 1.2V and below, which is difficult for traditional Gilbert mixers to achieve under advanced processes. At the same time, the parasitic capacitance effect in CMOS processes becomes more and more obvious as the frequency increases, making it difficult for traditional Gilbert mixers to achieve broadband.

[0004] Therefore, this invention proposes a wideband, high-linearity mixer that meets the requirements of advanced CMOS process technology, based on the traditional Gilbert mixer, to adapt to the needs of wideband wireless communication. Summary of the Invention

[0005] The present invention addresses the requirements of mixers in the above-mentioned application scenarios by proposing a wideband high linearity mixer.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: A wideband high linearity mixer sequentially comprises a transconductance stage, a switching stage, a load stage, and an output stage. The wideband high linearity mixer adopts a folded double-balanced architecture, reducing the requirements for supply voltage and minimizing output spectrum interference signals. The transconductance stage uses a PMOS differential input pair structure to convert the RF voltage signal into a current form. The source-level inductor negative feedback effect enhances the third-order intermodulation product of the transconductance stage to achieve high linearity, while simultaneously offsetting some parasitic capacitance of the PMOS differential input pair, reducing high-frequency effects and improving the operating bandwidth. The switching stage uses common-source common-gate input technology to improve port isolation and mitigate the second-order intermodulation phenomenon caused by signal feedthrough. Resonance technology reduces the third-order and second-order intermodulation products introduced by the switching pair, thereby improving linearity. The load stage uses a long-channel active transistor to convert the current signal into a voltage signal, achieving high gain. The output stage uses a common-source amplifier structure to improve the mixer's output swing and increase the driving capability for subsequent circuits. This invention features wide operating bandwidth and high linearity, and can be used in wireless communication radio frequency integrated circuits such as navigation transceivers, satellite communication transceivers, and Bluetooth transceivers.

[0007] The transconductance stage includes PMOS transistors MP1, MP2, and MP3, and inductors L1, L2, L3, and L4;

[0008] The switching stage includes NMOS transistors MN3, MN4, MN5, MN6, MN7, and MN8; resistors R1, R2, R3, R4, R5, and R6; capacitors C1, C2, C3, and C4; and inductors L5 and L6.

[0009] The load stage includes PMOS transistors MP4 and MP5, and resistors R7 and R8.

[0010] The output stage includes PMOS transistors MP6 and MP7, NMOS transistors MN9 and MN10, and resistors R9 and R10.

[0011] In this configuration, the source of PMOS transistor MP1 is connected to the power supply, the gate is connected to the bias voltage VB1, and the drain is connected to the right end of inductor L1 and the left end of inductor L2. The source of PMOS transistor MP2 is connected to the left end of inductor L1, the gate is connected to the input voltage VIN+, and the drain is connected to the upper end of inductor L3 and the source of NMOS transistor MN4. The source of PMOS transistor MP1 is connected to the right end of inductor L2, the gate is connected to the input voltage VIN-, and the drain is connected to the upper end of inductor L4 and the source of NMOS transistor MN3. The lower ends of inductors L3 and L4 are connected to ground. The gate of NMOS transistor MN3...

[0012] The drain of NMOS transistor MN4 is connected to the left end of resistor R1, and the drain of MN4 is connected to the left end of inductor L5 and the source of NMOS transistors MN5 and MN6. The gate of NMOS transistor MN4 is connected to the right end of resistor R2, and the drain of MN4 is connected to the right end of inductor L6 and the source of NMOS transistors MN7 and MN8. The right end of resistor R1 and the left end of R2 are both connected to the bias voltage VB6. The right end of inductor L5 is connected to the left end of inductor L6. The gate of NMOS transistor MN5 is connected to the upper plate of capacitor C1 and the lower end of resistor R3. The drain of MN4 is connected to the NMOS transistor... The drain of transistor MN7, the drain of PMOS transistor MP4, the gate of PMOS transistor MP6, and the left end of resistor R7 are connected. The lower plate of capacitor C1 is connected to the local oscillator signal LO+. The upper end of resistor R3 is connected to the bias voltage VB2. The gate of NMOS transistor MN6 is connected to the upper plate of capacitor C2 and the lower end of resistor R4. The gate of NMOS transistor MN7 is connected to the upper plate of capacitor C3 and the lower end of resistor R5. The gate of NMOS transistor MN7 is connected to the upper plate of capacitor C4 and the lower end of resistor R6. The drain of NMOS transistor MN7 is connected to the drain of MN6. The drain of PMOS transistor MN5, the gate of MP7, and the right end of resistor R8 are connected together. The lower plate of capacitor C4 is connected to the local oscillator signal LO+. The upper end of resistor R6 is connected to the bias voltage VB4. The upper ends of resistors R4 and R5 are both connected to the bias voltage VB3. The lower plates of capacitors C2 and C3 are both connected to the local oscillator signal LO-. The source of PMOS transistor MP4 is connected to the power supply. The gate of MP4 is connected to the gate of PMOS transistor MP5, the right end of resistor R7, and the left end of resistor R8. PMOS transistor M... The source of P5 is connected to the power supply voltage. The sources of PMOS transistors MP6 and MP7 are also connected to the power supply voltage. The drain of MP6 is connected to the drain of NMOS transistor MN9. The drain of MP7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN9 is connected to the left end of resistor R9, and its source is connected to ground. The gate of NMOS transistor MN10 is connected to the right end of resistor R10, and its source is connected to ground. The right end of resistor R9 and the left end of resistor R10 are both connected to the bias voltage VB5.

[0013] The advantages of this invention compared to the prior art are:

[0014] 1. The mixer in this invention can achieve an operating frequency band of 0.1 to 6 GHz;

[0015] 2. The mixer in this invention can achieve third-order input intermodulation of 15dBm. Attached Figure Description

[0016] Figure 1 A schematic diagram of a conventional Gilbert mixer in the background technology of this invention.

[0017] Figure 2 A schematic diagram of the wideband high linearity mixer circuit structure of the present invention. Detailed Implementation

[0018] The invention will now be described in detail with reference to the accompanying drawings. The wideband high-linearity mixer of the present invention includes a transconductance stage, a switching stage, a load stage, and an output stage. Compared with a conventional Gilbert mixer (… Figure 1 Compared to traditional Gilbert mixers, this invention's wideband high-linearity mixer employs a folded architecture, which is more suitable for low supply voltages compared to the transistor stacking architecture of traditional Gilbert mixers. The transconductance stage uses a PMOS differential input pair structure to convert the RF voltage signal into current, utilizing the source-level inductor negative feedback effect to improve the third-order intermodulation product of the transconductance stage to achieve high linearity, while simultaneously offsetting some parasitic capacitance of the PMOS differential input pair, reducing high-frequency effects and improving the operating bandwidth. The switching stage uses cascode input technology to improve port isolation and mitigate the second-order intermodulation phenomenon caused by signal feedthrough effect, utilizing resonance technology to reduce the third-order and second-order intermodulation products introduced by the switching pair, thereby improving linearity. The load stage uses long-channel active transistors to convert current signals into voltage signals, achieving high gain. The output stage uses a common-source amplifier structure to improve the mixer's output swing and increase the driving capability for subsequent circuits.

[0019] Figure 2 The overall circuit structure of the wideband high linearity mixer in this invention includes the following: the transconductance stage comprises PMOS transistors MP1, MP2, and MP3, and inductors L1, L2, L3, and L4; the switching stage comprises NMOS transistors MN3, MN4, MN5, MN6, MN7, and MN8, resistors R1, R2, R3, R4, R5, and R6, capacitors C1, C2, C3, and C4, and inductors L5 and L6; the load stage comprises PMOS transistors MP4 and MP5, and resistors R7 and R8; and the output stage comprises PMOS transistors MP6 and MP7, NMOS transistors MN9 and MN10, and resistors R9 and R10.

[0020] In this configuration, the source of PMOS transistor MP1 is connected to the power supply, the gate is connected to the bias voltage VB1, and the drain is connected to the right end of inductor L1 and the left end of inductor L2. The source of PMOS transistor MP2 is connected to the left end of inductor L1, the gate is connected to the input voltage VIN+, and the drain is connected to the upper end of inductor L3 and the source of NMOS transistor MN4. The source of PMOS transistor MP1 is connected to the right end of inductor L2, the gate is connected to the input voltage VIN-, and the drain is connected to the upper end of inductor L4 and the source of NMOS transistor MN3. The lower ends of inductors L3 and L4 are connected to ground. The gate of NMOS transistor MN3 is connected to the left end of resistor R1, and the drain is connected to inductor L5. The left end is connected to the source of NMOS transistors MN5 and MN6. The gate of NMOS transistor MN4 is connected to the right end of resistor R2. The drain is connected to the right end of inductor L6 and the source of NMOS transistors MN7 and MN8. The right end of resistor R1 and the left end of R2 are both connected to the bias voltage VB6. The right end of inductor L5 is connected to the left end of inductor L6. The gate of NMOS transistor MN5 is connected to the upper plate of capacitor C1 and the lower end of resistor R3. The drain is connected to the drain of NMOS transistor MN7, the drain of PMOS transistor MP4, the gate of PMOS transistor MP6, and the left end of resistor R7. The lower plate of capacitor C1 is connected to the local oscillator signal LO+. The upper end of resistor R3 is connected to the bias voltage VB2. The NMOS transistor MN6 gate is connected to the upper plate of capacitor C2 and the lower end of resistor R4. The NMOS transistor MN7 gate is connected to the upper plate of capacitor C3 and the lower end of resistor R5. The NMOS transistor MN7 gate is connected to the upper plate of capacitor C4 and the lower end of resistor R6. The drain of MN7 is connected to the drain of MN6, the drain of PMOS transistor MN5, the gate of MP7, and the right end of resistor R8. The lower plate of capacitor C4 is connected to the local oscillator signal LO+. The upper end of resistor R6 is connected to the bias voltage VB4. The upper ends of resistors R4 and R5 are both connected to the bias voltage VB3. The lower plates of capacitors C2 and C3 are both connected to the local oscillator signal LO-. The PMOS transistor... The source of MP4 is connected to the power supply, and its gate is connected to the gate of PMOS transistor MP5, the right end of resistor R7, and the left end of resistor R8. The source of PMOS transistor MP5 is connected to the power supply voltage. The sources of PMOS transistors MP6 and MP7 are both connected to the power supply voltage. The drain of MP6 is connected to the drain of NMOS transistor MN9, and the drain of MP7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN9 is connected to the left end of resistor R9, and its source is connected to ground. The gate of NMOS transistor MN10 is connected to the right end of resistor R10, and its source is connected to ground. The right end of resistor R9 and the left end of resistor R10 are both connected to the bias voltage VB5.

[0021] Working principle of the invention:

[0022] Traditional Gilbert mixers, due to their large number of transistors stacked together, require a power supply voltage V to ensure that each transistor operates in the saturation region. DD ≥V R +Vdsat3 ~6+V dsat1 ~2+V dsat _ ISS V R V is the DC voltage drop across the load resistors R1 / R2. dsat3 ~6, V dsat1 ~2, V dsat _ ISS The overdrive power supplies are respectively the switching stage, input stage, and bias current source. The wideband high-linearity mixer in this invention employs a folded architecture, which, compared to the traditional Gilbert mixer, reduces the number of stacked devices and requires only a power supply voltage V. DD ≥V dsat2 ~3+V dsat1 V dsat2 ~3, V dsat1 The overdrive voltage of the input stage and bias current source is reduced, thus lowering the power supply voltage requirements and better meeting low power consumption needs. Simultaneously, the folded architecture places the transconductance stage and switching stage in different DC operating states, reducing the trade-off between mixer gain and switching stage noise. The transconductance stage consists of inductors L1, L2, L3, and L4, and PMOS transistors MP1, MP2, and MP3. PMOS transistor MP1 operates in the saturation region as a current source, providing bias current for the differential pair composed of PMOS transistors MP2 and MP3, achieving a fully differential input pair and reducing interference signals in the mixer output spectrum. Inductors L1 and L2 act as source-level negative feedback inductors for the differential pair composed of PMOS transistors MP2 and MP3, changing the input transconductance from gmp to... The linearity of the input transconductance is improved, and in high-sideband mixing, the RF input signal has a greater conversion gain than the mirror signal, which increases the suppression of the mirror signal. It also has a certain suppression effect on interference noise higher than the RF input signal. The introduction of inductors L1 and L2 can offset part of the gate-source capacitance of the differential pair of PMOS transistors MP2 and MP3, increasing the operating frequency. Inductors L3 and L4 provide a DC path for the transconductance stage, suppressing AC signals. The switching stage uses cascode technology to introduce transistors MN3 and MN4, improving the isolation between the RF input signal port and the local oscillator signal port, reducing the self-mixing phenomenon caused by feedthrough of the RF signal / local oscillator signal, and improving the second-order intermodulation product of the mixer. Inductors L5 and L6 are located at the source stage of switching transistors MN5, MN6, MN7, and MN8, resonating with the parasitic capacitance of the switching transistors at twice the local oscillator signal frequency. This makes the common-source node of the switching transistors exhibit low impedance at twice the local oscillator signal frequency, compensating for the parasitic capacitance of the common-source node. The charging and discharging current reduces the third-order and second-order intermodulation products introduced by the switching pair, improving the mixer's linearity. Switches MN6 and MN7 are biased at the same voltage VB3, while switches MN5 and MN8 are biased at voltages VB2 and VB4, respectively. In applications, the second-order intermodulation characteristics can be further improved by adjusting the bias voltages VB2 and VB4. The load stage uses self-biased PMOS transistors MP4 and MP5. Compared with current source loads, this structure reduces the common-mode feedback circuit and lowers the circuit complexity. At the same time, PMOS transistors MP4 and MP5 are long-channel transistors to avoid channel modulation effects introducing nonlinearity into the mixer. The output stage adopts a common-source amplifier structure. To improve the signal amplitude and driving capability of the output stage, transistors MP6 and MP7 are larger-sized PMOS transistors. Furthermore, since the output stage and the switching stage are under different DC biases, the trade-off between mixer gain and switching stage noise is further reduced.

[0023] The verification tests of this invention show that the mixer can achieve an operating frequency of 0.1 to 6 GHz under a power supply voltage of 1.2V, and the input third-order intermodulation product can reach 15 dBm.

[0024] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A wideband, high-linearity mixer, characterized in that, Including transconductance stage, switching stage, load stage, and output stage; The transconductance stage includes PMOS transistors MP1, MP2, and MP3, and inductors L1, L2, L3, and L4; The switching stage includes NMOS transistors MN3, MN4, MN5, MN6, MN7, and MN8; resistors R1, R2, R3, R4, R5, and R6; capacitors C1, C2, C3, and C4; and inductors L5 and L6. The gate of NMOS transistor MN3 is connected to the left end of resistor R1, and its drain is connected to the left end of inductor L5 and the source of NMOS transistors MN5 and MN6. The gate of NMOS transistor MN4 is connected to the right end of resistor R2, and its drain is connected to the right end of inductor L6 and the source of NMOS transistors MN7 and MN8. The right end of resistor R1 and the left end of resistor R2 are both connected to the bias voltage VB6. The right end of inductor L5 is connected to the left end of inductor L6. The gate of NMOS transistor MN5 is connected to the upper plate of capacitor C1 and the lower end of resistor R3. The load stage includes PMOS transistors MP4 and MP5, resistors R7 and R8. The source of PMOS transistor MP1 is connected to the power supply, the gate is connected to the bias voltage VB1, and the drain is connected to the right end of inductor L1 and the left end of inductor L2. The source of PMOS transistor MP2 is connected to the left end of inductor L1, the gate is connected to the input voltage VIN+, and the drain is connected to the upper end of inductor L3 and the source of NMOS transistor MN4. The source of PMOS transistor MP3 is connected to the right end of inductor L2, the gate is connected to the input voltage VIN-, and the drain is connected to the upper end of inductor L4 and the source of NMOS transistor MN3. The lower ends of inductors L3 and L4 are connected to ground. The output stage includes PMOS transistors MP6 and MP7, NMOS transistors MN9 and MN10, and resistors R9 and R10.

2. The wideband, high-linearity mixer according to claim 1, characterized in that: in, The drain of MN5 is connected to the drain of NMOS transistor MN7, the drain of PMOS transistor MP4, the gate of MP6, and the left end of resistor R7. The lower plate of capacitor C1 is connected to the local oscillator signal LO+. The upper end of resistor R3 is connected to the bias voltage VB2. The gate of NMOS transistor MN6 is connected to the upper plate of capacitor C2 and the lower end of resistor R4. The gate of NMOS transistor MN7 is connected to the upper plate of capacitor C3 and the lower end of resistor R5. The gate of NMOS transistor MN8 is connected to the upper plate of capacitor C4 and the lower end of resistor R6. The drain of MN8 is connected to the drain of MN6, the drain of PMOS transistor MN5, the gate of MP7, and the right end of resistor R8. The lower plate of capacitor C4 is connected to the local oscillator signal LO+. The upper end of resistor R6 is connected to the bias voltage VB4. The upper ends of resistors R4 and R5 are both connected to the bias voltage VB3. The lower plates of capacitors C2 and C3 are both connected to the local oscillator signal LO-.

3. The wideband, high-linearity mixer according to claim 1, characterized in that: in, The source of PMOS transistor MP4 is connected to the power supply, and its gate is connected to the gate of PMOS transistor MP5, the right end of resistor R7, and the left end of resistor R8. The source of PMOS transistor MP5 is connected to the power supply voltage. The sources of PMOS transistors MP6 and MP7 are both connected to the power supply voltage. The drain of MP6 is connected to the drain of NMOS transistor MN9, and the drain of MP7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN9 is connected to the left end of resistor R9, and its source is connected to ground. The gate of NMOS transistor MN10 is connected to the right end of resistor R10, and its source is connected to ground. The right end of resistor R9 and the left end of resistor R10 are both connected to the bias voltage VB5.

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