Liquid ejection device and capacitive load drive circuit

Abstract

The present invention provides a liquid ejection device and a capacitive load driving circuit. The liquid ejection device includes: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by performing level conversion on a reference potential of an amplified modulation signal obtained by amplifying a modulation signal obtained by modulating the corrected basic driving signal; a demodulation circuit that demodulates the level-converted amplified modulation signal to output a driving signal. The correction circuit outputs a corrected basic driving signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs a level-converted amplified modulation signal having the reference potential of the amplified modulation signal set to a first potential, and outputs a corrected basic driving signal corrected according to a second correction value in a second mode in which the level conversion circuit outputs a level-converted amplified modulation signal obtained by level-converting the reference potential of the amplified modulation signal to a second potential.

Description

Technical Field

[0001] The present invention relates to a liquid ejection device and a capacitive load drive circuit. Background Art

[0002] In a liquid ejection device that ejects liquid to form an image and a document on a medium, a liquid ejection device using a capacitive load such as a piezoelectric element is known. In such a liquid ejection device, a capacitive load is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. Further, by driving the capacitive load, liquid is ejected from the nozzle provided corresponding to the capacitive load. In order to operate such a capacitive load, it is necessary to supply sufficient current. Therefore, a capacitive load drive circuit that outputs a drive signal for driving the capacitive load is configured to include an amplifier circuit that amplifies a source signal that is the basis of the drive signal through an amplifier circuit.

[0003] Patent Document 1 discloses a drive circuit that is a drive circuit (capacitive load drive circuit) that outputs a drive signal for driving a piezoelectric element, which is one of the capacitive loads, and includes a class-D amplifier circuit as an amplifier circuit, and reduces power consumption related to the output of the drive signal COM.

[0004] However, from the viewpoint of further improving the liquid ejection accuracy of the liquid in the liquid ejection device and further improving the waveform accuracy of the drive signal output by the capacitive load drive circuit, the technology described in Patent Document 1 is not sufficient, and there is room for improvement.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-124040 Summary of the Invention

[0006] One aspect of the liquid ejection device according to the present invention includes: a liquid ejection head having a capacitive load that is driven by being supplied with a drive signal and ejecting liquid by driving the capacitive load; a capacitive load drive circuit that outputs the drive signal, the capacitive load drive circuit having: a correction circuit that outputs a corrected basic drive signal obtained by correcting a basic drive signal that is the basis of the drive signal; a modulation circuit that outputs a modulation signal obtained by modulating the corrected basic drive signal; an amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by performing level conversion on the reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulation signal; and a feedback circuit that feeds back the drive signal to the correction circuit, the correction circuit outputting the corrected basic drive signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is set to a first potential, and outputting the corrected basic drive signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is level-converted to a second potential different from the first potential.

[0007] One mode of the capacitive load driving circuit according to the present invention is a capacitive load driving circuit that outputs a driving signal to a liquid ejection head. The liquid ejection head has a capacitive load that is driven by being supplied with the driving signal and ejects liquid by driving the capacitive load. The capacitive load driving circuit includes: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal that is the basis of the driving signal; a modulation circuit that outputs a modulation signal obtained by modulating the corrected basic driving signal; an amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting the reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal; and a feedback circuit that feeds back the driving signal to the correction circuit. The correction circuit outputs the corrected basic driving signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is set to a first potential, and outputs the corrected basic driving signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is level-converted to a second potential different from the first potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A diagram showing an example of the structure of a liquid ejection device.

[0009] Figure 2 A diagram showing an example of the functional structure of a liquid ejection device.

[0010] Figure 3 A diagram showing an example of the arrangement of a plurality of ejection parts in a head unit.

[0011] Figure 4 A diagram showing an example of the structure of an ejection part.

[0012] Figure 5 A diagram showing an example of the signal waveform of a driving signal COM.

[0013] Figure 6 A diagram showing an example of the structure of a driving signal selection circuit.

[0014] Figure 7 A diagram showing an example of the decoding content in a decoder.

[0015] Figure 8A diagram showing an example of the structure of the selection circuit.

[0016] Figure 9 A diagram for explaining the operation of the drive signal selection circuit.

[0017] Figure 10 A diagram showing an example of the functional structure of the drive circuit.

[0018] Figure 11 A diagram for explaining the relationship between the corrected basic drive signal and the modulation signal.

[0019] Figure 12 A diagram for explaining the relationship between the basic drive signal aA and the reference level switching signal LS.

[0020] Figure 13 A diagram showing an example of the functional structure of the drive circuit of the second embodiment.

[0021] Figure 14 A diagram showing an example of the functional structure of the drive circuit of the third embodiment.

[0022] Figure 15 A diagram showing an example of the functional structure of the drive circuit of the fourth embodiment. Detailed Embodiments

[0023] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The accompanying drawings used are for the purpose of facilitating the explanation. In addition, the embodiments described below are not embodiments that unduly limit the content of the present invention described in the technical solution. Furthermore, not all of the structures described below are necessarily essential structural elements of the present invention.

[0024] In the following description, as an example of the liquid ejection device according to the present invention, an inkjet printer for customers is used. However, the liquid ejection device is not limited to an inkjet printer for customers, and may be, for example, a color material ejection device used in the manufacture of color filters such as liquid crystal displays, an electrode material ejection device used in the formation of electrodes for organic EL (Electro Luminescence) displays, surface-emitting displays, etc., and a biological organic matter ejection device used in the manufacture of biochips.

[0025] 1. First Embodiment

[0026] 1.1 Structure of the Liquid Ejection Device

[0027] Figure 1 A diagram showing an example of the structure of the liquid ejection device 1. As Figure 1As shown in the figure, the liquid ejection device 1 includes a moving body 2 and a moving unit 3 that reciprocates the moving body 2 along the main scanning direction.

[0028] The moving unit 3 includes a carriage motor 31 that serves as a drive source for reciprocating movement along the main scanning direction of the moving body 2, a carriage guide shaft 32 with both ends fixed, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0029] The moving body 2 includes a carriage 24. The carriage 24 is supported on the carriage guide shaft 32 so as to be reciprocally movable, and is fixed to a part of the timing belt 33. Further, by causing the timing belt 33 to travel forward and backward using the carriage motor 31, the moving body 2 having the carriage 24 is guided by the carriage guide shaft 32 to perform reciprocating movement. In addition, the head unit 20 is located on a portion of the moving body 2 that faces the medium P. That is, the head unit 20 is mounted on the carriage 24. A plurality of nozzles that eject ink as a liquid are located on the surface of the head unit 20 that faces the medium P. Further, in the head unit 20, various control signals for controlling the operation of the head unit 20 are supplied via a cable 190. As such a cable 190, a flexible flat cable or the like that can slide following the reciprocating movement of the moving body 2 can be used.

[0030] In addition, the liquid ejection device 1 includes a conveyance unit 4 that conveys the medium P on the platen 40 along the conveyance direction. The conveyance unit 4 includes a conveyance motor 41 that serves as a drive source for conveying the medium P and a conveyance roller 42 that conveys the medium P along the conveyance direction by rotating using the conveyance motor 41.

[0031] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is conveyed by the conveyance unit 4. As a result, the ink ejected from the head unit 20 lands on a desired position on the medium P, and thus, a desired image and characters are formed on the surface of the medium P.

[0032] Next, the functional structure of the liquid ejection device 1 will be described. Figure 2 FIG. is a diagram showing an example of the functional structure of the liquid ejection device 1. As Figure 2 shown, the liquid ejection device 1 includes a control unit 10, a head unit 20, a moving unit 3, a conveyance unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0033] The control unit 10 includes a power supply circuit 11, a control unit 100, and a drive circuit 50.

[0034] The power supply circuit 11 generates voltage signals VHV1, VHV2, and VDD of a predetermined voltage value from a commercial AC power supply supplied from outside the liquid ejection device 1, and outputs the voltage signals to various structures of the liquid ejection device 1. Here, the voltage signals VHV1 and VHV2 output by the power supply circuit 11 are, for example, DC voltages of 25V, and the voltage signal VDD is, for example, a DC voltage of 3.3V. Such a power supply circuit 11 may also be configured to include, for example, an AC / DC converter that generates a DC voltage of a predetermined voltage value from a commercial AC power supply, and a DC / DC converter that generates the voltage signals VHV1, VHV2, and VDD by converting the voltage value of the generated DC voltage. In addition to outputting the voltage signals VHV1, VHV2, and VDD, the power supply circuit 11 also outputs DC voltages of different voltage values.

[0035] In the control unit 100, image data is supplied from an external device (not shown) provided outside the liquid ejection device 1, such as a host computer or the like. The control unit 100 generates various control signals for controlling each part of the liquid ejection device 1 by applying various image processing and the like to the supplied image data, and outputs the control signals to the corresponding structures.

[0036] Specifically, the control unit 100 generates a control signal Ctrl1 for controlling the reciprocating movement of the moving body 2, and outputs it to the carriage motor 31 included in the moving unit 3. In addition, the control unit 100 generates a control signal Ctrl2 for controlling the conveyance of the medium P, and outputs it to the conveyance motor 41 included in the conveyance unit 4. As a result, the reciprocating movement of the moving body 2 in the main scanning direction and the conveyance of the medium P in the conveyance direction are controlled by the control unit 100. As a result, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the conveyance of the medium P. As a result, the ink is ejected onto the desired position of the medium P, and thus a desired image and characters can be formed on the medium P.

[0037] In addition, the control unit 100 may supply the control signal Ctrl1 for controlling the reciprocating movement of the moving body 2 to the moving unit 3 via a carriage motor driver (not shown), and similarly, may supply the control signal Ctrl2 for controlling the conveyance of the medium P to the conveyance unit 4 via a conveyance motor driver (not shown).

[0038] In addition, the control unit 100 outputs a basic drive signal dA to the drive circuit 50. The basic drive signal dA output by the control unit 100 is a signal including data that defines the waveform of the drive signal COM supplied to the opposing head unit 20, and is, for example, a digital signal. After converting the input digital basic drive signal dA into an analog signal, the drive circuit 50 generates the drive signal COM by amplifying the converted signal. Then, the drive circuit 50 supplies the generated drive signal COM to the head unit 20. In addition, the detailed structure and operation of the drive circuit 50 will be described later.

[0039] In addition, the control unit 100 generates a clock signal SCK, a latch signal LAT, and a print data signal SI for controlling the operation of the head unit 20, and outputs these signals to the head unit 20.

[0040] The head unit 20 includes a drive signal selection circuit 200 and a liquid ejection head 21. In addition, the liquid ejection head 21 has a plurality of ejection portions 600, and each of the plurality of ejection portions 600 includes a piezoelectric element 60. In the following description, the structure in which the number of ejection portions 600 included in the liquid ejection head 21 is n will sometimes be described.

[0041] In the drive signal selection circuit 200, the clock signal SCK, the latch signal LAT, and the print data signal SI are input. Based on the print data signal SI propagated through the clock signal SCK, the drive signal selection circuit 200 switches whether to supply the drive signal COM as the drive signal VOUT to one end of each piezoelectric element 60 included in the plurality of ejection portions 600 during the period specified by the latch signal LAT.

[0042] In addition, a reference voltage signal VBS is supplied to the other end of each piezoelectric element 60 included in the plurality of ejection portions 600. The reference voltage signal VBS is a signal that functions as a reference potential for driving the piezoelectric element 60 driven by the drive signal VOUT, and is, for example, a signal having a fixed potential such as 5.5V, 6V, or a ground potential.

[0043] The piezoelectric element 60 is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. By driving the piezoelectric element 60, ink is ejected from the ejection portion 600 including the piezoelectric element 60.

[0044] In addition, although in Figure 2The figure shows a case where the head unit 20 has one liquid ejection head 21. However, the number of liquid ejection heads 21 included in the head unit 20 is not limited to one, and the head unit 20 may also have a plurality of liquid ejection heads 21 depending on the type and amount of ink to be ejected, etc.

[0045] As described above, the liquid ejection device 1 in the present embodiment includes a liquid ejection head 21 and a drive circuit 50. Among them, the liquid ejection head 21 has a plurality of piezoelectric elements 60 that are driven by being supplied with drive signals COM and VOUT, and ejects ink, which is an example of a liquid, by driving the plurality of piezoelectric elements 60. The drive circuit 50 outputs a drive signal COM.

[0046] 1.2 Structure and operation of the ejection unit

[0047] Next, an example of the structure of the plurality of ejection units 600 included in the head unit 20 and an example of the arrangement of the plurality of ejection units 600 in the head unit 20 will be described. Figure 3 For showing an example of the arrangement of the plurality of ejection units 600 in the head unit 20. In addition, in Figure 3 a case where the head unit 20 has four liquid ejection heads 21 is illustrated.

[0048] As Figure 3 shown, the four liquid ejection heads 21 each have a plurality of ejection units 600 arranged in a column in one direction. That is, the liquid ejection head 21 includes a nozzle row L formed by arranging nozzles 651 (described later) included in the ejection unit 600 in one direction. In addition, the liquid ejection heads 21 are arranged in the head unit 20 in a direction intersecting the nozzle row L. That is, in the head unit 20, the same number of nozzle rows L as the number of liquid ejection heads 21 are formed. In addition, the arrangement of the nozzles 651 in the nozzle row L included in the liquid ejection head 21 is not limited to one row. For example, they may be arranged in a staggered shape such that the positions of the even-numbered nozzles 651 counted from one end of the plurality of nozzles 651 and the odd-numbered nozzles 651 counted from one end of the plurality of nozzles 651 are different, or in the liquid ejection head 21, a nozzle row L may be formed by arranging two or more rows of the plurality of nozzles 651 in parallel.

[0049] Next, an example of the structure of the ejection unit 600 will be described. Figure 4 For showing an example of the structure of the ejection unit 600. As Figure 4 shown, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a chamber 631, and a nozzle 651. The diaphragm 621 vibrates as a result of Figure 4It is displaced by the drive of the piezoelectric element 60 provided on the upper surface. The vibration plate 621 functions as a diaphragm that expands / contracts the internal volume of the chamber 631. Ink is filled inside the chamber 631. Also, the chamber 631 functions as a pressure chamber whose internal volume changes due to the displacement of the vibration plate 621 caused by the drive of the piezoelectric element 60. The nozzle 651 is an opening formed on the nozzle plate 632 and communicating with the chamber 631. And, along with the change in the internal volume of the chamber 631, the ink retained inside the chamber 631 is ejected from the nozzle 651.

[0050] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is clamped using a pair of electrodes 611, 612. The piezoelectric body 601 of this structure flexes the central portion of the electrodes 611, 612 and the vibration plate 621 relative to the both end portions in the Figure 4 vertical direction in

[0051] Specifically, a drive signal VOUT is supplied to the electrode 611 which is one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to the electrode 612 which is the other end. Moreover, when the piezoelectric element 60 is driven in the upward direction according to the change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced in the upward direction. As a result, the internal volume of the chamber 631 expands. Therefore, the ink retained in the reservoir 641 is introduced into the chamber 631. On the other hand, when the piezoelectric element 60 is driven in the downward direction according to the change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced in the downward direction. As a result, the internal volume of the chamber 631 contracts. Therefore, an amount of ink corresponding to the degree of contraction of the internal volume of the chamber 631 is ejected from the nozzle 651.

[0052] As described above, the liquid ejection head 21 includes the piezoelectric element 60 and ejects ink to the medium by driving the piezoelectric element 60. In addition, the ejection portion 600 and the piezoelectric element 60 included in the ejection portion 600 are not limited to the illustrated structure, as long as it is a structure that can drive the piezoelectric element 60 based on the drive signal VOUT and eject ink from the corresponding nozzle 651 by driving the piezoelectric element 60.

[0053] 1.3 Structure and operation of the selection control circuit

[0054] Next, the structure and operation of the drive signal selection circuit 200 will be described. As described above, the drive signal selection circuit 200 switches whether to supply the drive signal VOUT based on the drive signal COM to each of the plurality of ejection units 600 based on the clock signal SCK, the latch signal LAT, and the print data signal SI. Therefore, when describing the structure and operation of the drive signal selection circuit 200, first, an example of the signal waveform of the drive signal COM supplied to the drive signal selection circuit 200 will be described.

[0055] Figure 5 FIG. showing an example of the signal waveform of the drive signal COM. As Figure 5 shown, the drive signal COM includes a trapezoidal waveform Adp in each period T from the rise of the latch signal LAT to the rise of the next latch signal LAT. The trapezoidal waveform Adp includes a period in which the voltage vc is constant, a period in which the voltage is constant at a voltage vb smaller than the voltage vc after the period in which the voltage vc is constant, a period in which the voltage is constant at a voltage vt larger than the voltage vc compared to the voltage vc after the period in which the voltage vb is constant, and a period in which the voltage is constant at the voltage vc after the period in which the voltage vt is constant. That is, the drive signal COM includes a trapezoidal waveform Adp that starts and ends with the voltage vc.

[0056] The voltage vc corresponds to the potential that serves as the reference for the displacement of the piezoelectric element 60. And by changing the voltage value of the drive signal COM supplied to the piezoelectric element 60 from the voltage vc to the voltage vb, the piezoelectric element 60 is driven upward as Figure 4 shown. As a result, the diaphragm 621 is displaced upward as Figure 4 shown. Then, as the diaphragm 621 is displaced upward as Figure 4 shown, the internal volume of the chamber 631 is expanded, so that the ink is introduced from the reservoir 641 into the chamber 631. After that, by changing the voltage value of the drive signal COM supplied to the piezoelectric element 60 from the voltage vb to the voltage vt, the piezoelectric element 60 is driven downward as Figure 4 shown. As a result, the diaphragm 621 is displaced downward as Figure 4 shown. Then, as the diaphragm 621 is displaced downward as Figure 4 shown, the internal volume of the chamber 631 is reduced, so that the ink retained in the chamber 631 is ejected from the nozzle 651.

[0057] In addition, sometimes, during a fixed period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60, the ink near the nozzle 651 or the vibration plate 621 continues to vibrate. The period during which the voltage vc in the drive signal COM is constant also functions as a period for stopping the vibration that does not contribute to the ejection of the ink or the ink generated in the vibration plate 621.

[0058] Here, Figure 5 The signal waveform of the drive signal COM shown is an example, and it is not limited thereto. It may also include signal waveforms of various shapes corresponding to the physical properties of the ink ejected from the liquid ejection head 21, the length of the period T of the drive signal COM, the conveyance speed of the medium P, and the like.

[0059] Next, the structure and operation of the drive signal selection circuit 200 that generates the drive signal VOUT by selecting or not selecting the signal waveform included in the drive signal COM will be described. Figure 6 FIG. is an example showing the structure of the drive signal selection circuit 200. As Figure 6 shown, the drive signal selection circuit 200 includes a selection control circuit 210 and n selection circuits 230.

[0060] In the selection control circuit 210, a clock signal SCK, a print data signal SI, and a latch signal LAT are input. In addition, the selection control circuit 210 has a set composed of a shift register (S / R) 212, a latch circuit 214, and a decoder 216 corresponding to each of the n ejection units. That is, the drive signal selection circuit 200 has n shift registers 212, n latch circuits 214, and n decoders 216.

[0061] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. The print data signal SI serially includes print data [SId] corresponding to each of the n ejection units 600, and the print data [SId] is used to select "ejection FD" for forming dots on the medium P by ejecting ink from the ejection unit 600 and "non-ejection ND" for not forming dots on the medium P by not ejecting ink from the ejection unit 600. That is, the print data signal SI is a serial signal of n bits or more.

[0062] The print data [SId] included in the print data signal SI is held by n shift registers 212 corresponding to n ejection units 600. Specifically, the n shift registers 212 corresponding to the ejection units 600 are cascade-connected to each other, and the print data signal SI input serially is forwarded to the subsequent shift register 212 in sequence according to the clock signal SCK. And, by having the print data [SId] held in the corresponding shift register 212, the supply of the clock signal SCK will stop. In other words, by stopping the supply of the clock signal SCK, the print data [SId] included in the print data signal SI is held in the corresponding shift register 212. Additionally, in Figure 6 in order to distinguish the n shift registers 212, they are sequentially labeled as the first stage, the second stage, …… the nth stage from the upstream side where the print data signal SI is input to the downstream side.

[0063] Each of the n latch circuits 214 latches the print data [SId] held in the corresponding shift register 212 simultaneously at the rising edge of the latch signal LAT. The print data [SId] latched by the latch circuit 214 is input to the corresponding decoder 216.

[0064] Figure 7 It is a diagram showing an example of the decoding content in the decoder 216. The decoder 216 outputs a selection signal S of a logical level corresponding to the input print data [SId]. Specifically, when the print data [SId] = [1] is input to the decoder 216, the decoder 216 outputs a selection signal S of H level within the period T, and when the print data [SId] = [0] is input to the decoder 216, the decoder 216 outputs a selection signal S of L level within the period T.

[0065] The selection signal S output by the decoder 216 is input to the selection circuit 230. The selection circuit 230 is provided in a manner corresponding to each of the n ejection units 600. That is, the drive signal selection circuit 200 has n selection circuits 230 with the same number as the n ejection units 600. Figure 8 It is an example showing the structure of the selection circuit 230 corresponding to the amount of one ejection unit 600. As Figure 8 shown, the selection circuit 230 includes an inverter 232 as a NOT circuit and a transmission gate 234.

[0066] After the selection signal S is input to the positive control terminal of the transmission gate 234 without the circular mark and its logic level is inverted by the inverter 232, it is also input to the negative control terminal of the transmission gate 234 with the circular mark. In addition, the drive signal COM is supplied to the input terminal of the transmission gate 234. And when the selection signal S of H level is input to the transmission gate 234, the connection between the input terminal and the output terminal is set to the conducting state, and when the selection signal S of L level is input, the connection between the input terminal and the output terminal is set to the non-conducting state. That is, when the logic level of the input selection signal S is H level, the trapezoidal waveform Adp is output from the output terminal, and when the logic level of the input selection signal S is L level, the trapezoidal waveform Adp is not output from the output terminal. The signal input to the output terminal of the transmission gate 234 included in the selection circuit 230 is output from the drive signal selection circuit 200 as the drive signal VOUT.

[0067] Here, use Figure 9 to describe the operation of the drive signal selection circuit 200. Figure 9 FIG. is for describing the operation of the drive signal selection circuit 200. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK. And the print data signal SI is sequentially forwarded in the n shift registers 212 corresponding to the n ejection units 600 in synchronization with the clock signal SCK. After that, when the input of the clock signal SCK stops, the print data [SId] corresponding to each of the n ejection units 600 is held in the shift register 212. In addition, in the print data signal SI, the print data [SId] is included in the order corresponding to the nth stage, ……, 2nd stage, 1st stage of the shift register 212 corresponding to the ejection unit 600.

[0068] Moreover, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SId] held in the shift register 212. The print data [SId] latched by the latch circuit 214 is input to the corresponding decoder 216. In addition, Figure 9 The LT1, LT2, ……, LTn shown correspond to the print data [SId] latched by the latch circuit 214 in a manner corresponding to the 1st stage, 2nd stage, ……, nth stage of the shift register 212.

[0069] The decoder 216 decodes the input print data [SId] to generate Figure 7The selection signal S of the indicated logic level is output to the corresponding selection circuit 230. Then, the selection circuit 230 selects or does not select the trapezoidal waveform Adp included in the drive signal COM according to the logic level of the selection signal S output by the decoder 216, thereby generating a drive signal VOUT corresponding to each of the n ejection units 600 and outputting the drive signal VOUT to the corresponding ejection unit 600.

[0070] Specifically, when the printing data [SId] = [1] is input to the decoder 216, the decoder 216 outputs a selection signal S of H level within the period T. Thus, the selection circuit 230 selects and outputs the trapezoidal waveform Adp within the period T. That is, the drive signal selection circuit 200 supplies the drive signal VOUT corresponding to "ejection FD" to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, an amount of ink corresponding to the drive signal VOUT is ejected from the corresponding ejection unit 600. And, the ink ejected from the ejection unit 600 lands on the medium P, thereby forming dots on the medium P.

[0071] On the other hand, when the printing data [SId] = [0] is input to the decoder 216, the decoder 216 outputs a selection signal S of L level within the period T. Thus, the selection circuit 230 does not select the trapezoidal waveform Adp within the period T. At this time, in the electrode 611 of the piezoelectric element 60 corresponding to the selection circuit 230, a voltage vc is held by the capacitance component of the piezoelectric element 60. That is, the drive signal selection circuit 200 supplies the voltage vc just held by the capacitance component of the corresponding piezoelectric element 60 as the drive signal VOUT corresponding to "non-ejection ND" to the piezoelectric element 60. As a result, no ink is ejected from the corresponding ejection unit 600, and thus, no dots are formed on the medium P.

[0072] As described above, the drive signal selection circuit 200 switches the supply of the drive signal COM to the plurality of piezoelectric elements 60 based on the printing data signal SI.

[0073] 1.4 Structure and operation of the drive circuit

[0074] Next, the structure and operation of the drive circuit 50 that generates and outputs the drive signal COM will be described. Figure 10 FIG. shows an example of the functional structure of the drive circuit 50. As Figure 10 shown, the drive circuit 50 includes a correction circuit 510, a modulation circuit 520, an amplification circuit 550, a demodulation circuit 560, a first feedback circuit 570, a second feedback circuit 580, and a level conversion circuit 70.

[0075] In the correction circuit 510, a basic drive signal dA, which is a digital signal, is input from the control unit 100. The correction circuit 510 performs digital-to-analog conversion on the input basic drive signal dA and performs correction to generate and output a corrected basic drive signal oA. Such a correction circuit 510 includes a basic drive signal correction circuit 513, a DAC (Digital-to-Analog Converter) 511, and adders 515 and 516.

[0076] In the basic drive signal correction circuit 513, the basic drive signal dA and a reference level switching signal LS from a level conversion circuit 70 described later are input. The basic drive signal correction circuit 513 subtracts a predetermined correction value from the basic drive signal dA according to the logic level of the input reference level switching signal LS and outputs it as a correction signal dAJ. Specifically, when the reference level switching signal LS of L level is input, the basic drive signal correction circuit 513 subtracts a predetermined correction value Cv1 from the basic drive signal dA and outputs it as the correction signal dAJ, and when the reference level switching signal LS of H level is input, the basic drive signal correction circuit 513 subtracts a predetermined correction value Cv2 from the basic drive signal dA and outputs it as the correction signal dAJ.

[0077] Here, in the following description, a method in which the correction value Cv1 is "0" and the correction value Cv2 is an arbitrary value in natural numbers will be described. That is, the basic drive signal correction circuit 513 in the present embodiment will be described as follows. When the reference level switching signal LS of L level is input, the basic drive signal dA is output as the correction signal dAJ, and when the reference level switching signal LS of H level is input, a value specified by a predetermined correction value Cv2 is subtracted from the basic drive signal dA and output as the correction signal dAJ. In addition, the respective values of the correction values Cv1 and Cv2 are not limited to this, but any values can be used.

[0078] The correction signal dAJ is input to the DAC circuit 511. The DAC circuit 511 generates and outputs an analog basic drive signal aA by performing digital-to-analog conversion on the input correction signal dAJ.

[0079] A basic drive signal aA is input to the input terminal on the + side of the adder 515, and a first feedback signal VFB1 is input to the input terminal on the - side of the adder 515. Further, the adder 515 outputs a signal obtained by subtracting the first feedback signal VFB1 from the basic drive signal aA. Here, the first feedback signal VFB1 input to the adder 515 is a signal obtained by feeding back the drive signal COM via the first feedback circuit 570. Specifically, it is a signal obtained by attenuating the voltage value of the drive signal COM by the attenuator 572.

[0080] The signal output from the adder 515 is input to the input terminal on the + side of the adder 516, and a second feedback signal VFB2 is input to the input terminal on the - side of the adder 516. Further, the adder 516 outputs, as a corrected basic drive signal oA, a signal obtained by subtracting the second feedback signal VFB2 from the signal output from the adder 515. Here, the second feedback signal VFB2 is a signal obtained by feeding back the drive signal COM via the second feedback circuit 580. Specifically, it is a signal obtained by attenuating the voltage value of the signal of the high-frequency component included in the drive signal COM by the attenuator 582.

[0081] As described above, the correction circuit 510 corrects the input basic drive signal dA based on the correction value Cv1 or the correction value Cv2, the first feedback signal VFB1, and the second feedback signal VFB2, thereby generating and outputting a corrected basic drive signal oA. That is, the correction circuit 510 outputs a corrected basic drive signal oA obtained by correcting the basic drive signal dA that is the basis of the drive signal COM.

[0082] The modulation circuit 520 includes, for example, a comparator. Further, the modulation circuit 520 outputs a modulation signal MS obtained by pulse-modulating the corrected basic drive signal oA. Specifically, the modulation circuit 520 compares the voltage value of the corrected basic drive signal oA with a predetermined voltage value vref as a reference voltage. Then, the modulation circuit 520 generates and outputs the modulation signal MS, which becomes the H level when the voltage value of the input corrected basic drive signal oA is greater than the voltage vref, and becomes the L level when the voltage value of the corrected basic drive signal oA is less than the voltage vref.

[0083] The amplifier circuit 550 includes a gate driver circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. Further, the amplifier circuit 550 outputs an amplified modulation signal AMS1 from the midpoint CP1.

[0084] Specifically, the modulation signal MS is input to the gate driver 531 included in the gate driver circuit 530. The gate driver 531 generates and outputs a gate signal HGD1 obtained by level-shifting the input modulation signal MS. In addition, after the logic level of the modulation signal MS is inverted in the inverter 521, it is input to the gate driver 532 included in the gate driver circuit 530. The gate driver 532 generates and outputs a gate signal LGD1 obtained by level-shifting the signal obtained by inverting the logic level of the input modulation signal MS.

[0085] Both the transistors M1 and M2 are composed of N-channel MOS-FETs (Metal Oxide Semiconductor Field-Effect Transistors). The gate signal HGD1 output by the gate driver 531 is input to the gate terminal of the transistor M1. A voltage signal VHV1 is supplied to the drain terminal of the transistor M1. The source terminal of the transistor M1 is electrically connected to the midpoint CP1. In addition, the gate signal LGD1 output by the gate driver 532 is input to the gate terminal of the transistor M2. The drain terminal of the transistor M2 is electrically connected to the midpoint CP1. A ground potential is supplied to the source terminal of the transistor M2. Then, by the transistor M1 operating based on the gate signal HGD1 and the transistor M2 operating based on the gate signal LGD1, an amplified modulation signal AMS1 obtained by amplifying the modulation signal MS with the voltage signal VHV1 is generated at the midpoint CP1 where the transistor M1 and the transistor M2 are connected together.

[0086] Here, the operation of the gate driver circuit 530 that outputs the gate signal HGD1 and the gate signal LGD1 based on the modulation signal MS will be described. The gate driver circuit 530 includes gate drivers 531 and 532. As described above, the modulation signal MS is input to the gate driver 531, and the signal obtained by inverting the logic level of the modulation signal MS by the inverter 521 is input to the gate driver 532. That is, the signals input to the gate driver 531 and the gate driver 532 exclusively become the H level. Here, exclusively becoming the H level includes the case where the H-level signal is not simultaneously input to the gate driver 531 and the gate driver 532. That is, the case where the L-level signal is simultaneously input to the gate driver 531 and the gate driver 532 is not excluded.

[0087] The power supply terminal on the low potential side of the gate driver 531 is electrically connected to the midpoint CP1. Therefore, in the power supply terminal on the low potential side of the gate driver 531, the signal generated at the midpoint CP1 is supplied as the voltage signal HVS1. In addition, the power supply terminal on the high potential side of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. In addition, the voltage vm is supplied to the anode terminal of the diode D1, and the other end of the capacitor C1 is electrically connected to the midpoint CP1. That is, in the power supply terminal on the high potential side of the gate driver 531, the output voltage of the bootstrap circuit including the diode D1 and the capacitor C1 is supplied. Thus, in the power supply terminal on the high potential side of the gate driver 531, a voltage signal HVD1 having a voltage value increased by the voltage vm compared to the voltage signal HVS1 input to the power supply terminal on the low potential side of the gate driver 531 is supplied. Therefore, when the H-level modulation signal MS is input to the gate driver 531, the gate driver 531 outputs a gate signal HGD1 having a voltage value increased by the voltage vm compared to the voltage value of the midpoint CP1 and based on the voltage value of the voltage signal HVD1, and when the L-level modulation signal MS is input to the gate driver 531, the gate driver 531 outputs the voltage value of the midpoint CP1, that is, the gate signal HGD1 based on the voltage value of the voltage signal HVS1.

[0088] Here, the voltage vm is a voltage value capable of driving each of the transistors M1, M2, M3, and M4, and is a DC voltage of, for example, 7.5V. This voltage vm can also be generated, for example, by stepping down or stepping up the voltage signals VHV1, VHV2, and VDD output from the power supply circuit 11.

[0089] In the power supply terminal on the low potential side of the gate driver 532, a signal of the ground potential is supplied as the voltage signal LVS1. In addition, in the power supply terminal on the high potential side of the gate driver 532, the voltage vm is supplied as the voltage signal VLD1. Therefore, when an H-level signal obtained by inverting the logic level of the L-level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs the voltage vm, that is, the gate signal LGD1 based on the voltage value of the voltage signal LVD1, and when an L-level signal obtained by inverting the logic level of the H-level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs the gate signal LGD1 based on the voltage value of the voltage signal LVS1 of the ground potential.

[0090] As described above, the amplifier circuit 550 includes: a gate driver circuit 530 that outputs a gate signal HGD1 and a gate signal LGD1 based on a modulation signal MS; a transistor M1 whose one end, i.e., the drain terminal, is supplied with a voltage signal VHV1, and the other end, i.e., the source terminal, is electrically connected to the midpoint CP1, and operates based on the gate signal HGD1 input to the gate terminal; and a transistor M2 whose one end, i.e., the drain terminal, is electrically connected to the midpoint CP1, and the other end, i.e., the source terminal, is supplied with a ground potential, and operates based on the gate signal LGD1 input to the gate terminal.

[0091] The level conversion circuit 70 includes a reference level switching circuit 710, a gate driver circuit 730, diodes D11, D12, capacitors C11, C12, transistors M3, M4, and a bootstrap circuit BS. Moreover, the level conversion circuit 70 outputs a level-converted amplified modulation signal AMS2 obtained by level-converting the reference potential of the amplified modulation signal AMS1 to the midpoint CP2.

[0092] Specifically, a basic drive signal dA is input to the reference level switching circuit 710 included in the level conversion circuit 70. The reference level switching circuit 710 generates a reference level switching signal LS based on the basic drive signal dA and outputs it to the gate driver circuit 730. Specifically, the reference level switching circuit 710 generates an H-level reference level switching signal LS and outputs it to the gate driver circuit 730 when the voltage value specified by the basic drive signal dA is equal to or higher than a predetermined threshold voltage, and generates an L-level reference level switching signal LS and outputs it to the gate driver circuit 730 when the voltage value specified by the basic drive signal dA is less than the threshold voltage. Here, the predetermined threshold voltage is a voltage value lower than the voltage value of the voltage signal VHV1 supplied to the amplifier circuit 550, and is preferably a voltage value near the voltage value of the voltage signal VHV1.

[0093] The gate driver circuit 730 outputs a gate signal HGD2 for driving the transistor M3 and a gate signal LGD2 for driving the transistor M4 according to the logic level of the reference level switching signal LS.

[0094] Specifically, the reference level switching signal LS output by the reference level switching circuit 710 is input to the gate driver 731 included in the gate driver circuit 730. The gate driver 731 generates and outputs a gate signal HGD2 obtained by level-converting the input reference level switching signal LS. In addition, the reference level switching signal LS output by the reference level switching circuit 710 is input to the gate driver 732 included in the gate driver circuit 730 after the logic level thereof is inverted in the inverter 721. The gate driver 732 generates and outputs a gate signal LGD2 obtained by level-converting the signal obtained by inverting the logic level of the input reference level switching signal LS.

[0095] Both the transistors M3 and M4 are composed of N-channel MOS-FETs. The gate signal HGD2 output by the gate driver 731 is input to the gate terminal of the transistor M3. A voltage signal VHV3 output by the bootstrap circuit BS is supplied to the drain terminal of the transistor M3. The source terminal of the transistor M3 is electrically connected to the midpoint CP2. In addition, the gate signal LGD2 output by the gate driver 732 is input to the gate terminal of the transistor M4. The drain terminal of the transistor M4 is electrically connected to the midpoint CP2. The source terminal of the transistor M4 is electrically connected to the midpoint CP1. Moreover, by causing the transistor M3 to operate based on the gate signal HGD2 and causing the transistor M4 to operate based on the gate signal LGD2, a level-converted amplified modulation signal AMS2 obtained by level-converting the reference potential of the amplified modulation signal AMS1 is generated at the midpoint CP2 where the transistor M3 and the transistor M4 are connected together.

[0096] That is, one end, i.e., the drain terminal, of the transistor M3 included in the level conversion circuit 70 is supplied with the voltage signal VHV3 output by the bootstrap circuit BS, and the other end, i.e., the source terminal, is electrically connected to the midpoint CP2, and it operates based on the gate signal HGD2 output by the gate driver 731. One end, i.e., the drain terminal, of the transistor M4 included in the level conversion circuit 70 is electrically connected to the midpoint CP2, and the other end, i.e., the source terminal, is supplied with the amplified modulation signal AMS1 output by the amplifier circuit 550, and it operates based on the gate signal LGD2 output by the gate driver 732. Moreover, the level conversion circuit 70 outputs the signal generated at the midpoint CP2 where the transistor M3 and the transistor M4 are connected together as the level-converted amplified modulation signal AMS2.

[0097] The bootstrap circuit BS includes a diode D13 and a capacitor C13. A voltage signal VHV2 is supplied to the anode terminal of the diode D13, and the cathode terminal of the diode D13 is electrically connected to one end of the capacitor C13. In addition, the other end of the capacitor C13 is electrically connected to the midpoint CP1. That is, the voltage signal VHV2 and the amplified modulation signal AMS1 output to the midpoint CP1 are input to the bootstrap circuit BS. Moreover, the bootstrap circuit BS generates a voltage signal VHV3 obtained by adding the voltage value of the voltage signal VHV2 and the voltage value of the amplified modulation signal AMS1, and outputs it to the drain terminal of the transistor M3. In other words, the bootstrap circuit BS outputs a voltage signal VHV3 corresponding to the voltage signal VHV2 and the amplified modulation signal AMS1, which is obtained by level-shifting the reference potential of the amplified modulation signal AMS1 based on the voltage signal VHV2.

[0098] Here, the operation of the gate driver circuit 730 that outputs the gate signal HGD2 and the gate signal LGD2 based on the reference level switching signal LS will be described. The gate driver circuit 730 includes gate drivers 731 and 732. As described above, the reference level switching signal LS is input to the gate driver 731, and the signal obtained by inverting the logic level of the reference level switching signal LS by the inverter 721 is input to the gate driver 732. That is, the signal input to the gate driver 731 and the signal input to the gate driver 732 exclusively become the H level. Here, exclusively becoming the H level includes the case where the H-level signal is not simultaneously input to the gate driver 731 and the gate driver 732. That is, the case where the L-level signal is simultaneously input to the gate driver 731 and the gate driver 732 is not excluded.

[0099] The power supply terminal on the low potential side of the gate driver 731 is electrically connected to the midpoint CP2. Therefore, in the power supply terminal on the low potential side of the gate driver 731, the signal generated at the midpoint CP2 is supplied as the voltage signal HVS2. In addition, the power supply terminal on the high potential side of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. In addition, the voltage vm is supplied to the anode terminal of the diode D11, and the other end of the capacitor C11 is electrically connected to the midpoint CP2. That is, the diode D11 and the capacitor C11 constitute a bootstrap circuit. Moreover, the output voltage of the bootstrap circuit constituted by the diode D11 and the capacitor C11 is supplied to the power supply terminal on the high potential side of the gate driver 731. That is, in the power supply terminal on the high potential side of the gate driver 731, a voltage signal HVD2 with a voltage value increased by the voltage vm compared to the voltage signal HVS2 input to the power supply terminal on the low potential side of the gate driver 731 is supplied. Therefore, when the H-level reference level switching signal LS is input to the gate driver 731, the gate driver 731 outputs a gate signal HGD2 based on the voltage signal HVD2 with a voltage value increased by the voltage vm compared to the voltage value of the midpoint CP2, and when the L-level reference level switching signal LS is input to the gate driver 731, the gate driver 731 outputs the voltage value of the midpoint CP2, that is, the gate signal HGD2 based on the voltage signal HVS2.

[0100] The power supply terminal on the low potential side of the gate driver 732 is electrically connected to the midpoint CP1. Therefore, in the power supply terminal on the low potential side of the gate driver 732, the signal generated at the midpoint CP1 and the amplified modulation signal AMS1 are supplied as the voltage signal LVS2. In addition, the power supply terminal on the high potential side of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. In addition, the voltage vm is supplied to the anode terminal of the diode D12, and the other end of the capacitor C12 is electrically connected to the midpoint CP1. That is, a bootstrap circuit including the diode D12 and the capacitor C13 is electrically connected to the power supply terminal on the high potential side of the gate driver 732. Therefore, in the power supply terminal on the high potential side of the gate driver 732, a voltage signal LVD2 with a voltage value increased by the voltage vm compared to the voltage signal LVS2 input to the power supply terminal on the low potential side of the gate driver 732 is supplied.

[0101] Therefore, when the H-level signal obtained by inverting the logic level of the reference level switching signal LS at the L level by the inverter 721 is input to the gate driver 732, the gate driver 732 outputs a gate signal LGD2 based on the voltage value of the voltage signal LVD2, which has a voltage vm increased compared to the voltage value of the midpoint CP1. And when the L-level signal obtained by inverting the logic level of the reference level switching signal LS at the H level by the inverter 721 is input to the gate driver 732, the gate driver 732 outputs a gate signal HGD2 with the voltage value of the midpoint CP1, that is, based on the voltage value of the voltage signal LVS2.

[0102] Here, the gate driver circuit 730 outputs a gate signal HGD2 and a gate signal LGD2 based on the logic level of the reference level switching signal LS output by the reference level switching circuit 710. Here, as described above, the logic level of the reference level switching signal LS output by the reference level switching circuit 710 is switched according to whether the voltage value specified by the base drive signal dA is above a predetermined threshold voltage. That is, the gate driver circuit 730 outputs the gate signal HGD2 and the gate signal LGD2 based on the base drive signal dA.

[0103] In the level conversion circuit 70 configured in the above manner, when the drain terminal and the source terminal of the transistor M3 are controlled to be in a non-conductive state based on the gate signal HGD2, and the drain terminal and the source terminal of the transistor M4 are controlled to be in a conductive state based on the gate signal LGD2, that is, when the reference level switching circuit 710 outputs a reference level switching signal LS at the L level, the midpoint CP1 of the amplifier circuit 550 and the midpoint CP2 of the level conversion circuit 70 are electrically connected via the transistor M4. Therefore, the level conversion circuit 70 outputs the amplified modulation signal AMS1 supplied to the midpoint CP2 via the transistor M4 as a level conversion amplified modulation signal AMS2.

[0104] On the other hand, when the drain terminal and the source terminal of the transistor M3 are controlled to be in a conductive state based on the gate signal HGD2, and the drain terminal and the source terminal of the transistor M4 are controlled to be in a non-conductive state based on the gate signal LGD2, that is, when the reference level switching circuit 710 outputs a reference level switching signal LS at the H level, the midpoint CP1 of the amplifier circuit 550 and the midpoint CP2 of the level conversion circuit 70 are electrically connected via the bootstrap circuit BS and the transistor M3. Therefore, the level conversion circuit 70 outputs the voltage signal VHV3 obtained by level-converting the reference potential of the amplified modulation signal AMS1 based on the voltage signal VHV2 as a level conversion amplified modulation signal AMS2.

[0105] Here, in the following description, the operation mode in which the level conversion circuit 70 outputs a level conversion amplified modulation signal AMS2 with the reference potential for amplifying the modulation signal AMS1 as the ground potential is referred to as the first mode MD1, and the operation mode in which the level conversion circuit 70 outputs a level conversion amplified modulation signal AMS2 that level-converts the reference potential of the amplified modulation signal AMS1 into a voltage signal VHV2 different from and greater than the ground potential is referred to as the second mode MD2. That is, the level conversion circuit 70 becomes the first mode MD1 when the voltage value specified by the base drive signal dA is less than a predetermined threshold voltage, and becomes the second mode MD2 when the voltage value specified by the base drive signal dA is greater than the predetermined threshold voltage.

[0106] The level conversion amplified modulation signal AMS2 output by the level conversion circuit 70 is input to the demodulation circuit 560. The demodulation circuit 560 demodulates by smoothing the level conversion amplified modulation signal AMS2 output by the level conversion circuit 70, thereby generating a drive signal COM and outputting it from the drive circuit 50. In other words, the demodulation circuit 560 outputs the drive signal COM by demodulating the level conversion amplified modulation signal AMS2.

[0107] The demodulation circuit 560 includes an inductor L10 and a capacitor C10. One end of the inductor L10 is electrically connected to the midpoint CP2. The other end of the inductor L10 is electrically connected to one end of the capacitor C10. Moreover, the ground potential is supplied to the other end of the capacitor C10. That is, the inductor L10 and the capacitor C10 constitute a low-pass filter circuit. Thus, the level conversion amplified modulation signal AMS2 output from the level conversion circuit 70 is smoothed and output as the drive signal COM from the drive circuit 50.

[0108] The first feedback circuit 570 and the second feedback circuit 580 feedback the drive signal COM to the correction circuit 510.

[0109] The first feedback circuit 570 has an attenuator 572. The drive signal COM is input to the attenuator 572. Moreover, the attenuator 572 feeds back a first feedback signal VFB1 obtained by attenuating the voltage value of the drive signal COM to the correction circuit 510.

[0110] The second feedback circuit 580 includes capacitors C21, C22, C23, and resistors R21, R22. A drive signal COM is supplied to one end of capacitor C21. The other end of capacitor C21 is connected to one end of resistor R21 and one end of resistor R22. A ground potential is supplied to the other end of resistor R21. Thus, capacitor C21 and resistor R21 function as a high-pass filter. In other words, the second feedback circuit 580 includes a high-pass filter. Through this high-pass filter, the low-frequency components of the drive signal COM input to the second feedback circuit 580 are removed. As a result, a triangular-wave-like signal formed by the ripple components superimposed on the drive signal COM is extracted. Here, the meaning of the triangular-wave-like signal is a signal that, according to the frequency characteristics of the second feedback circuit 580, strictly speaking, is not a triangular wave. Additionally, in the following description, the case where the signal extracted by the second feedback circuit 580 is a triangular wave will be described.

[0111] Furthermore, the other end of resistor R22 is connected to one end of capacitor C22 and one end of capacitor C23. A ground potential is supplied to the other end of capacitor C22. Thus, in the second feedback circuit 580, resistor R22 and capacitor C22 function as a low-pass filter. That is, the second feedback circuit 580 includes a low-pass filter. The cut-off frequency of this low-pass filter is set to be sufficiently higher than the cut-off frequency of the high-pass filter formed by capacitor C21 and resistor R21. Thus, the low-pass filter formed by resistor R22 and capacitor C22 removes the high-frequency noise components overlapping with the output of the high-pass filter formed by capacitor C21 and resistor R21.

[0112] As described above, the second feedback circuit 580 functions as a band-pass filter that allows the signals in a predetermined frequency domain included in the drive signal COM to pass through. And after the second feedback circuit 580 attenuates the signal passing through this band-pass filter via the attenuator 582, it feeds it back to the correction circuit 510 as the second feedback signal VFB2. Thus, through the second feedback circuit 580, a triangular-wave signal is fed back to the correction circuit 510 as the second feedback signal VFB2. The triangular-wave signal is a triangular-wave signal obtained by extracting the high-frequency components included in the drive signal COM, specifically, a triangular-wave signal corresponding to the period of the ripple voltage superimposed on the drive signal COM according to the amplified modulation signal AMS1.

[0113] Here, the driving signal COM output by the driving circuit 50 is a signal obtained by smoothing a level-converted amplified modulation signal AMS2 obtained by level-converting the reference voltage of the amplified modulation signal AMS1 through a low-pass filter included in the demodulation circuit 560. By feeding back the driving signal COM output by such a driving circuit 50 to the correction circuit 510 via the first feedback circuit 570, the driving circuit 50 oscillates self-excitedly at a frequency determined by the delay of the first feedback circuit 570 and the transfer function of the feedback. However, since the delay amount is large in the feedback path via the first feedback circuit 570, there is a case where the self-excited oscillation frequency of the driving circuit 50 cannot be increased to a level where the accuracy of the driving signal COM can be sufficiently ensured. Therefore, in the driving circuit 50 of the present embodiment, a feedback path via the second feedback circuit 580 is provided separately from the feedback path via the first feedback circuit 570. As a result, the high-frequency components included in the driving signal COM can be fed back individually, and thus the delay amount when observing the entire circuit can be reduced. As a result, the frequencies of the correction basic driving signal oA and the modulation signal MS can be increased to a level where the accuracy of the driving signal COM can be sufficiently ensured.

[0114] Thus, in the case where the operating mode is the first mode MD1, the driving circuit 50 outputs the amplified modulation signal AMS1 as the level-converted amplified modulation signal AMS2 without level-converting the reference potential of the amplified modulation signal AMS1 output by the amplifier circuit 550. In such a first mode MD1, when the voltage value at an arbitrary timing of the driving signal COM output by the driving circuit 50 is set to the voltage vcom, the voltage vcom can be expressed by the following formula (1) using the conduction duty AMon of the amplified modulation signal AMS1 and the voltage vhv1 which is the voltage value of the voltage signal VHV1.

[0115] Mathematical formula 1

[0116] vcom = AMon × vhv1…(1)

[0117] Moreover, in view of the fact that the signal obtained by amplifying the modulation signal MS by the amplifier circuit 550 is the amplified modulation signal AMS1, the conduction duty AMon of the amplified modulation signal AMS1 and the conduction duty Mon of the modulation signal MS are substantially equal, and thus the conduction duty AMon in the above formula (1) can be replaced with the conduction duty Mon of the modulation signal MS. Then, the voltage value at an arbitrary timing of the driving signal COM output by the driving circuit 50, that is, the voltage vcom, can be expressed by the following formula (2).

[0118] Mathematical formula 2

[0119] vcom = Mon × vhv1…(2)

[0120] That is, the drive circuit 50 outputs a drive signal COM having a voltage value obtained based on the conduction duty Mon of the modulation signal MS obtained by modulating the corrected basic drive signal oA.

[0121] Next, the conduction duty Mon of the modulation signal MS will be described. Figure 11 FIG. is a diagram for explaining the relationship between the corrected basic drive signal oA and the modulation signal MS. As described above, the corrected basic drive signal oA output from the correction circuit 510 is a signal obtained by subtracting the first feedback signal VFB1 and the second feedback signal VFB2 from the basic drive signal aA output from the DAC 511, and the second feedback signal VFB2 input to the correction circuit 510 is a triangular wave signal obtained based on the period of the ripple voltage superimposed on the drive signal COM according to the frequency of the amplified modulation signal AMS1.

[0122] Therefore, when the voltage value of the basic drive signal aA is set as the voltage vaa, the voltage value of the first feedback signal VFB1 is set as the voltage vfb1, the voltage value of a predetermined bias voltage is set as the voltage vo, and the voltage amplitude of the triangular wave of the second feedback signal VFB2 is set as the amplitude A, the corrected basic drive signal oA becomes a triangular wave having the voltage v1 shown in the following formula (3) as the central value and the voltage value varying within the range of the following formulas (4) to (5) according to the period of the ripple voltage superimposed on the drive signal COM.

[0123] Mathematical formula 3

[0124] v1 = (vaa - vfb1) + vo…(3)

[0125] Mathematical formula 4

[0126] v2 = (vdaa - vfb1) + vo + A / 2…(4)

[0127] Mathematical formula 5

[0128] v3 = (vdaa - vfb1) + vo - A / 2…(5)

[0129] Here, the voltage vo shown in the above formulas (3) to (5) corresponds to the voltage value of a predetermined bias voltage, such as the voltage value of the DC voltage component remaining in the triangular wave of the second feedback signal VFB2 or the voltage value of the bias voltage of the comparator constituting the modulation circuit 520, and any voltage value for correcting the errors or deviations generated in the drive circuit 50.

[0130] Moreover, the modulation circuit 520 compares the voltage value of the corrected base drive signal oA output from the correction circuit 510 with the voltage vref as a reference voltage, and generates and outputs a modulation signal MS. The modulation signal MS becomes an H level when the voltage value of the corrected base drive signal oA is greater than the voltage value of the voltage vref, and becomes an L level when the voltage value of the corrected base drive signal oA is less than the voltage value of the voltage vref.

[0131] At this time, the conduction duty Mon of the modulation signal MS output by the modulation circuit 520 can be based on Figure 11 and is represented by the following equation (6).

[0132] Mathematical formula 6

[0133]

[0134] Furthermore, by substituting equation (3) into the above equation (6), the conduction duty Mon of the modulation signal MS output by the modulation circuit 520 can be represented by the following equation (7).

[0135] Mathematical formula 7

[0136]

[0137] In addition, the voltage vfb1 as the voltage value of the first feedback signal VFB1 is the voltage value obtained by attenuating the voltage vcom as the voltage of the drive signal COM by using the first feedback circuit 570. Therefore, when the attenuation rate of the attenuator 541 included in the first feedback circuit 570 is set to α, the voltage vfb1 as the voltage value of the first feedback signal VFB1 can be represented by the following equation (8).

[0138] Mathematical formula 8

[0139] vfb1 = α × vcom…(8)

[0140] Furthermore, by substituting equations (7) and (8) into the above equation (2) and arranging, the voltage value at any timing of the drive signal COM output by the drive circuit 50 in the first mode MD1, that is, the voltage vcom, can be represented by the following equation (9).

[0141] Mathematical formula 9

[0142]

[0143] On the other hand, in the case where the operation mode is the second mode MD2, the driving circuit 50 outputs, as a level-converted amplified modulation signal AMS2, a signal obtained by converting the reference potential level of the amplified modulation signal AMS1 output from the amplifier circuit 550 into a voltage signal VHV2. In such a second mode MD2, the voltage value at any timing of the driving signal COM output from the driving circuit 50, that is, the voltage vcom, becomes a value obtained by adding the voltage value of the voltage signal VHV2 obtained by level-converting into the above formula (2), that is, the voltage vhv2, and can be expressed by the following formula (10).

[0144] Mathematical formula 10

[0145] vcom = Mon × vhv1 + vhv2…(10)

[0146] Furthermore, by substituting formulas (7) and (8) into the above formula (10) and arranging them, the voltage value at any timing of the driving signal COM output from the driving circuit 50 in the second mode MD2, that is, the voltage vcom, can be expressed by the following formula (11).

[0147] Mathematical formula 11

[0148]

[0149] In the liquid ejecting device 1 of the present embodiment, in the first mode MD1, the voltage vcom of the driving signal COM output from the driving circuit 50 and, in the second mode MD2, the voltage vcom of the driving signal COM output from the driving circuit 50 continuously change based on the basic driving signal dA input to the driving circuit 50. Thereby, the driving circuit 50 outputs Figure 5 a driving signal COM having a signal waveform as shown. However, in the voltage value at any timing of the driving signal COM output from the driving circuit 50 in the first mode MD1, that is, the voltage vcom shown in formula (9), and the voltage value at any timing of the driving signal COM output from the driving circuit 50 in the second mode MD2, that is, the voltage vcom shown in formula (11), the output voltage values are different.

[0150] Specifically, when the voltage value at any timing of the driving signal COM output from the driving circuit 50 in the first mode MD1 is set as the voltage vcom1 and the voltage value at any timing of the driving signal COM output from the driving circuit 50 in the second mode MD2 is set as the voltage vcom2, a potential difference as shown in the following formula (12) occurs between the voltage vcom1 and the voltage vcom2.

[0151] Mathematical formula 12

[0152]

[0153] That is, when the operating mode of the driving circuit 50 changes from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, the voltage value of the driving signal COM output by the driving circuit 50, i.e., the voltage vcom, becomes discontinuous. As a result, deformation may occur in the signal waveform of the driving signal COM output by the driving circuit 50. The deformation of the signal waveform occurring in such a driving signal COM causes deviation in the driving characteristics of the piezoelectric element 60. As a result, the ejection characteristics of the ink may deteriorate in the liquid ejection device 1.

[0154] In view of the above problem, in the liquid ejection device 1 of the present embodiment, the correction circuit 510 of the driving circuit 50 includes a basic driving signal correction circuit 513. Then, the basic driving signal correction circuit 513 subtracts a predetermined correction value from the basic driving signal dA according to the logic level of the reference level switching signal LS output by the reference level switching circuit 710. Thus, when the operating mode of the driving circuit 50 changes from the first mode MD1 to the second mode MD2 and when the operating mode of the driving circuit 50 changes from the second mode MD2 to the first mode MD1, the possibility of deformation occurring in the signal waveform of the driving signal COM output by the driving circuit 50 is reduced. As a result, the possibility of deterioration of the ejection characteristics of the ink in the liquid ejection device 1 is reduced.

[0155] Use Figure 12 to illustrate the operation of the correction circuit 510. Figure 12 FIG. is used to illustrate the relationship between the basic driving signal aA and the reference level switching signal LS. As described above, when the voltage value specified by the basic driving signal dA, which is a digital signal, is a predetermined threshold th, the reference level switching circuit 710 outputs a reference level switching signal LS of the L level. Therefore, the reference level switching signal LS of the L level is input to the basic driving signal correction circuit 513. When the reference level switching signal LS of the L level is input to the basic driving signal correction circuit 513, the basic driving signal correction circuit 513 outputs a correction signal dAJ obtained by adding the basic driving signal dA and "0" as a predetermined correction value Cv1. Therefore, the DAC 511 generates and outputs a basic driving signal aA obtained by performing digital-to-analog conversion on the basic driving signal dA.

[0156] On the other hand, when the voltage value specified by the base drive signal dA, which is a signal in the form of a number, exceeds a predetermined threshold th, the reference level switching circuit 710 outputs a reference level switching signal LS of H level. Therefore, the reference level switching signal LS of H level is input to the base drive signal correction circuit 513. When the reference level switching signal LS of H level is input to the base drive signal correction circuit 513, the base drive signal correction circuit 513 subtracts the correction signal dAJ obtained by subtracting the correction value calculated based on the above formula (12) from the base drive signal dA as a predetermined correction value Cv2. Therefore, the DAC 511 generates and outputs a base drive signal aA having a voltage value reduced by the correction value Cv2 compared to the base drive signal dA.

[0157] Therefore, in the first mode MD1 in which the level conversion circuit 70 outputs a level conversion amplified modulation signal AMS2 having a reference potential of the amplified modulation signal AMS1 set to the ground potential, the correction circuit 510 outputs a corrected base drive signal oA corrected according to the correction value Cv1, and in the second mode MD2 in which the level conversion circuit 70 outputs a level conversion amplified modulation signal AMS2 that converts the reference potential level of the amplified modulation signal AMS1 into a voltage signal VHV2 different from the ground potential, the correction circuit 510 outputs a corrected base drive signal oA corrected according to a correction value Cv2 different from the correction value Cv1, specifically, according to the correction value calculated based on the formula (12).

[0158] Thus, even when the operating mode of the drive circuit 50 is switched from the first mode MD1 to the second mode MD2 and when the operating mode of the drive circuit 50 is switched from the second mode MD2 to the first mode MD1, the voltage value of the drive signal COM, that is, the voltage vcom, continuously changes. As a result, the possibility of distortion occurring in the signal waveform of the drive signal COM is reduced. Therefore, the possibility of deterioration in the ejection characteristics of the ink in the liquid ejection device 1 is reduced.

[0159] Here, the base drive signal correction circuit 513 may also output a correction signal dAJ obtained by adding the base drive signal dA and the correction value based on the above formula (12) as a predetermined correction value Cv1 when a reference level switching signal LS of L level is input from the reference level switching circuit 710, and output a correction signal dAJ obtained by adding the base drive signal dA and "0" as a predetermined correction value Cv2 when a reference level switching signal LS of H level is input.

[0160] In addition, the values used for the correction values Cv1 and Cv2 are not limited to the values calculated by the above formula (12). For example, they can also be values obtained by taking into account errors or deviations generated in the drive circuit 50, losses that may occur during the operation of the drive circuit 50, etc. in the values calculated by the above formula (12). In addition, the correction values Cv1 and Cv2 can be calculated each time by the basic drive signal correction circuit 513 or an arithmetic circuit (not shown), or can be stored in a storage circuit (not shown).

[0161] Here, the piezoelectric element 60 is an example of a capacitive load, and the drive circuit 50 corresponds to a capacitive load drive circuit. Moreover, the drive signal COM output by the drive circuit 50 is an example of a drive signal, and in view of the fact that the drive signal VOUT is generated based on the drive signal COM, the drive signal VOUT is also an example of a drive signal. Moreover, the midpoint CP1 is an example of a first output point, and the midpoint CP2 is an example of a second output point. In addition, the second feedback circuit 580 is an example of a feedback circuit. In addition, the ground potential is an example of a first potential, and the potential based on the voltage vhv2 different from the ground potential is an example of a second potential. In addition, the correction value Cv1 is an example of a first correction value, and the correction value Cv2 is an example of a second correction value. In addition, the gate signal HGD1 is an example of a first gate signal, the gate signal LGD1 is an example of a second gate signal, and the gate driver circuit 530 that outputs the gate signal HGD1 and the gate signal LGD1 is an example of a first gate driver circuit. In addition, the gate signal HGD2 is an example of a third gate signal, the gate signal LGD2 is an example of a fourth gate signal, and the gate driver circuit 730 that outputs the gate signal HGD2 and the gate signal LGD2 is an example of a second gate driver circuit. In addition, the transistor M1 is an example of a first transistor, the transistor M2 is an example of a second transistor, the transistor M3 is an example of a third transistor, and the transistor M4 is an example of a fourth transistor. In addition, the voltage signal VHV1 is an example of a first voltage signal, the ground potential is an example of a second voltage signal, the voltage signal VHV2 is an example of a third voltage signal, and the voltage signal VHV3 is an example of a fourth voltage signal. Moreover, a voltage value less than a predetermined threshold voltage in the voltage value specified by the basic drive signal dA is an example of a first voltage value, and a voltage value equal to or higher than the predetermined threshold voltage in the voltage value specified by the basic drive signal dA is an example of a second voltage value.

[0162] 1.5 Effects

[0163] As described above, in the first mode MD1 in which the level conversion circuit 70 outputs the level conversion amplified modulation signal AMS2 with the reference potential of the amplified modulation signal AMS1 set to the ground potential, the output correction circuit 510 of the drive circuit 50 outputs the corrected basic drive signal oA corrected according to the correction value Cv1. And in the second mode MD2 in which the level conversion circuit 70 outputs the level conversion amplified modulation signal AMS2 with the reference potential of the amplified modulation signal AMS1 level-converted to the potential based on the voltage vhv2 different from the ground potential, it outputs the corrected basic drive signal oA corrected according to the correction value Cv2 different from the correction value Cv1. Further, the modulation circuit 520 outputs the modulation signal MS obtained by modulating the corrected basic drive signal oA, the amplifier circuit 550 outputs the amplified modulation signal AMS1 obtained by amplifying the modulation signal MS, the level conversion circuit 70 outputs the level conversion amplified modulation signal AMS2 obtained by level-converting the reference potential of the amplified modulation signal AMS1, and the demodulation circuit 560 outputs the drive signal COM by demodulating the level conversion amplified modulation signal AMS2. That is, the drive circuit 50 of the liquid ejection device 1 according to the present embodiment generates and outputs the drive signal COM based on the corrected basic drive signal oA obtained by correcting the basic drive signal dA using different correction values Cv1 and Cv2 corresponding to the operation mode output from the correction circuit 510. Thereby, even when changing from the first mode MD1 to the second mode MD2 and when changing from the second mode MD2 to the first mode MD1, the possibility of distortion occurring in the signal waveform of the drive signal COM is reduced. That is, the waveform accuracy of the drive signal COM output from the drive circuit 50 is improved, and as a result, the ejection accuracy of the ink in the liquid ejection device 1 including the drive circuit 50 is further improved.

[0164] 2. Second Embodiment

[0165] Next, the liquid ejection device 1 and the drive circuit 50 of the second embodiment will be described. Although in the liquid ejection device 1 and the drive circuit 50 of the first embodiment, the method of generating the corrected basic drive signal oA by correcting the digital basic drive signal dA input to the drive circuit 50 through the correction circuit 510 has been described, in the liquid ejection device 1 and the drive circuit 50 of the second embodiment, after the correction circuit 510 converts the basic drive signal dA, which is a digital signal, into the basic drive signal aA, which is an analog signal, a predetermined correction value is subtracted from the basic drive signal aA to generate the corrected basic drive signal oA. In this regard, it is different from the liquid ejection device 1 and the drive circuit 50 of the first embodiment. In addition, when describing the liquid ejection device 1 and the drive circuit 50 of the second embodiment, the same reference numerals are given to the same structures as those of the liquid ejection device 1 and the drive circuit 50 of the first embodiment, and their descriptions are simplified or omitted.

[0166] Figure 13 FIG. showing an example of the functional structure of the drive circuit 50 of the second embodiment. As Figure 13 shown, in the drive circuit 50 of the modified example, the correction circuit 510 includes a DAC 511, adders 514, 515, 516, and a correction voltage generation circuit 517.

[0167] The DAC circuit 511 performs digital-to-analog conversion on the basic drive signal dA, which is a digital signal, to generate and output the basic drive signal aA, which is an analog signal.

[0168] In the correction voltage generation circuit 517, a reference level switching signal LS is input from the level conversion circuit 70. Moreover, the correction voltage generation circuit 517 generates a correction voltage VCB corresponding to the logical level of the input reference level switching signal LS. Specifically, the correction voltage generation circuit 517 generates correction voltages VCB having different voltage values when the reference level switching signal LS of L level is input and when the reference level switching signal LS of H level is input.

[0169] The basic drive signal aA is input to one of the + side input terminals of the adder 514, and the correction voltage VCB is input to the other of the + side input terminals of the adder 514. The adder 514 outputs a signal obtained by correcting the basic drive signal aA based on the correction voltage VCB by subtracting the correction voltage VCB from the basic drive signal aA.

[0170] The signal output by the adder 514 is input to the input terminal on the + side of the adder 515, and the first feedback signal VFB1 is input to the input terminal on the - side of the adder 515. Moreover, the adder 515 outputs a signal obtained by subtracting the first feedback signal VFB1 from the basic drive signal aA. The signal output by the adder 515 is input to the input terminal on the + side of the adder 516, and the second feedback signal VFB2 is input to the input terminal on the - side of the adder 516. Moreover, the adder 516 outputs, as the corrected basic drive signal oA, the signal obtained by subtracting the second feedback signal VFB2 from the signal output by the adder 515 from the correction circuit 510.

[0171] Moreover, the drive circuit 50 generates and outputs a drive signal COM based on the corrected basic drive signal oA output by the correction circuit 510 in the same manner as in the first embodiment.

[0172] Even for the liquid ejection device 1 and the drive circuit 50 including the drive circuit 50 having the correction circuit 510 configured in the above manner, the same effects as those of the liquid ejection device 1 and the drive circuit 50 of the first embodiment can be achieved.

[0173] Here, the basic drive signal aA based on the basic drive signal dA is an example of the basic drive signal of the second embodiment. When the reference level switching signal LS of L level is input, the voltage value of the correction voltage VCB output by the correction voltage generation circuit 517 is an example of the first correction value of the second embodiment. When the reference level switching signal LS of H level is input, the voltage value of the correction voltage VCB output by the correction voltage generation circuit 517 is an example of the second correction value of the second embodiment.

[0174] 3. Third Embodiment

[0175] Next, the liquid ejection device 1 and the drive circuit 50 of the third embodiment will be described. In the liquid ejection device 1 and the drive circuit 50 of the third embodiment, the level conversion circuit 70 has a timing control circuit 711, which is different from the liquid ejection device 1 and the drive circuit 50 of the first and second embodiments. In addition, when describing the liquid ejection device 1 and the drive circuit 50 of the third embodiment, the same reference numerals are given to the same structures as those of the liquid ejection device 1 and the drive circuit 50 of the first and second embodiments, and the description thereof is simplified or omitted.

[0176] Figure 14 FIG. showing an example of the functional structure of the drive circuit 50 of the third embodiment. As Figure 14As shown, in the drive circuit 50 of the third embodiment, the level conversion circuit 70 has a timing control circuit 711. A reference level switching signal LS output from the reference level switching circuit 710 is input to the timing control circuit 711. The timing control circuit 711 outputs to the gate driver circuit 730 after delaying the input reference level switching signal LS by a certain time.

[0177] There is a case where the time until the transistors M3 and M4 of the level conversion circuit 70 are controlled according to the logic level of the reference level switching signal LS output from the reference level switching circuit 710 is different from the time until the amplifier circuit 550 is controlled according to the corrected basic drive signal oA that reflects the correction after the basic drive signal dA or the basic drive signal aA is corrected based on the logic level of the reference level switching signal LS output from the reference level switching circuit 710.

[0178] The timing control circuit 711 corrects the possible time difference between the time until the transistors M3 and M4 of the level conversion circuit 70 are controlled according to the logic level of the reference level switching signal LS output from the reference level switching circuit 710 and the time until the amplifier circuit 550 is controlled according to the corrected basic drive signal oA that reflects the correction after the basic drive signal dA or the basic drive signal aA is corrected based on the logic level of the reference level switching signal LS output from the reference level switching circuit 710. Thereby, the waveform accuracy of the drive signal COM output from the drive circuit 50 is further improved.

[0179] 4. Fourth Embodiment

[0180] Next, the liquid ejection device 1 and the drive circuit 50 of the fourth embodiment will be described. In the liquid ejection device 1 and the drive circuit 50 of the fourth embodiment, they are different from the liquid ejection device 1 and the drive circuit 50 of the first, second, and third embodiments in that the level conversion circuit 70 is configured in multiple stages. In addition, when describing the liquid ejection device 1 and the drive circuit 50 of the fourth embodiment, the same structures as those of the liquid ejection device 1 and the drive circuit 50 of the first, second, and third embodiments are denoted by the same reference numerals, and their descriptions are simplified or omitted.

[0181] Figure 15 FIG. is an example showing the functional structure of the drive circuit 50 of the fourth embodiment. As Figure 15As shown, the drive circuit 50 of the fourth embodiment includes a level conversion circuit 70a and a level conversion circuit 70b. Here, both the level conversion circuit 70a and the level conversion circuit 70b have the same structure as the level conversion circuit 70 of the first embodiment and perform the same operations. Additionally, in Figure 15 in order to distinguish the various structures of the level conversion circuit 70a from the various structures of the level conversion circuit 70b, an "a" is appended to the end of the symbol of the structure of the level conversion circuit 70a corresponding to the various structures of the level conversion circuit 70 of the first embodiment, and a "b" is appended to the end of the symbol of the structure of the level conversion circuit 70b. Specifically, the structure of the level conversion circuit 70a corresponding to the reference level switching circuit 710 of the level conversion circuit 70 of the first embodiment is referred to as the reference level switching circuit 710a, and the structure of the level conversion circuit 70b is referred to as the reference level switching circuit 710b.

[0182] Similarly, in order to distinguish the various signals generated by the level conversion circuit 70a from the various signals generated by the level conversion circuit 70b, an "a" is appended to the end of the symbol of the signal of the level conversion circuit 70a corresponding to the various signals generated by the level conversion circuit 70 of the first embodiment, and a "b" is appended to the end of the symbol of the signal of the level conversion circuit 70b corresponding to the various signals generated by the level conversion circuit 70 of the first embodiment. Specifically, the signal of the level conversion circuit 70a corresponding to the reference level switching signal LS of the level conversion circuit 70 of the first embodiment is referred to as the reference level switching signal LSa, and the signal of the level conversion circuit 70b is referred to as the reference level switching signal LSb.

[0183] In the level conversion circuit 70a, a basic drive signal dA and an amplified modulation signal AMS1 output by the amplifier circuit 550 are input. Moreover, when the voltage value specified by the basic drive signal dA is equal to or higher than a predetermined threshold voltage, the level conversion circuit 70a outputs a level conversion amplified modulation signal AMS2a obtained by converting the reference potential level of the input amplified modulation signal AMS1 to the voltage value of a voltage signal VHV2A, which is the voltage vhv2a, and when the voltage value specified by the basic drive signal dA is less than the predetermined threshold voltage, the input amplified modulation signal AMS1 is output as the level conversion amplified modulation signal AMS2a.

[0184] In the level conversion circuit 70b, a basic drive signal dA and a level conversion amplified modulation signal AMS2a output from the level conversion circuit 70a are input. Further, when the voltage value defined by the basic drive signal dA is equal to or higher than a predetermined threshold voltage, the level conversion circuit 70b outputs a level conversion amplified modulation signal AMS2b in which the reference potential level of the input level conversion amplified modulation signal AMS2a is converted to a voltage value vhv2b of a voltage signal VHV2b. When the voltage value defined by the basic drive signal dA is less than the predetermined threshold voltage, the level conversion circuit 70b outputs the input level conversion amplified modulation signal AMS2a as the level conversion amplified modulation signal AMS2b.

[0185] The level conversion amplified modulation signal AMS2b output from the level conversion circuit 70b is input to the demodulation circuit 560. The demodulation circuit 560 demodulates the input level conversion amplified modulation signal AMS2b to generate a drive signal COM. The drive signal COM is output from the drive circuit 50.

[0186] In addition, when the voltage value defined by the input basic drive signal dA is equal to or higher than the predetermined threshold voltage, a reference level switching circuit 710a included in the level conversion circuit 70a generates a reference level switching signal LSa of H level and outputs the signal to the gate driver circuit 730a and the correction circuit 510. When the voltage value defined by the basic drive signal dA is less than the threshold voltage, the reference level switching circuit 710a generates a reference level switching signal LSa of L level and outputs the signal to the gate driver circuit 730a and the correction circuit 510.

[0187] Similarly, when the voltage value defined by the input basic drive signal dA is equal to or higher than the predetermined threshold voltage, a reference level switching circuit 710b included in the level conversion circuit 70b generates a reference level switching signal LSb of H level and outputs the signal to the gate driver circuit 730b and the correction circuit 510. When the voltage value defined by the basic drive signal dA is less than the threshold voltage, the reference level switching circuit 710b generates a reference level switching signal LSb of L level and outputs the signal to the gate driver circuit 730b and the correction circuit 510.

[0188] Here, the threshold voltage at which the logic level of the reference level switching signal LSa output by the reference level switching circuit 710a included in the level conversion circuit 70a is switched, and the threshold voltage at which the logic level of the reference level switching signal LSb output by the reference level switching circuit 710b included in the level conversion circuit 70b is switched are different. Specifically, the threshold voltage at which the logic level of the reference level switching signal LSa output by the reference level switching circuit 710a included in the level conversion circuit 70a is switched is smaller than the threshold voltage at which the logic level of the reference level switching signal LSb output by the reference level switching circuit 710b included in the level conversion circuit 70b is switched.

[0189] The correction circuit 510 outputs a corrected basic drive signal oA obtained by correcting the basic drive signal dA or the basic drive signal aA based on a correction value according to the logic levels of the reference level switching signal LSa output by the reference level switching circuit 710a and the reference level switching signal LSb output by the reference level switching circuit 710b. The drive circuit 50 generates and outputs a drive signal COM based on the corrected basic drive signal oA output by the correction circuit 510.

[0190] Even when using the liquid ejecting device 1 including the drive circuit 50 having the correction circuit 510 configured in the above-described manner and the drive circuit 50, the same operational effects as those of the liquid ejecting device 1 and the drive circuit 50 of the first embodiment can be achieved.

[0191] As described above, although the embodiments and modification examples have been described, the present invention is not limited to these embodiments, and can be implemented in various ways without departing from the gist thereof. For example, the above-described embodiments can also be appropriately combined.

[0192] The present invention includes a structure substantially the same as the structure described in the embodiment (for example, a structure having the same function, method, and result, or a structure having the same purpose and effect). In addition, the present invention includes a structure in which a non-essential part of the structure described in the embodiment is replaced. In addition, the present invention includes a structure that can achieve the same operational effect as the structure described in the embodiment, or a structure that can achieve the same purpose. In addition, the present invention includes a structure in which a well-known technique is added to the structure described in the embodiment.

[0193] Based on the above-described embodiment, the following can be derived.

[0194] One aspect of the liquid ejection device includes: a liquid ejection head having a capacitive load driven by being supplied with a drive signal, and ejecting liquid by driving the capacitive load; a capacitive load drive circuit that outputs the drive signal, the capacitive load drive circuit having: a correction circuit that outputs a corrected basic drive signal obtained by correcting a basic drive signal that is the basis of the drive signal; a modulation circuit that outputs a modulation signal obtained by modulating the corrected basic drive signal; an amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by performing level conversion on the reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulation signal; a feedback circuit that feeds back the drive signal to the correction circuit, and the correction circuit outputs the corrected basic drive signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal having the reference potential of the amplified modulation signal set to a first potential, and outputs the corrected basic drive signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal having the reference potential of the amplified modulation signal level-converted to a second potential different from the first potential.

[0195] According to this liquid ejection device, depending on whether the level conversion circuit is in a first mode of outputting a level-converted amplified modulation signal having the reference potential of the amplified modulation signal set to a first potential or in a second mode of outputting a level-converted amplified modulation signal having the reference potential of the amplified modulation signal level-converted to a second potential different from the first potential, the correction circuit corrects the basic drive signal that is the basis of the drive signal and outputs it as the corrected basic drive signal. And by generating the drive signal based on the corrected basic drive signal, even when the level conversion circuit changes from the first mode to the second mode, the possibility of distortion occurring in the signal waveform of the drive signal can be reduced. Therefore, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved, and thus the ejection accuracy of the liquid in the liquid ejection device is improved.

[0196] In one aspect of the liquid ejection device, it can also be set that the level conversion circuit becomes the first mode when the voltage value specified by the basic drive signal is a first voltage value, and becomes the second mode when the voltage value specified by the basic drive signal is a second voltage value greater than the first voltage value.

[0197] According to the liquid ejection device, since the correction circuit corrects the basic drive signal that is the basis of the drive signal according to whether it is the first mode or the second mode and outputs it as the corrected basic drive signal, even when the voltage value specified by the basic drive signal is the first voltage value and it becomes the first mode, and when the voltage value specified by the basic drive signal is the second voltage value that is larger than the first voltage value and it becomes the second mode, the possibility of distortion occurring in the signal waveform of the drive signal can be reduced. Therefore, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved, and thus the ejection accuracy of the liquid in the liquid ejection device is improved.

[0198] In one aspect of the liquid ejection device, it may also be configured that the amplifier circuit includes: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal, the other end electrically connected to the first output point, and operating based on the first gate signal; and a second transistor having one end electrically connected to the first output point, the other end supplied with a second voltage signal, and operating based on the second gate signal.

[0199] In one aspect of the liquid ejection device, it may also be configured that the level conversion circuit includes: a bootstrap circuit that is input with a third voltage signal and the amplified modulation signal and outputs a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a second gate driver circuit that outputs a third gate signal and a fourth gate signal based on the basic drive signal; a third transistor having one end supplied with the fourth voltage signal, the other end electrically connected to the second output point, and operating based on the third gate signal; and a fourth transistor having one end electrically connected to the second output point, the other end supplied with the amplified modulation signal, and operating based on the fourth gate signal.

[0200] In one aspect of the liquid ejection device, it may also be configured that the feedback circuit includes a high-pass filter.

[0201] In one aspect of the liquid ejection device, it may also be configured that the feedback circuit includes a low-pass filter.

[0202] In one aspect of the liquid ejection device, it may also be configured that the capacitive load is a piezoelectric element.

[0203] One type of capacitive load driving circuit is a capacitive load driving circuit that outputs a driving signal to a liquid ejection head. The liquid ejection head has a capacitive load that is driven by being supplied with the driving signal, and ejects liquid by driving the capacitive load. The capacitive load driving circuit includes: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal that is the basis of the driving signal; a modulation circuit that outputs a modulation signal obtained by modulating the corrected basic driving signal; an amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by performing level conversion on the reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal; and a feedback circuit that feeds back the driving signal to the correction circuit. The correction circuit outputs the corrected basic driving signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is set to a first potential, and outputs the corrected basic driving signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is level-converted to a second potential different from the first potential.

[0204] According to this capacitive load driving circuit, depending on whether the level conversion circuit outputs the level-converted amplified modulation signal obtained by setting the reference potential of the amplified modulation signal to the first potential (first mode) or outputs the level-converted amplified modulation signal obtained by level-converting the reference potential of the amplified modulation signal to a second potential different from the first potential (second mode), the correction circuit corrects the basic driving signal that is the basis of the driving signal and outputs it as the corrected basic driving signal. Moreover, by generating the driving signal based on the corrected basic driving signal, even when the level conversion circuit changes from the first mode to the second mode, the possibility of distortion occurring in the signal waveform of the driving signal can be reduced. Therefore, the waveform accuracy of the driving signal output by the capacitive load driving circuit is improved.

[0205] Symbol Explanation

[0206] 1... Liquid ejection device; 2... Moving body; 3... Moving unit; 4... Conveying unit; 10... Control unit; 11... Power supply circuit; 20... Head unit; 21... Liquid ejection head; 24... Carriage; 31... Carriage motor; 32... Carriage guide shaft; 33... Timing belt; 40... Platen; 41... Conveying motor; 42... Conveying roller; 50... Driving circuit; 60... Piezoelectric element; 70... Level conversion circuit; 100... Control section; 190... Cable; 200... Driving signal selection circuit; 210... Selection control circuit; 212... Shift register; 214... Latch circuit; 216... Decoder; 230... Selection circuit; 232... Inverter; 234... Transmission gate; 510... Correction circuit; 511... DAC circuit; 513... Basic driving signal correction circuit; 514 - 516... Adder; 517... Correction voltage generation circuit; 520... Modulation circuit; 521... Inverter; 530... Gate driver circuit; 531, 532... Gate driver; 550... Amplification circuit; 560... Demodulation circuit; 570... First feedback circuit; 572... Attenuator; 580... Second feedback circuit; 582... Attenuator; 600... Ejection section; 601... Piezoelectric body; 611, 612... Electrodes; 621... Vibration plate; 631... Chamber; 632... Nozzle plate; 641... Reservoir; 651... Nozzle; 710... Reference level switching circuit; 711... Timing control circuit; 721... Inverter; 730... Gate driver circuit; 731, 732... Gate driver; BS... Bootstrap circuit; C1, C10 - C13, C21 - C23... Capacitors; CP1, CP2... Midpoints; D1, D11 - D13... Diodes; L... Nozzle array; L10... Inductor; M1 - M4... Transistors; P... Medium; R21, R22... Resistors.

Claims

1. A liquid ejection device, characterized in that, Comprising: A liquid ejection head having a capacitive load driven by being supplied with a drive signal, and ejecting liquid by driving the capacitive load; A capacitive load drive circuit that outputs the drive signal, The capacitive load drive circuit having: A correction circuit that outputs a corrected basic drive signal obtained by correcting a basic drive signal that is the basis of the drive signal; A modulation circuit that outputs a modulation signal obtained by modulating the corrected basic drive signal; An amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; A level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting the reference potential of the amplified modulation signal to a second output point; A demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulation signal; A feedback circuit that feeds back the drive signal to the correction circuit, The correction circuit outputs the corrected basic drive signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is set to a first potential, and The correction circuit outputs the corrected basic drive signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is level-converted to a second potential different from the first potential.

2. The liquid ejection device according to claim 1, wherein: The level conversion circuit becomes the first mode when the voltage value specified by the basic drive signal is a first voltage value, and becomes the second mode when the voltage value specified by the basic drive signal is a second voltage value larger than the first voltage value.

3. The liquid ejection device according to claim 1 or 2, wherein: The amplification circuit has: A first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; A first transistor having one end supplied with a first voltage signal, the other end electrically connected to the first output point, and operating based on the first gate signal; A second transistor having one end electrically connected to the first output point, the other end supplied with a second voltage signal, and operating based on the second gate signal.

4. The liquid ejection device according to claim 1, wherein: The level conversion circuit has: A bootstrap circuit that is input with a third voltage signal and the amplified modulation signal, and outputs a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; A second gate driver circuit that outputs a third gate signal and a fourth gate signal based on the basic drive signal; A third transistor having one end supplied with the fourth voltage signal, the other end electrically connected to the second output point, and operating based on the third gate signal; A fourth transistor, one end of which is electrically connected to the second output point, the other end of which is supplied with the amplified modulation signal, and which operates based on the fourth gate signal.

5. The liquid ejecting apparatus according to claim 1, wherein the feedback circuit includes a high-pass filter.

6. The liquid ejecting apparatus according to claim 5, wherein the feedback circuit includes a low-pass filter.

7. The liquid ejecting apparatus according to claim 1, wherein the capacitive load is a piezoelectric element.

8. A capacitive load driving circuit, characterized in that, It outputs a drive signal to a liquid ejection head, the liquid ejection head having a capacitive load that is driven by being supplied with the drive signal and ejecting liquid by driving the capacitive load, the capacitive load drive circuit includes: a correction circuit that outputs a corrected basic drive signal obtained by correcting a basic drive signal that is the basis of the drive signal; a modulation circuit that outputs a modulation signal obtained by modulating the corrected basic drive signal; an amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting the reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulation signal; a feedback circuit that feeds back the drive signal to the correction circuit, the correction circuit outputs the corrected basic drive signal corrected according to a first correction value in a first mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is set to a first potential, and the correction circuit outputs the corrected basic drive signal corrected according to a second correction value different from the first correction value in a second mode in which the level conversion circuit outputs the level-converted amplified modulation signal in which the reference potential of the amplified modulation signal is level-converted to a second potential different from the first potential.

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