Liquid ejection device and capacitive load driving circuit

Abstract

The present invention provides a liquid ejection device and a capacitive load driving circuit. The liquid ejection device comprises: a liquid ejection head having a plurality of capacitive loads driven by a driving signal, and ejecting liquid by driving the plurality of capacitive loads; a capacitive load driving circuit outputting a driving signal, the capacitive load driving circuit comprising: a correction circuit outputting a corrected basic driving signal obtained by correcting the basic driving signal; a modulation circuit outputting a modulated signal obtained by modulating the corrected basic driving signal; an amplifier circuit outputting an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit including a capacitor, and outputting a driving signal by demodulating the amplified modulated signal; and a feedback circuit feeding back the driving signal to the correction circuit, the correction circuit outputting a corrected basic driving signal corrected according to the number of driving capacitive loads driven by the driving signal.

Description

Technical Field

[0001] The invention relates to a liquid ejecting device and a capacitive load driving circuit. Background Art

[0002] Among liquid ejecting devices that eject liquid to form images and documents on a medium, there is known a liquid ejecting device that uses a capacitive load such as a piezoelectric element. In such a liquid ejecting device, a capacitive load is provided corresponding to each of a plurality of nozzles that eject liquid, and is driven according to a drive signal. Furthermore, by driving the capacitive load, liquid is ejected from the nozzle provided corresponding to the capacitive load. In order for such a capacitive load to operate, it is necessary to supply sufficient current. Therefore, a capacitive load driving circuit that outputs a drive signal for driving the capacitive load is constructed to include an amplifier circuit that amplifies a source signal that serves as a basis for the drive signal through an amplifier circuit.

[0003] Patent document 1 discloses a drive circuit that outputs a drive signal for driving a piezoelectric element as one of capacitive loads (capacitive load drive circuit), and includes a class D amplifier circuit as an amplifier circuit.

[0004] However, from the perspective of further improving the ejection accuracy of the liquid in the liquid ejection device and further improving the waveform accuracy of the drive signal output by the capacitive load drive circuit, the technology described in Patent Document 1 is not sufficient and there is room for improvement.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-164779 Summary of the Invention

[0006] One embodiment of the liquid ejection device involved in the present invention comprises: a liquid ejection head, which has a plurality of capacitive loads driven by being supplied with a drive signal, and ejects liquid by driving the plurality of capacitive loads; a capacitive load driving circuit, which outputs the drive signal, and the capacitive load driving circuit has: a correction circuit, which outputs a corrected basic drive signal obtained by correcting a basic drive signal that serves as a basis for the drive signal; a modulation circuit, which outputs a modulated signal obtained by modulating the corrected basic drive signal; an amplifier circuit, which outputs an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit, which includes a capacitor, and outputs the drive signal by demodulating the amplified modulated signal; a feedback circuit, which feeds back the drive signal to the correction circuit, and the correction circuit outputs the corrected basic drive signal that is corrected according to the number of driven capacitive loads driven by the drive signal among the plurality of capacitive loads.

[0007] One embodiment of the capacitive load driving circuit involved in the present invention is a capacitive load driving circuit that outputs a driving signal to a liquid ejection head, wherein the liquid ejection head has a plurality of capacitive loads that are driven by being supplied with the driving signal and ejects liquid by driving the plurality of capacitive loads, and the capacitive load driving circuit has: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal that is the basis of the driving signal; a modulation circuit that outputs a modulated signal obtained by modulating the corrected basic driving signal; an amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit that includes a capacitor and outputs the driving signal by demodulating the amplified modulated signal; and a feedback circuit that feeds back the driving signal to the correction circuit, and the correction circuit outputs the corrected basic driving signal that is corrected according to the number of driving capacitive loads driven by the driving signal among the plurality of capacitive loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A diagram showing an example of the structure of a liquid ejecting device.

[0009] Figure 2 This is a diagram showing an example of the functional structure of a liquid ejecting device.

[0010] Figure 3 A diagram showing an example of the arrangement of a plurality of ejection parts in a head unit.

[0011] Figure 4 This is a diagram showing an example of the structure of the ejection portion.

[0012] Figure 5 3 is a diagram showing an example of the signal waveform of the drive signal COM.

[0013] Figure 6 A diagram showing an example of the configuration of a drive signal selection circuit.

[0014] Figure 7 A diagram showing an example of decoded content in a decoder.

[0015] Figure 8 This is a diagram showing an example of the configuration of a selection circuit corresponding to the amount of one ejection unit.

[0016] Figure 9 This is a diagram for explaining the operation of the drive signal selection circuit.

[0017] Figure 10 A diagram showing an example of the configuration of a driving circuit.

[0018] Figure 11 A diagram for explaining the relationship between the correction base drive signal and the modulation signal.

[0019] Figure 12 FIG. 4 is a diagram showing an example of the DAC correction signal VDAC when the number of piezoelectric elements driven by the drive signal VOUT is large.

[0020] Figure 13 This is a diagram showing an example of the DAC correction signal VDAC when the number of piezoelectric elements driven by the drive signal VOUT is small.

[0021] Figure 14 This is a diagram showing a specific example of a method for calculating the total number of piezoelectric elements driven by the drive signal VOUT based on the drive signal COM.

[0022] Figure 15 A diagram showing the configuration of a drive circuit according to a second embodiment. DETAILED DESCRIPTION

[0023] The following drawings illustrate preferred embodiments of the present invention. The drawings are provided for ease of explanation. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the technical solution. Furthermore, not all of the structures described below are necessarily essential components of the present invention.

[0024] In the following description, a consumer inkjet printer is used as an example of the liquid ejection device involved in the present invention. However, the liquid ejection device is not limited to consumer inkjet printers. For example, the liquid ejection device may be a color material ejection device used in the manufacture of color filters for liquid crystal displays, an electrode material ejection device used in the formation of electrodes for organic EL (electroluminescence) displays and surface-emitting displays, or a bio-organic material ejection device used in the manufacture of biochips.

[0025] 1. First Implementation

[0026] 1.1 Structure of liquid ejection device

[0027] Figure 1 FIG. 1 is a diagram showing an example of the structure of the liquid ejecting device 1. Figure 1 As shown, the liquid ejecting apparatus 1 includes a movable body 2 and a moving unit 3 that moves the movable body 2 back and forth in a main scanning direction.

[0028] The moving unit 3 includes a carriage motor 31 serving as a driving source for reciprocating movement along the main scanning direction of the movable body 2 , a carriage guide shaft 32 fixed at both ends, and a timing belt 33 extending substantially parallel to the carriage guide shaft 32 and driven by the carriage motor 31 .

[0029] The movable body 2 has a carriage 24. The carriage 24 is supported on a carriage guide shaft 32 so as to be able to move back and forth freely, and is fixed to a portion of a timing belt 33. Then, by utilizing the carriage motor 31 to move the timing belt 33 forward and backward, the movable body 2 having the carriage 24 is guided by the carriage guide shaft 32 and moves back and forth. In addition, the head unit 20 is located on a portion of the movable body 2 that is opposite to the medium P. That is, the head unit 20 is mounted on the carriage 24. In addition, a plurality of nozzles that eject ink as a liquid are located on the surface of the head unit 20 that is opposite to the medium P. In addition, various control signals for controlling the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. As such a cable 190, a flexible flat cable or the like that can slide to follow the back and forth movement of the movable body 2 can be used.

[0030] The liquid ejecting apparatus 1 further includes a transport unit 4 that transports the medium P along a transport direction onto the platen 40. The transport unit 4 includes a transport motor 41 serving as a drive source for transporting the medium P, and transport rollers 42 that are rotated by the transport motor 41 to transport the medium P along the transport direction.

[0031] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is transported by the transport unit 4. Thus, the ink ejected by the head unit 20 lands at a desired position on the medium P, resulting in the formation of a desired image and text on the surface of the medium P.

[0032] Next, the functional structure of the liquid ejecting device 1 will be described. Figure 2 FIG. 1 is a diagram showing an example of the functional structure of the liquid ejecting device 1. Figure 2 As shown, the liquid ejecting device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0033] The control unit 10 includes a power supply circuit 11 , a control unit 100 , and a drive circuit 50 .

[0034] The power supply circuit 11 generates voltage signals VHV and VDD of predetermined voltage values ​​from a commercial AC power source supplied from outside the liquid ejection device 1, and outputs these voltage signals to various components of the liquid ejection device 1. Here, the voltage signal VHV output by the power supply circuit 11 is, for example, a 42V DC voltage, and the voltage signal VDD is, for example, a 3.3V DC voltage. Such a power supply circuit 11 may also be configured to include, for example, an AC / DC converter that generates the voltage signal VHV from the commercial AC power source, and a DC / DC converter that generates the voltage signal VDD from the voltage signal VHV. Furthermore, in addition to outputting the voltage signals VHV and VDD, the power supply circuit 11 may also output DC voltages of varying voltage values.

[0035] The control unit 100 is supplied with image data from an external device (not shown), such as a host computer, which is provided outside the liquid ejection device 1. The control unit 100 applies various image processing and the like to the supplied image data to generate various control signals for controlling various components of the liquid ejection device 1, and outputs the control signals to the corresponding components.

[0036] Specifically, the control unit 100 generates a control signal Ctrl1 for controlling the reciprocating movement of the movable body 2 and outputs it to the carriage motor 31 included in the movable unit 3. Furthermore, the control unit 100 generates a control signal Ctrl2 for controlling the conveyance of the medium P and outputs it to the conveyance motor 41 included in the conveyance unit 4. Thus, the reciprocating movement of the movable body 2 in the main scanning direction and the conveyance of the medium P in the conveyance direction are controlled by the control unit 100. As a result, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the conveyance of the medium P. This allows the ink to land at the desired location on the medium P, thereby forming the desired image and text on the medium P.

[0037] In addition, the control unit 100 can also supply the control signal Ctrl1 for controlling the reciprocating movement of the movable body 2 to the moving unit 3 via the carriage motor driver not shown. Similarly, it can also supply the control signal Ctrl2 for controlling the conveyance of the medium P to the conveying unit 4 via the conveying motor driver not shown.

[0038] In addition, the control unit 100 outputs a basic drive signal dA to the drive circuit 50. The basic drive signal dA output by the control unit 100 is a signal containing data that specifies the waveform of the drive signal COM supplied to the head unit 20, and is, for example, a digital signal. After converting the input digital basic drive signal dA into an analog signal, the drive circuit 50 amplifies the converted signal to generate the drive signal COM. The drive circuit 50 then supplies the generated drive signal COM to the head unit 20. The structure and operation of the drive circuit 50 will be described in detail later.

[0039] Furthermore, the control unit 100 generates a clock signal SCK, a latch signal LAT, and a print data signal SI for controlling the operation of the head unit 20 , and outputs the signals to the head unit 20 .

[0040] The head unit 20 includes a drive signal selection circuit 200 and a liquid ejection head 21. Furthermore, the liquid ejection head 21 includes a plurality of ejection units 600, each of which includes a piezoelectric element 60. In the following description, the liquid ejection head 21 may be described as having n ejection units 600.

[0041] The drive signal selection circuit 200 receives inputs of a clock signal SCK, a latch signal LAT, and a print data signal SI. Based on the print data signal SI transmitted via the clock signal SCK, the drive signal selection circuit 200 switches whether to supply the drive signal COM as the drive signal VOUT to one end of the piezoelectric element 60 included in each of the plurality of ejection units 600 during a period specified by the latch signal LAT.

[0042] Furthermore, a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60 included in each of the plurality of ejection units 600. The reference voltage signal VBS functions as a reference potential for driving the piezoelectric element 60 driven by the drive signal VOUT, and is a signal having a fixed potential such as 5.5 V, 6 V, or ground potential.

[0043] The piezoelectric element 60 is driven by a potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end.

[0044] In addition, although Figure 2The figure shows a case where the head unit 20 has one liquid ejecting head 21, but the number of liquid ejecting heads 21 of the head unit 20 is not limited to one. The head unit 20 may have multiple liquid ejecting heads 21 depending on the type and amount of ink ejected.

[0045] As described above, the liquid ejection device 1 in this embodiment includes a liquid ejection head 21 and a driving circuit 50, wherein the liquid ejection head 21 has a plurality of piezoelectric elements 60 driven by being supplied with driving signals COM and VOUT, and ink as an example of a liquid is ejected by driving the plurality of piezoelectric elements 60, and the driving circuit 50 outputs the driving signal COM.

[0046] 1.2 Structure and operation of the ejection part

[0047] Next, an example of the structure of the plurality of ejection parts 600 included in the head unit 20 and the arrangement of the plurality of ejection parts 600 in the head unit 20 will be described. Figure 3 1 is an example of the arrangement of the plurality of ejection parts 600 in the head unit 20. Figure 3 In the embodiment, the case where the head unit 20 includes four liquid ejecting heads 21 is exemplified.

[0048] like Figure 3 As shown, the four liquid ejection heads 21 each have a plurality of ejection sections 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which the nozzles 651 described later included in the ejection section 600 are arranged in one direction. In addition, the liquid ejection heads 21 are arranged in a direction intersecting the nozzle row L in the head unit 20. That is, the same number of nozzle rows L as the number of liquid ejection heads 21 are formed in the head unit 20. In addition, the arrangement of the nozzles 651 in the nozzle row L of the liquid ejection head 21 is not limited to one row. For example, the nozzles 651 may be arranged in a staggered manner in such a manner that the positions of the even-numbered nozzles 651 and the odd-numbered nozzles 651 are different from those of the odd-numbered nozzles 651. Alternatively, one nozzle row L may be formed by arranging the plurality of nozzles 651 in two or more rows in parallel in the liquid ejection head 21.

[0049] Next, an example of the structure of the ejection portion 600 will be described. Figure 4 FIG. 6 is a diagram showing an example of the structure of the ejection portion 600. Figure 4 As shown, the ejection unit 600 includes a piezoelectric element 60, a vibration plate 621, a chamber 631, and a nozzle 651. The vibration plate 621 is accompanied by Figure 4The vibrating plate 621 is displaced by the driving of the piezoelectric element 60 provided on the upper surface. The vibrating plate 621 functions as a diaphragm that expands / contracts the internal volume of the cavity 631. The interior of the cavity 631 is filled with ink. Furthermore, the cavity 631 functions as a pressure chamber whose internal volume changes due to the displacement of the vibrating plate 621 caused by the driving of the piezoelectric element 60. The nozzle 651 is an opening portion formed on the nozzle plate 632 and connected to the cavity 631. Furthermore, as the internal volume of the cavity 631 changes, the ink stored in the interior of the cavity 631 is ejected from the nozzle 651.

[0050] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is clamped by a pair of electrodes 611 and 612. The piezoelectric body 601 of this structure has the electrodes 611 and 612 and the center portion of the vibration plate 621 being oriented relative to the end portions according to the potential difference between the electrodes 611 and 612. Figure 4 Deflection in the up and down directions.

[0051] Specifically, a drive signal VOUT is supplied to electrode 611 at one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to electrode 612 at the other end. When the piezoelectric element 60 is driven upward in response to changes in the voltage value of the drive signal VOUT, the vibrating plate 621 displaces upward, resulting in an expansion of the internal volume of the cavity 631. Consequently, ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to changes in the voltage value of the drive signal VOUT, the vibrating plate 621 displaces downward, resulting in a reduction in the internal volume of the cavity 631. Consequently, an amount of ink corresponding to the reduction in the internal volume of the cavity 631 is ejected from the nozzle 651.

[0052] As described above, the liquid ejection head 21 includes the piezoelectric element 60 and ejects ink onto the medium P by driving the piezoelectric element 60. The piezoelectric element 60 and the ejection unit 600 are not limited to the structures shown in the figure, and any structure can be used as long as the piezoelectric element 60 is displaced to eject ink from the nozzle 651.

[0053] 1.3 Select the structure and operation of the control circuit

[0054] Next, the structure and operation of the drive signal selection circuit 200 will be described. As previously described, the drive signal selection circuit 200 switches whether to supply a drive signal VOUT based on the drive signal COM to the piezoelectric element 60 included in each of the multiple ejection units 600 based on the clock signal SCK, the latch signal LAT, and the print data signal SI. Therefore, when describing the structure and operation of the drive signal selection circuit 200, an example of the signal waveform of the drive signal COM supplied to the drive signal selection circuit 200 will be described first.

[0055] Figure 5 FIG. 1 is a diagram showing an example of a signal waveform of the driving signal COM. Figure 5 As shown, the drive signal COM includes a trapezoidal waveform Adp in each period T from the rise of the latch signal LAT to the rise of the next latch signal LAT. The trapezoidal waveform Adp includes a period in which the voltage vc is constant; a period in which the voltage vc is constant followed by a period in which the voltage vb is constant, which is smaller than the voltage vc; a period in which the voltage vb is constant followed by a period in which the voltage vt is constant, which is larger than the voltage vc; and a period in which the voltage vt is constant followed by a period in which the voltage vc is constant. In other words, the drive signal COM includes a trapezoidal waveform Adp that starts and ends at the voltage vc. In the following description, the potential difference between the voltage vt and the voltage vb in the drive signal COM may be referred to as the amplitude of the drive signal COM.

[0056] The voltage vc corresponds to a potential that serves as a reference for the displacement of the piezoelectric element 60. Furthermore, by changing the voltage value of the driving signal COM supplied to the piezoelectric element 60 from the voltage vc to the voltage vb, the piezoelectric element 60 is displaced. Figure 4 As a result, the vibration plate 621 will move in the upward direction. Figure 4 Then, the vibration plate 621 is moved upward. Figure 4 The inner volume of the cavity 631 is expanded by the upward displacement shown in FIG. 6 , so that the ink is introduced from the reservoir 641 into the cavity 631. Then, the voltage value of the driving signal COM supplied to the piezoelectric element 60 changes from the voltage vb to the voltage vt, so that the piezoelectric element 60 moves in the opposite direction. Figure 4 As a result, the vibration plate 621 moves in the downward direction. Figure 4 Then, the vibration plate 621 is moved to the lower direction. Figure 4 The inner volume of the cavity 631 is reduced by displacement in the downward direction shown, so that the ink stored in the cavity 631 is ejected from the nozzle 651 .

[0057] Furthermore, the ink near the nozzle 651 or the vibration plate 621 may continue to vibrate for a fixed period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The period during which the voltage vc included in the driving signal COM is constant also functions as a period for stabilizing vibrations that do not contribute to the ejection of the ink or the vibration plate 621.

[0058] Here, Figure 5 The signal waveform of the driving signal COM shown is an example and is not limited to this. It can also include signal waveforms of various shapes corresponding to the physical properties of the ink ejected by the liquid ejection head 21, the length of the period T of the driving signal COM, the conveying speed of the medium P, etc.

[0059] Next, the configuration and operation of the drive signal selection circuit 200 for generating the drive signal VOUT by selecting or not selecting a signal waveform included in the drive signal COM will be described. Figure 6 FIG. 2 is a diagram showing an example of the structure of the drive signal selection circuit 200. Figure 6 As shown, the drive signal selection circuit 200 includes a selection control circuit 210 and n selection circuits 230 .

[0060] The clock signal SCK, the print data signal SI, and the latch signal LAT are input to the selection control circuit 210. Furthermore, the selection control circuit 210 includes a set of shift registers (S / R) 212, latch circuits 214, and decoders 216, corresponding to each of the n ejection units. In other words, the drive signal selection circuit 200 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0061] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. This print data signal SI serially includes print data [SId] corresponding to each of the n ejection units 600. This print data [SId] selects between "discharge FD," in which the ejection unit 600 ejects ink to form dots on the medium P, and "non-discharge ND," in which the ejection unit 600 does not eject ink to form dots on the medium P. In other words, the print data signal SI is a serial signal of n bits or more.

[0062] The printing data [SId] contained in the printing data signal SI is held by the n shift registers 212 corresponding to the n ejection units 600. Specifically, the n shift registers 212 corresponding to the ejection units 600 are cascade-connected to each other, and the serially input printing data signal SI is forwarded to the subsequent shift register 212 in sequence according to the clock signal SCK. Furthermore, by keeping the printing data [SId] in the corresponding shift register 212, the supply of the clock signal SCK is stopped. In other words, by stopping the supply of the clock signal SCK, the printing data [SId] contained in the printing data signal SI is kept in the corresponding shift register 212. In addition, in Figure 6 In order to distinguish the n shift registers 212 , they are sequentially labeled as 1st stage, 2nd stage, . . . nth stage from the upstream side where the print data signal SI is input toward the downstream side.

[0063] Each of the n latch circuits 214 simultaneously latches the print data [SId] held in the corresponding shift register 212 at the rising edge of the latch signal LAT. The print data [SId] latched by the latch circuit 214 is input to the corresponding decoder 216 .

[0064] Figure 7 This diagram shows an example of decoding content in decoder 216. Decoder 216 outputs a selection signal S of a logic level corresponding to the input print data [SId]. Specifically, when print data [SId] = [1] is input to decoder 216, decoder 216 outputs selection signal S at an H level for a period T. When print data [SId] = [0] is input to decoder 216, decoder 216 outputs selection signal S at an L level for a period T.

[0065] The selection signal S output by the decoder 216 is input to the selection circuit 230. The selection circuit 230 is provided so as to correspond to each of the n ejection units 600. That is, the drive signal selection circuit 200 has n selection circuits 230, which is the same number as the n ejection units 600. Figure 8 1 is an example of the structure of the selection circuit 230 corresponding to the amount of one ejection unit 600. Figure 8 As shown, the selection circuit 230 includes an inverter 232 and a transmission gate 234 as a NOT circuit.

[0066] The selection signal S is input to the positive control terminal (not marked with a circle) of transmission gate 234 and, after its logic level is inverted by inverter 232, is also input to the negative control terminal (marked with a circle) of transmission gate 234. Furthermore, the drive signal COM is supplied to the input terminal of transmission gate 234. When the selection signal S is input at an H level, transmission gate 234 establishes a conductive state between the input terminal and the output terminal, and when the selection signal S is input at an L level, the input terminal and the output terminal are non-conductive. Specifically, when the logic level of the input selection signal S is H, transmission gate 234 outputs a trapezoidal waveform Adp from its output terminal, and when the logic level of the input selection signal S is L, it does not output the trapezoidal waveform Adp from its output terminal. The signal input to the output terminal of transmission gate 234 of selection circuit 230 is output from drive signal selection circuit 200 as drive signal VOUT.

[0067] Here, use Figure 9 Next, the operation of the drive signal selection circuit 200 will be described. Figure 9 This diagram illustrates the operation of the drive signal selection circuit 200. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK. Furthermore, the print data signal SI is sequentially forwarded through the n shift registers 212 corresponding to the n ejection units 600 in synchronization with the clock signal SCK. When the input of the clock signal SCK stops, the shift register 212 retains the print data [SId] corresponding to each of the n ejection units 600. Furthermore, the print data signal SI includes the print data [SId] in the order corresponding to the ejection units 600: nth stage, ..., 2nd stage, and 1st stage of the shift register 212.

[0068] When the latch signal LAT rises, each latch circuit 214 simultaneously latches the print data [SId] held in the shift register 212. The print data [SId] latched by the latch circuit 214 is input to the corresponding decoder 216. Figure 9 LT1 , LT2 , . . . , LTn shown correspond to the print data [SId] latched by the latch circuit 214 in a manner corresponding to the 1st, 2nd, . . . , nth stage of the shift register 212 .

[0069] The decoder 216 decodes the input print data [SId] to generate Figure 7, and outputs the selection signal S of the logic level shown in FIG. 2 to the corresponding selection circuit 230. The selection circuit 230 then selects or deselects the trapezoidal waveform Adp included in the drive signal COM based on the logic level of the selection signal S output by the decoder 216, thereby generating a drive signal VOUT corresponding to each of the n ejection units 600 and outputting it to the corresponding ejection unit 600.

[0070] Specifically, when print data [SId] = [1] is input to decoder 216, decoder 216 outputs a selection signal S at an H level for a period T. Consequently, selection circuit 230 selects and outputs trapezoidal waveform Adp for a period T. Specifically, drive signal selection circuit 200 supplies drive signal VOUT corresponding to "discharge FD" to the piezoelectric element 60 of the corresponding discharge unit 600. As a result, an amount of ink corresponding to drive signal VOUT is discharged from the corresponding discharge unit 600. The ink discharged from the discharge unit 600 lands on medium P, forming dots on medium P.

[0071] On the other hand, when print data [SId] = [0] is input to decoder 216, decoder 216 outputs an L-level selection signal S within period T. Consequently, selection circuit 230 selects trapezoidal waveform Adp within period T. At this point, voltage vc is held at electrode 611 of the piezoelectric element 60 corresponding to selection circuit 230 due to the capacitance component of the piezoelectric element 60. Specifically, drive signal selection circuit 200 supplies the voltage vc, currently held by the capacitance component of the corresponding piezoelectric element 60, to piezoelectric element 60 as drive signal VOUT corresponding to "non-discharge ND." As a result, ink is not discharged from the corresponding discharge unit 600, and no dot is formed on medium P.

[0072] As described above, the drive signal selection circuit 200 switches the supply of the drive signal COM to the plurality of piezoelectric elements 60 based on the print data signal SI. In other words, the liquid ejection device 1 includes the drive signal selection circuit 200 that switches the supply of the drive signal VOUT based on the drive signal COM to the plurality of piezoelectric elements 60 based on the print data signal SI.

[0073] 1.4 Structure and operation of the driving circuit

[0074] Next, the configuration and operation of the drive circuit 50 that outputs the drive signal COM will be described. Figure 10 1 is a diagram showing an example of the configuration of the drive circuit 50 .

[0075] like Figure 10As shown, the driving circuit 50 includes an integrated circuit 500 , an amplifying circuit 550 , a demodulating circuit 560 , a first feedback circuit 570 , and a second feedback circuit 572 .

[0076] The integrated circuit 500 includes a plurality of terminals, including a terminal Id, a terminal Is, a terminal Ifb1, a terminal Ifb2, a terminal Bst, a terminal Hdr, a terminal Sw, a terminal Gvd, a terminal Ldr, and a terminal Gnd. Furthermore, the integrated circuit 500 includes a basic drive signal correction circuit 510, a modulation circuit 520, and a gate driver circuit 530. Furthermore, some or all of the basic drive signal correction circuit 510, the modulation circuit 520, and the gate driver circuit 530 included in the integrated circuit 500 may be provided external to the integrated circuit 500, and structures other than the basic drive signal correction circuit 510, the modulation circuit 520, and the gate driver circuit 530 may also be included in the integrated circuit 500.

[0077] The basic drive signal correction circuit 510 includes a DAC (Digital to Analog Converter) 511, a drive element count circuit 512, a correction value calculation circuit 513, and adders 514, 515, and 516. The basic drive signal correction circuit 510 outputs a corrected basic drive signal oA obtained by correcting the basic drive signal dA according to the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM.

[0078] A basic drive signal dA, which is a digital signal defining the waveform of the drive signal COM, is input to the DAC 511. The DAC 511 converts the input basic drive signal dA into an analog signal, namely, a basic drive signal aA, and outputs the converted signal.

[0079] The printing data signal SI is input to the driving element count circuit 512. Based on the input printing data signal SI, the driving element count circuit 512 counts the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM during the period T. The driving element count circuit 512 then generates and outputs a driving element count signal PZC indicating the calculation result.

[0080] The correction value calculation circuit 513 receives the driving element count signal PZC as input. Based on the input driving element count signal PZC, the correction value calculation circuit 513 calculates a correction value for the base driving signal aA based on the base driving signal dA. The correction value calculation circuit 513 then outputs a correction signal ADJ containing the calculated correction value.

[0081] The basic drive signal aA output by the DAC 511 is input to one of the positive input terminals of the adder 514. The correction signal ADJ output by the correction value calculation circuit 513 is input to the other of the positive input terminals of the adder 514. Specifically, the adder 514 adds the correction signal ADJ output by the correction value calculation circuit 513 to the basic drive signal aA output by the DAC 511. The adder 514 then outputs a DAC correction signal VDAC containing the addition result.

[0082] The DAC correction signal VDAC output by adder 514 is input to the positive input terminal of adder 515. Furthermore, the negative input terminal of adder 515 receives a first feedback signal VFB1, which is the result of attenuating the drive signal COM fed back via terminal Ifb1 through an integral attenuator 541. Specifically, adder 514 outputs a signal obtained by subtracting the first feedback signal VFB1 input to the negative input terminal from the DAC correction signal VDAC input to the positive input terminal. Here, the maximum voltage amplitude of the base drive signal aA, which serves as the basis for the DAC correction signal VDAC, may be approximately 2V, while the maximum voltage value of the drive signal COM is 25V or greater and exceeds 40V. The integral attenuator 541 attenuates the voltage of the drive signal COM input via terminal Ifb1 to ensure that the amplitude ranges of the two voltages match when calculating the deviation.

[0083] The output signal of adder 515 is input to the positive input terminal of adder 516. The negative input terminal of adder 516 receives a second feedback signal VFB2, which is a signal obtained by attenuating the high-frequency components of drive signal COM input via terminal Ifb2 using attenuator 542. In other words, adder 516 outputs a signal obtained by subtracting the second feedback signal VFB2 input to its negative input terminal from the output signal of adder 515 input to its positive input terminal. The output signal of adder 516 is output from base drive signal correction circuit 510 as the corrected base drive signal oA. In other words, base drive signal correction circuit 510 outputs the corrected base drive signal oA by correcting base drive signals dA and aA, which serve as the basis for drive signal COM.

[0084] The corrected base drive signal oA output by the base drive signal correction circuit 510 is input to the modulation circuit 520. The modulation circuit 520 includes, for example, a comparator. Furthermore, the modulation circuit 520 outputs a modulation signal MS obtained by pulse-modulating the corrected base drive signal oA. Specifically, the modulation circuit 520 compares the voltage value of the corrected base drive signal oA with a voltage vref, which is a predetermined reference voltage. Furthermore, the modulation circuit 520 generates and outputs the modulation signal MS. The modulation signal MS is at an H level when the voltage value of the corrected base drive signal oA is greater than the voltage vref, and is at an L level when the voltage value of the corrected base drive signal oA is less than the voltage vref.

[0085] The modulation signal MS output by the modulation circuit 520 is supplied to the gate driver 531 included in the gate driver circuit 530. Furthermore, the modulation signal MS output by the modulation circuit 520 is also supplied to the gate driver 532 included in the gate driver circuit 530 after its logic level is inverted by the inverter 521. That is, signals having mutually exclusive logic levels are input to the gate driver 531 and the gate driver 532.

[0086] Here, the signals input to the gate driver 531 and the gate driver 532, whose logic levels are mutually exclusive, only need to have the logic level of the signal supplied to the gate driver 531 and the logic level of the signal supplied to the gate driver 532 not be at the H level at the same time. Therefore, for example, the timing at which the logic level of the signal supplied to the gate driver 531 and the timing at which the logic level of the signal supplied to the gate driver 532 are at the H level can also be controlled by a timing circuit (not shown).

[0087] The gate driver circuit 530 includes a gate driver 531 and a gate driver 532 .

[0088] The gate driver 531 outputs an amplified control signal HGD from terminal Hdr, which is obtained by level-converting the modulation signal MS output by the modulation circuit 520. Of the power supply voltage supplied to the gate driver 531, the high side is supplied via terminal Bst, and the low side is supplied via terminal Sw. Terminal Bst is connected to one end of capacitor C5 and the cathode of diode D1, which prevents backflow. Terminal Sw is connected to the other end of capacitor C5. In addition, the anode of diode D1 is supplied with voltage vm via terminal Gvd, which is supplied from a power supply circuit (not shown). Therefore, the potential difference between terminal Bst and terminal Sw is the potential difference across capacitor C5 and is approximately equal to voltage vm. In other words, the gate driver 531 generates an amplified control signal HGD based on the input modulation signal MS, which is increased by the voltage vm compared to the voltage value of terminal Sw, and outputs it from terminal Hdr.

[0089] The gate driver 532 operates at a lower potential than the gate driver 531. The gate driver 532 outputs an amplified control signal LGD from terminal Ldr. This amplified control signal LGD is a signal obtained by inverting the logic level of the modulation signal MS output by the modulation circuit 520 through the inverter 521 and performing a level shift. The gate driver 532 receives a voltage vm on the upper side of its power supply voltage, and a ground potential (e.g., 0V) is supplied on the lower side via terminal Gnd. Thus, the gate driver 532 generates an amplified control signal LGD based on a signal obtained by inverting the logic level of the input modulation signal MS, which is increased by the voltage vm compared to the voltage at terminal Gnd, and outputs it from terminal Ldr.

[0090] The amplifier circuit 550 includes a transistor M1 and a transistor M2 .

[0091] A voltage signal VHV is supplied to the drain of transistor M1. The gate of transistor M1 is electrically connected to one end of resistor R1, and the other end of resistor R1 is electrically connected to terminal Hdr of integrated circuit 500. In other words, an amplification control signal HGD is supplied to the gate of transistor M1. Furthermore, the source of transistor M1 is electrically connected to terminal Sw of integrated circuit 500.

[0092] The drain of transistor M2 is electrically connected to terminal Sw of integrated circuit 500. That is, the drain of transistor M2 and the source of transistor M1 are electrically connected to each other. The gate of transistor M2 is electrically connected to one end of resistor R2, and the other end of resistor R2 is electrically connected to terminal Ldr of integrated circuit 500. That is, the gate of transistor M2 is supplied with amplification control signal LGD. In addition, the source of transistor M2 is supplied with ground potential.

[0093] In amplifier circuit 550 configured as described above, when the drain and source of transistor M1 are controlled to a non-conducting state and the drain and source of transistor M2 are controlled to a conducting state, the voltage value of the node electrically connected to terminal Sw becomes the ground potential. Therefore, voltage vm is supplied to terminal Bst. On the other hand, when the drain and source of transistor M1 are controlled to a conducting state and the drain and source of transistor M2 are controlled to a non-conducting state, the voltage value of the node electrically connected to terminal Sw becomes the voltage value of voltage signal VHV, i.e., voltage vhv. Therefore, a signal having a voltage value of voltage vhv + voltage vm is supplied to terminal Bst. That is, the gate driver 531 that drives the transistor M1 uses the capacitor C5 as a floating power supply and changes the voltage value of the terminal Sw to the ground potential or the voltage vhv according to the operation of the transistor M1 and the transistor M2, thereby generating an amplified control signal HGD whose L level changes from the ground potential to the voltage vhv and whose H level changes from the voltage vhv to the voltage vhv+voltage vm, and supplies it to the gate of the transistor M1.

[0094] Meanwhile, the gate driver 532 driving the transistor M2 generates an amplification control signal LGD whose L level is the ground potential and whose H level is the voltage vm, regardless of the operations of the transistors M1 and M2, and supplies it to the gate of the transistor M2.

[0095] The amplifier circuit 550 described above amplifies the modulation signal MS, which is obtained by modulating the corrected base drive signal oA using transistors M1 and M2, based on the voltage signal VHV. Consequently, at the connection point where the source of transistor M1 and the drain of transistor M2 are connected in a common manner, an amplified modulation signal AMS is generated. This amplification is achieved by amplifying the modulation signal MS based on the voltage signal VHV. In other words, the amplifier circuit 550 outputs the amplified modulation signal AMS obtained by amplifying the modulation signal MS.

[0096] The amplified modulation signal AMS outputted from the amplifier circuit 550 is inputted to the demodulation circuit 560 . The demodulation circuit 560 demodulates the amplified modulation signal AMS outputted from the amplifier circuit 550 to generate the driving signal COM, and outputs the driving signal COM from the driving circuit 50 .

[0097] The demodulation circuit 560 includes an inductor L1 and a capacitor C1. One end of the inductor L1 is connected to one end of the capacitor C1. Furthermore, the amplified modulation signal AMS is input to the other end of the inductor L1. Furthermore, the other end of the capacitor C1 is supplied with a ground potential. In other words, the inductor L1 and capacitor C1 included in the demodulation circuit 560 form a low-pass filter. Through this low-pass filter, the demodulation circuit 560 smoothes the amplified modulation signal AMS and thereby performs demodulation. The demodulation circuit 560 then outputs the demodulated signal as the drive signal COM. That is, the demodulation circuit 560 includes the capacitor C1 and demodulates the amplified modulation signal AMS to output the drive signal COM.

[0098] The first feedback circuit 570 and the second feedback circuit 572 feed back the driving signal COM to the basic driving signal correction circuit 510 .

[0099] The first feedback circuit 570 includes resistors R3 and R4. A drive signal COM is supplied to one end of resistor R3. The other end of resistor R3 is connected to terminal Ifb1 and one end of resistor R4. A voltage signal VHV is supplied to the other end of resistor R4. Thus, the first feedback signal VFB1, which is obtained by pulling up the drive signal COM after passing through the first feedback circuit 570 and terminal Ifb1 and then being pulled up by the voltage signal VHV, is fed back to the basic drive signal correction circuit 510.

[0100] The second feedback circuit 572 includes capacitors C2, C3, and C4, and resistors R5 and R6. A drive signal COM is supplied to one end of capacitor C2. The other end of capacitor C2 is connected to one end of resistor R5 and one end of resistor R6. A ground potential is supplied to the other end of resistor R5. Thus, capacitor C2 and resistor R5 function as a high-pass filter. In other words, the second feedback circuit 572 includes a high-pass filter. This high-pass filter removes the low-frequency components of the drive signal COM input to the second feedback circuit 572. As a result, a triangular wave signal formed by the ripple component superimposed on the drive signal COM is extracted. Here, the triangular wave signal means a signal that is not strictly a triangular wave due to the frequency characteristics of the second feedback circuit 572. In addition, in the following description, the signal extracted by the second feedback circuit 572 is described as a triangular wave.

[0101] Furthermore, the other end of resistor R6 is connected to one end of capacitor C4 and one end of capacitor C3. The other end of capacitor C3 is supplied with a ground potential. Thus, in the second feedback circuit 572, resistor R6 and capacitor C3 function as a low-pass filter. In other words, the second feedback circuit 572 includes a low-pass filter. The cutoff frequency of this low-pass filter is set to be sufficiently higher than the cutoff frequency of the high-pass filter formed by capacitor C2 and resistor R5. Thus, the low-pass filter formed by resistor R6 and capacitor C3 removes high-frequency noise components that overlap with the output of the high-pass filter formed by capacitor C2 and resistor R5.

[0102] The second feedback circuit 572 configured as described above also functions as a bandpass filter that allows signals in the predetermined frequency domain included in the drive signal COM to pass through. Furthermore, the other end of capacitor C4 is connected to terminal Ifb2 of integrated circuit 500. Thus, through the second feedback circuit 572, a triangular wave signal is fed back to the basic drive signal correction circuit 510 as the second feedback signal VFB2. This triangular wave signal is obtained by extracting the high-frequency components included in the drive signal COM. Specifically, this triangular wave signal corresponds to the period of the ripple voltage superimposed on the drive signal COM based on the amplified modulation signal AMS.

[0103] Here, the drive signal COM output by the drive circuit 50 is a signal obtained by smoothing the amplified modulated signal AMS via the low-pass filter included in the demodulation circuit 560. The drive signal COM output by the drive circuit 50 is integrated and subtracted via the terminal Ifb1 before being fed back to the adder 515. This causes the drive circuit 50 to self-oscillate at a frequency determined by the delay of the first feedback circuit 570 and the feedback transfer function. However, the feedback path via the terminal Ifb1 has a significant delay, making it difficult to increase the self-oscillation frequency of the drive circuit 50 to a level sufficient to ensure the accuracy of the drive signal COM. Therefore, in the drive circuit 50 of this embodiment, a feedback path via the second feedback circuit 572 is provided in addition to the feedback path via the first feedback circuit 570 to feed back the high-frequency components of the drive signal COM, thereby reducing the delay of the entire circuit. This allows the frequency of the corrected base drive signal oA to be increased to a level sufficient to ensure the accuracy of the drive signal COM.

[0104] Here, when the voltage value of the drive signal COM output by the drive circuit 50 at any time is set to voltage vcom, the voltage vcom can be expressed by the following formula (1) using the on-duty AMon of the amplified modulation signal AMS and the voltage vhv which is the voltage value of the voltage signal VHV.

[0105] Mathematical formula 1

[0106] vcom=AMon×vhv…(1)

[0107] Furthermore, since the signal obtained by amplifying the modulation signal MS by the amplifier circuit 550 is the amplified modulation signal AMS, the on-duty AMon of the amplified modulation signal AMS and the on-duty Mon of the modulation signal MS are substantially equal. Therefore, the on-duty AMon in the above-mentioned equation (1) can be replaced with the on-duty Mon of the modulation signal MS. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 at any given time, that is, the voltage vcom, can also be expressed by the following equation (2).

[0108] Mathematical formula 2

[0109] vcom=Mon×vhv…(2)

[0110] That is, the drive circuit 50 outputs the drive signal COM having a voltage value obtained based on the on-duty Mon of the modulation signal MS obtained by modulating the corrected basic drive signal oA.

[0111] Next, the on-duty Mon of the modulation signal MS will be described. Figure 11 This diagram illustrates the relationship between the corrected basic drive signal oA and the modulation signal MS. As previously described, the corrected basic drive signal oA output by the basic drive signal correction circuit 510 is obtained by subtracting the first feedback signal VFB1 and the second feedback signal VFB2 from the DAC correction signal VDAC. Furthermore, the second feedback signal VFB2 input to the basic drive signal correction circuit 510 is a triangular wave signal derived from the period of the ripple voltage superimposed on the drive signal COM according to the frequency of the amplified modulation signal AMS.

[0112] Therefore, when the voltage value of the DAC correction signal VDAC is set to voltage vdac, the voltage value of the first feedback signal VFB1 is set to voltage vfb1, the voltage value of the predetermined bias voltage is set to voltage vo, and the voltage amplitude of the second feedback signal VFB2 of the triangular wave is set to amplitude A, the corrected basic drive signal oA becomes a triangular wave having a voltage v1 shown in the following equation (3) as a central value and a voltage value that varies within the range of the following equations (4) to (5) according to the period of the ripple voltage superimposed on the drive signal COM.

[0113] Mathematical formula 3

[0114] v1=(vdac-vfb1)+vo…(3)

[0115] Mathematical formula 4

[0116] v2=(vdac-vfb1)+vo+A / 2…(4)

[0117] Mathematical formula 5

[0118] v3=(vdac-vfb1)+vo-A / 2…(5)

[0119] Here, the voltage vo shown in the above-mentioned equations (3) to (5) is equivalent to a predetermined bias voltage value and is an arbitrary voltage value used to correct errors or deviations generated in the driving circuit 50, such as the voltage value of the DC voltage component remaining in the triangular wave serving as the second feedback signal VFB2 or the voltage value of the bias voltage of the comparator constituting the modulation circuit 520.

[0120] Moreover, the modulation circuit 520 compares the voltage value of the corrected basic drive signal oA output from the basic drive signal correction circuit 510 with the voltage vref serving as the voltage value of the reference voltage, and generates and outputs a modulation signal MS, wherein the modulation signal MS becomes an H level when the voltage value of the corrected basic drive signal oA is greater than the voltage vref, and becomes an L level when the voltage value of the corrected basic drive signal oA is less than the voltage vref.

[0121] At this time, the on-duty Mon of the modulation signal MS output by the modulation circuit 520 can be adjusted according to Figure 11 It is expressed as the following formula (6).

[0122] Mathematical formula 6

[0123]

[0124] Furthermore, by substituting equation (3) into the above equation (6), the on-duty Mon of the modulation signal MS output by the modulation circuit 520 can be expressed by the following equation (7).

[0125] Mathematical formula 7

[0126]

[0127] Furthermore, voltage vfb1, which is the voltage value of the first feedback signal VFB1, is a voltage value obtained by attenuating voltage vcom, which is the voltage of the drive signal COM, by the first feedback circuit 570 and the integral attenuator 541. Therefore, when the attenuation rate achieved by the first feedback circuit 570 and the integral attenuator 541 is set to α, voltage vfb1, which is the voltage value of the first feedback signal VFB1, can be expressed by the following equation (8).

[0128] Mathematical formula 8

[0129] vfb1=α×vcom…(8)

[0130] Furthermore, by substituting equations (7) and (8) into the above equation (2) and rearranging them, the voltage value of the drive signal COM output by the drive circuit 50 at any timing, that is, the voltage vcom, can be expressed by the following equation (9).

[0131] Mathematical formula 9

[0132]

[0133] According to equation (9), the voltage value of the drive signal COM output by the drive circuit 50, namely, the voltage vcom, depends on the amplitude A, which is the voltage amplitude of the second feedback signal VFB2. Specifically, the amplitude of the drive signal COM is proportional to the voltage vdac and inversely proportional to the denominator of equation (9). Therefore, the amplitude of the drive signal COM depends on the amplitude A, which is the voltage amplitude of the second feedback signal VFB2.

[0134] Here, the second feedback signal VFB2 is a signal that depends on the ripple voltage superimposed on the drive signal COM, as described above. The amplitude A of the second feedback signal VFB2 depends on the voltage amplitude of the ripple voltage superimposed on the drive signal COM. Furthermore, the voltage amplitude of the ripple voltage superimposed on the drive signal COM depends on the load capacitance generated in the transmission path through which the drive signal COM propagates. Specifically, if the load capacitance generated in the transmission path through which the drive signal COM propagates changes, the amplitude A of the second feedback signal VFB2 changes, and the value of voltage vcom, which is the voltage value of the drive signal COM, also fluctuates. As a result, the amplitude of the voltage value of the drive signal COM changes according to the load capacitance.

[0135] In particular, in a liquid ejection device 1 such as the liquid ejection device 1 of the present embodiment, which forms an image on a medium P by including a plurality of piezoelectric elements 60 serving as capacitive loads and switching whether or not to supply a drive signal VOUT based on a drive signal COM to each of the plurality of piezoelectric elements 60, the number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM can vary significantly. As a result, the load capacity generated along the propagation path through which the drive signal COM propagates can vary significantly. Specifically, in a drive circuit 50 that supplies the drive signal COM to a plurality of piezoelectric elements 60, the amplitude of the voltage value of the drive signal COM can vary depending on the number of piezoelectric elements 60 supplied with the drive signal VOUT based on the drive signal COM.

[0136] For example, as the number of piezoelectric elements 60 supplied with the drive signal VOUT increases, the amplitude A of the second feedback signal VFB decreases. Consequently, the amplitude of the drive signal COM increases. On the other hand, as the number of piezoelectric elements 60 supplied with the drive signal VOUT decreases, the amplitude A of the second feedback signal VFB increases. Consequently, the amplitude of the drive signal COM decreases. In other words, the amplitude of the drive signal COM may change as the number of piezoelectric elements 60 supplied with the drive signal VOUT changes.

[0137] To address this issue, in the liquid ejection device 1 of the present embodiment, a driving element count circuit 512 included in a base driving signal correction circuit 510 of the driving circuit 50 counts the number of piezoelectric elements 60 driven by a driving signal VOUT based on the driving signal COM, based on the print data signal SI. Based on the calculation result of the driving element count circuit 512, a correction value calculation circuit 513 calculates a correction value corresponding to the number of piezoelectric elements 60 driven by the driving signal VOUT based on the driving signal COM. Then, based on the correction signal ADJ including the correction value calculated by the correction value calculation circuit 513, the base driving signal aA based on the base driving signal dA is corrected. Consequently, in a driving circuit 50 that supplies the driving signal COM to a plurality of piezoelectric elements 60, the possibility of a change in the amplitude of the voltage value of the driving signal COM is reduced, even if the number of piezoelectric elements 60 supplied with the driving signal VOUT based on the driving signal COM fluctuates.

[0138] Here, a specific example of the DAC correction signal VDAC obtained by correcting the basic drive signal aA according to the correction signal ADJ will be described. Figure 12 1 is a diagram showing an example of the DAC correction signal VDAC when the number of piezoelectric elements 60 driven by the drive signal VOUT is large. Figure 12 In FIG. 5 , the uncorrected basic drive signal aA is shown by the dotted line (a), and the DAC correction signal VDAC obtained by correcting the basic drive signal aA according to the correction signal ADJ including the correction value calculated by the correction value calculation circuit 513 is shown by the solid line (b). Figure 12 As shown, when a large number of piezoelectric elements 60 are driven by the drive signal VOUT based on the drive signal COM in response to the print data signal SI, the DAC correction signal VDAC is corrected to reduce the amplitude of the basic drive signal aA based on the basic drive signal dA based on the correction signal ADJ including the correction value calculated by the correction value calculation circuit 513. This reduces the possibility of fluctuations in the amplitude of the voltage value of the drive signal COM.

[0139] Figure 13 : is a diagram showing an example of the DAC correction signal VDAC when the number of piezoelectric elements 60 driven by the drive signal VOUT is small. Figure 13 In FIG. 5 , the uncorrected basic drive signal aA is shown by the dotted line (c), and the DAC correction signal VDAC obtained by correcting the basic drive signal aA according to the correction signal ADJ including the correction value calculated by the correction value calculation circuit 513 is shown by the solid line (d). Figure 13 As shown, when the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM in response to the print data signal SI is small, the DAC correction signal VDAC is corrected to increase the amplitude of the basic drive signal aA based on the basic drive signal dA based on the correction signal ADJ including the correction value calculated by the correction value calculation circuit 513. This reduces the possibility of variations in the amplitude of the voltage value of the drive signal COM.

[0140] As described above, in the liquid ejection device 1 of this embodiment, the basic drive signal correction circuit 510 included in the drive circuit 50 outputs a corrected basic drive signal oA. This corrected basic drive signal oA is a signal obtained by correcting the basic drive signal dA according to the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM. This reduces the possibility that the amplitude of the voltage value of the drive signal COM output by the drive circuit 50 will vary with changes in the load capacity.

[0141] Next, an example of a method of calculating the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM, performed by the basic drive signal correction circuit 510 , will be described.

[0142] As described above, the drive signal selection circuit 200 controls whether or not the drive signal VOUT based on the drive signal COM is supplied to the plurality of piezoelectric elements 60 included in the liquid ejection head 21 .

[0143] Specifically, the drive signal selection circuit 200 supplies the drive signal VOUT generated based on the drive signal COM, corresponding to discharge FD, to the piezoelectric element 60 included in the ejection unit 600 corresponding to the input print data [SId] = [1]. Furthermore, the drive signal VOUT corresponding to the voltage value held in the piezoelectric element 60, corresponding to non-discharge ND, is supplied to the piezoelectric element 60 included in the ejection unit 600 corresponding to the input print data [SId] = [0]. In other words, the drive signal VOUT generated based on the drive signal COM is supplied to the piezoelectric element 60 included in the ejection unit 600 corresponding to the print data [SId] = [1].

[0144] Therefore, in the basic drive signal correction circuit 510, the driving element count circuit 512 counts the total number of print data [SId] = [1] included in the print data signal SI, thereby calculating the total number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM. Furthermore, the correction value calculation circuit 513 calculates a correction value based on the total number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM. In other words, the basic drive signal correction circuit 510 counts the number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM, based on the print data signal SI.

[0145] As a method for calculating the total number of print data [SId]=[1] included in the brush data signal SI by the drive element count circuit 512 of the basic drive signal correction circuit 510, a method of sequentially adding the print data [SId]=[1] included in the print data signal SI is conceivable. However, since the liquid ejection device 1 has hundreds to thousands of nozzles, this method of sequentially adding the print data [SId]=[1] included in the print data signal SI by the drive element count circuit 512 may increase the computation load and the time required for computational processing, thereby potentially reducing the speed at which ink is ejected onto the medium P.

[0146] Therefore, in this embodiment, the drive element count circuit 512 first calculates 2-bit addition data by adding adjacently transmitted print data [SId] among the n print data [SId] serially included in the print data signal SI. Then, it calculates 4-bit addition data by adding adjacent 2-bit addition data. The drive element count circuit 512 repeatedly performs the same calculation process to calculate n-bit addition data. This reduces the computational load incurred by the drive element count circuit 512 when calculating the total number of print data [SId] = [1] included in the print data signal SI, and also shortens the time required for the calculation process in the drive element count circuit 512.

[0147] A specific example of the calculation method in the driving element number counting circuit 512 as described above will be described. Figure 14 : is a diagram showing a specific example of a method for calculating the total number of piezoelectric elements 60 driven by the drive signal VOUT based on the drive signal COM. Figure 14 In order to simplify the description, the case where the 8-bit printing data signal SI is input to the driving element number counting circuit 512 is exemplified.

[0148] like Figure 14 As shown, when the 8-bit printing data signal SI = [1, 1, 0, 1, 1, 0, 0, 0] is input to the driving element counting circuit 512 as an example of the printing data signal SI, the driving element counting circuit 512 adds adjacent 1 bits in the input printing data signal SI = [1, 1, 0, 1, 1, 0, 0, 0]. Thus, the driving element counting circuit 512 calculates 2-bit addition data.

[0149] Specifically, the driving element number counting circuit 512 calculates the logical product of the printing data signal SI = [1, 1, 0, 1, 1, 0, 0, 0] and S1 = [0, 1, 0, 1, 0, 1, 0, 1], and calculates the logical product of the calculation result obtained by shifting the printing data signal SI = [1, 1, 0, 1, 1, 0, 0, 0] right by 1 bit and S1 = [0, 1, 0, 1, 0, 1, 0, 1]. The driving element counting circuit 512 then adds the result of the logical product of the print data signal SI = [1, 1, 0, 1, 1, 0, 0, 0] and S1 = [0, 1, 0, 1, 0, 1, 0, 1], and the result of the logical product of the print data signal SI = [1, 1, 0, 1, 1, 0, 0, 0] shifted right by one bit and S1 = [0, 1, 0, 1, 0, 1, 0, 1]. Thus, the driving element counting circuit 512 calculates the two-bit addition data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0], which is the sum of adjacent one-bit data in the print data signal SI = [1, 1, 0, 1, 1, 0, 0, 0].

[0150] Afterwards, the driving element number counting circuit 512 calculates the logical product of the 2-bit addition operation data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0] and S2 = [0, 0, 1, 1, 0, 0, 1, 1], and calculates the logical product of the calculation result obtained by shifting the 2-bit addition operation data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0] to the right by 2 bits and S2 = [0, 0, 1, 1, 0, 0, 1, 1]. The driving element count circuit 512 then adds the result of the logical product of the 2-bit addition data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0] and S2 = [0, 0, 1, 1, 0, 0, 1, 1], and the result of the logical product of the result of the 2-bit addition data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0] shifted right by 2 bits and S2 = [0, 0, 1, 1, 0, 0, 1, 1]. Thus, the driving element count circuit 512 calculates 4-bit addition data 4bit-S = [0, 0, 1, 1, 0, 0, 0, 1], which is obtained by adding the adjacent 2-bit data in the 2-bit addition data 2bit-S = [1, 0, 0, 1, 0, 1, 0, 0].

[0151] Afterwards, the driving element number counting circuit 512 calculates the logical product of the 4-bit addition operation data 4bit-S = [0, 0, 1, 1, 0, 0, 0, 1] and S4 = [0, 0, 0, 0, 1, 1, 1, 1], and calculates the logical product of the calculation result obtained by shifting the 4-bit addition operation data 4bit-S = [0, 0, 1, 1, 0, 0, 1] to the right by 4 bits and S4 = [0, 0, 0, 0, 1, 1, 1, 1]. The driving element count circuit 512 then adds the result of the logical product of the 4-bit addition data 4bit-S = [0, 0, 1, 1, 0, 0, 1] and S4 = [0, 0, 0, 0, 1, 1, 1, 1], and the result of the logical product of the result of the 4-bit addition data 4bit-S = [0, 0, 1, 1, 0, 0, 0, 1] shifted right by 4 bits and S4 = [0, 0, 0, 0, 1, 1, 1, 1]. Thus, the driving element count circuit 512 calculates 8-bit addition data 8bit-S = [0, 0, 0, 0, 0, 1, 0, 0], which is obtained by adding the adjacent 4-bit data in the 4bit addition data 4bit-S = [0, 0, 1, 1, 0, 0, 0, 1].

[0152] The 8-bit addition data 8bit-S = [0, 0, 0, 0, 0, 1, 0, 0] calculated by the driving element count circuit 512 corresponds to the total number of print data [SId] = [1] included in the 8-bit print data signal SI = [1, 1, 0, 1, 1, 0, 0, 0]. The driving element count circuit 512 generates a driving element count signal PZC including the calculated 8-bit addition data 8bit-S = [0, 0, 0, 0, 0, 1, 0, 0] and outputs it to the correction value calculation circuit 513.

[0153] As described above, the driving element count circuit 512 counts the number of piezoelectric elements 60 driven by the drive signal VOUT generated based on the drive signal COM, based on the print data signal SI. For example, even if the head unit 20 has 800 piezoelectric elements 60, that is, if the print data signal SI includes 800 bits of print data [SId], the total number of print data [SId] = [1] included in the print data signal SI can be calculated using 29 addition operations and 8 logical operations. This reduces the likelihood of an increase in the computational load on the driving element count circuit 512 and shortens the time required for computational processing in the driving element count circuit 512.

[0154] Here, the piezoelectric element 60 is an example of a capacitive load, and the drive circuit 50 that outputs the drive signal COM supplied to the plurality of piezoelectric elements 60 as a plurality of capacitive loads is an example of a capacitive load drive circuit. In addition, since the drive signal VOUT is generated based on the drive signal COM, both the drive signal COM and the drive signal VOUT output by the drive circuit 50 are examples of drive signals. Moreover, the piezoelectric element 60 among the plurality of piezoelectric elements 60 that is supplied with the drive signal VOUT generated based on the drive signal COM is an example of a drive capacitive load. In addition, the drive signal selection circuit 200 that switches the supply of the drive signal VOUT generated based on the drive signal COM to the plurality of piezoelectric elements 60 is an example of a switching circuit, and the printing data signal SI in the drive signal selection circuit 200 that controls the switching of the supply of the drive signal VOUT generated based on the drive signal COM to the plurality of piezoelectric elements 60 is an example of ejection data. Furthermore, the basic drive signal aA, which serves as the basis for the drive signal COM, is an example of a basic drive signal. Since the basic drive signal aA is a signal obtained by performing digital-to-analog conversion on the digital basic drive signal dA, the basic drive signal dA is also an example of a basic drive signal. Furthermore, the basic drive signal correction circuit 510, which corrects the basic drive signal aA to output the corrected basic drive signal oA, is an example of a correction circuit. Furthermore, the capacitor C1 included in the demodulation circuit 560 is an example of a capacitor, and the second feedback circuit 572 is an example of a feedback circuit.

[0155] 1.5 Effects

[0156] As described above, the drive circuit 50 included in the liquid ejection device 1 of this embodiment corrects the basic drive signal aA in the basic drive signal correction circuit 510 according to the number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM. This reduces the likelihood of changes in the voltage value of the signal waveform of the drive signal COM, even if the capacitance component of the propagation path of the drive signal COM changes due to changes in the number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM. In other words, the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved, resulting in further improved ink ejection accuracy in the liquid ejection device 1 equipped with the drive circuit 50.

[0157] 1.6 Variations

[0158] Although the above-described embodiment of the drive circuit 50 included in the liquid ejection device 1 is described as a method in which the base drive signal correction circuit 510 generates the corrected base drive signal oA by adding the analog base drive signal aA output by the DAC 511 and the correction signal ADJ based on the drive element count signal PZC calculated by the drive element count counting circuit 512, the base drive signal correction circuit 510 may also generate the base drive signal aA and the corrected base drive signal oA by adding the digital base drive signal dA and the correction value for the number of driven nozzles calculated by the drive element count counting circuit 512. Even in this case, the same operational effects can be achieved.

[0159] 2. Second Implementation

[0160] Next, the structure of the liquid ejection device 1 in the second embodiment will be described. The structure of the drive circuit 50 for outputting the drive signal COM in the liquid ejection device 1 in the second embodiment is different from that in the liquid ejection device 1 in the first embodiment. In addition, when describing the liquid ejection device 1 in the second embodiment, the same reference numerals are used for the same structures as those in the liquid ejection device 1 in the first embodiment, and the description thereof will be simplified or omitted.

[0161] Figure 15 FIG. 5 is a diagram showing the structure of the driving circuit 50 according to the second embodiment. Figure 15 As shown, the driving circuit 50 of the second embodiment includes a level shifting circuit 70 in addition to a basic driving signal correction circuit 510 , a modulation circuit 520 , a gate driver circuit 530 , an amplifier circuit 550 , and a demodulation circuit 560 .

[0162] Similar to the liquid ejection device 1 of the first embodiment, the basic drive signal correction circuit 510 receives inputs such as the basic drive signal dA, the print data signal SI, the first feedback signal VFB1, and the second feedback signal VFB2. The basic drive signal correction circuit 510 calculates the number of piezoelectric elements 60 supplied with the drive signal VOUT generated based on the drive signal COM based on the print data signal SI, and based on this calculation, corrects the basic drive signal dA or the basic drive signal aA corresponding to the basic drive signal dA. Furthermore, the basic drive signal correction circuit 510 adds or subtracts the first feedback signal VFB1 fed back from the first feedback circuit 570 and the second feedback signal VFB2 fed back from the second feedback circuit 572 to generate a corrected basic drive signal oA, which it outputs to the modulation circuit 520.

[0163] The modulation circuit 520 generates a modulation signal MS by modulating the corrected basic drive signal oA outputted from the basic drive signal correction circuit 510 , and outputs the modulation signal MS to the gate driver circuit 530 .

[0164] The gate driver circuit 530 generates an amplified control signal HGD obtained by level-converting the modulation signal MS and supplies it to the gate of the transistor M1 of the amplifier circuit 550. It also generates an amplified control signal LGD obtained by level-converting a signal obtained by inverting the logic level of the modulation signal MS through the inverter 521 and supplies it to the gate of the transistor M2 of the amplifier circuit 550.

[0165] The amplifier circuit 550 includes transistors M1 and M2. Transistors M1 and M2 operate based on amplification control signals HGD and LGD output by the gate driver circuit 530, thereby outputting an amplified modulation signal AMS obtained by amplifying the modulation signal MS. The amplifier circuit 550 of the second embodiment amplifies the modulation signal MS based on a voltage signal VHV1 having a smaller voltage value than the voltage signal VHV of the first embodiment, thereby outputting the amplified modulation signal AMS.

[0166] Level shifter circuit 70 includes a reference level switching circuit 710, a gate driver circuit 730, diodes D11 and D12, capacitors C11 and C12, transistors M3 and M4, and a bootstrap circuit BS. Level shifter circuit 70 generates and outputs a level-shifted amplified modulation signal LAMS, which is obtained by level-shifting the reference potential of amplified modulation signal AMS.

[0167] The basic drive signal dA is input to the reference level switching circuit 710. The reference level switching circuit 710 generates a level switching signal LS based on the input basic drive signal dA and outputs it to the gate driver circuit 730. Specifically, the reference level switching circuit 710 outputs an H-level level switching signal LS when the voltage value specified by the input basic drive signal dA is greater than a predetermined threshold value, and outputs an L-level level switching signal LS when the voltage value specified by the input basic drive signal dA is less than the predetermined threshold value.

[0168] The gate driver circuit 730 includes gate drivers 731 and 732. The level switching signal LS output by the reference level switching circuit 710 is input to the gate driver 731. Furthermore, the gate driver 731 generates and outputs a gate signal TRD1 obtained by level-converting the input signal. The gate driver 732 receives an input signal obtained by inverting the logic level of the level switching signal LS inverted by the inverter 721. Furthermore, the gate driver 732 generates and outputs a gate signal TRD2 obtained by level-converting the input signal.

[0169] Gate signal TRD1 is input to the gate of transistor M3. Voltage signal VHV3 output by bootstrap circuit BS is supplied to the drain of transistor M3. Gate signal TRD2 is input to the gate of transistor M4. Amplified modulation signal AMS is input to the source of transistor M4. Furthermore, the source of transistor M3 and the drain of transistor M4 are electrically connected. Level shifter circuit 70 outputs the signal generated at the connection point where the source of transistor M3 and the drain of transistor M4 are electrically connected as level-shifted amplified modulation signal LAMS.

[0170] Bootstrap circuit BS includes a diode D13 and a capacitor C13. A voltage signal VHV2 is supplied to the anode of diode D13, and the cathode of diode D13 is electrically connected to one end of capacitor C13. Furthermore, an amplified modulation signal AMS is supplied to the other end of capacitor C13. Here, voltage signal VHV2 has a smaller voltage value than voltage signal VHV1, and preferably has a voltage value close to that of voltage signal VHV1.

[0171] In the level shifter circuit 70 configured as described above, when the potential specified by the base drive signal dA input to the reference level switching circuit 710 is lower than a predetermined potential, the reference level switching circuit 710 generates an L-level level switching signal LS and outputs it to the gate driver circuit 730. Consequently, the gate driver circuit 730 outputs an L-level gate signal TRD1 and an H-level gate signal TRD2. Consequently, the drain and source of the transistor M3 are controlled to be non-conductive, while the drain and source of the transistor M4 are controlled to be conductive. As a result, the amplified modulation signal AMS supplied to the source of the transistor M4 is output from the level shifter circuit 70 as the level-shifted amplified modulation signal LAMS.

[0172] On the other hand, when the potential specified by the base drive signal dA input to the reference level switching circuit 710 is above a predetermined potential, the reference level switching circuit 710 generates an H-level level switching signal LS and outputs it to the gate driver circuit 730. Consequently, the gate driver circuit 730 outputs an H-level gate signal TRD1 and an L-level gate signal TRD2. Consequently, the drain and source of the transistor M3 are controlled to be conductive, while the drain and source of the transistor M4 are controlled to be non-conductive. As a result, the reference potential of the amplified modulation signal AMS supplied to the other end of the capacitor C13 is level-converted to a potential based on the voltage signal VHV2 supplied to the anode of the diode D13. The amplified modulation signal AMS, resulting from the level-conversion of the reference potential to a potential based on the voltage signal VHV2, is output from the level shift circuit 70 as the level-converted amplified modulation signal LAMS via the transistor M4.

[0173] The level-converted amplified modulated signal LAMS output from the level shift circuit 70 is input to the demodulation circuit 560. The demodulation circuit 560 smoothes and demodulates the level-converted amplified modulated signal LAMS output from the level shift circuit 70, and outputs the signal from the drive circuit 50 as the drive signal COM.

[0174] Furthermore, the drive signal COM output by the demodulation circuit 560 is input to the basic drive signal correction circuit 510 via the first feedback circuit 570 as the first feedback signal VFB1 , and is input to the basic drive signal correction circuit 510 via the second feedback circuit 572 as the second feedback signal VFB2 .

[0175] As described above, the drive circuit 50 of the second embodiment switches whether to output the reference potential of the amplified modulated signal AMS output by the amplifier circuit 550 as the ground potential or as the voltage signal VHV2, based on the voltage value specified by the base drive signal dA. In this drive circuit 50, the voltage value of the amplified voltage of the amplifier circuit 550, namely the voltage signal VHV1, can be made lower than the voltage value of the amplified voltage of the drive circuit 50 of the first embodiment, namely the voltage signal VHV. This reduces the loss of the transistors M1 and M2 included in the amplifier circuit 550, and reduces the power consumption of the drive circuit 50.

[0176] In addition, even in the driving circuit 50 of the second embodiment, the basic driving signal correction circuit 510 calculates the number of piezoelectric elements 60 supplied with the driving signal VOUT generated based on the driving signal COM according to the printing data signal SI, and corrects the basic driving signal dA or the basic driving signal aA corresponding to the basic driving signal dA based on the calculation result, thereby achieving the same effect as the liquid ejecting device 1 of the first embodiment.

[0177] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments can be appropriately combined.

[0178] The present invention includes structures that are substantially the same as the structures described in the embodiments (for example, structures with the same functions, methods, and results, or structures with the same purposes and effects). In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that can achieve the same effects as the structures described in the embodiments, or structures that can achieve the same purposes. In addition, the present invention includes structures that add known technologies to the structures described in the embodiments.

[0179] The following contents can be derived from the above-mentioned embodiment.

[0180] One embodiment of a liquid ejection device comprises: a liquid ejection head having a plurality of capacitive loads driven by being supplied with a drive signal, and ejecting liquid by driving the plurality of capacitive loads; a capacitive load drive circuit that outputs the drive signal, the capacitive load drive circuit comprising: a correction circuit that outputs a corrected basic drive signal obtained by correcting a basic drive signal serving as a basis for the drive signal; a modulation circuit that outputs a modulated signal obtained by modulating the corrected basic drive signal; an amplifier circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit including a capacitor, and outputting the drive signal by demodulating the amplified modulated signal; and a feedback circuit that feeds back the drive signal to the correction circuit, the correction circuit outputting the corrected basic drive signal that has been corrected according to the number of driven capacitive loads driven by the drive signal within the plurality of capacitive loads.

[0181] According to this liquid ejection device, the correction circuit corrects the base drive signal, which serves as the basis for the drive signal, based on the number of capacitive loads driven by the drive signal output by the capacitive load drive circuit, and outputs the corrected base drive signal. This corrected base drive signal reduces the likelihood of a change in the voltage value of the drive signal waveform even when the capacitance component generated along the propagation path through which the drive signal propagates varies depending on the number of capacitive loads driven. Consequently, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved, thereby improving the ejection accuracy of liquid in the liquid ejection device.

[0182] In one embodiment of the liquid ejection device, it can also be set to include a switching circuit, which switches the supply of the drive signal to the multiple capacitive loads based on the ejection data, and the correction circuit calculates the number of the driven capacitive loads within the multiple capacitive loads based on the ejection data.

[0183] According to this liquid ejection device, by calculating the number of driven capacitive loads based on the ejection data, the number of driven capacitive loads driven by the drive signal can be easily and accurately grasped. As a result, the waveform accuracy of the drive signal output by the capacitive load drive circuit is further improved, thereby further improving the ejection accuracy of the liquid in the liquid ejection device.

[0184] In one embodiment of the liquid ejection device, the feedback circuit may include a high-pass filter.

[0185] In one embodiment of the liquid ejection device, the feedback circuit may include a low-pass filter.

[0186] In one embodiment of the liquid ejection device, each of the plurality of capacitive loads may be a piezoelectric element.

[0187] In one embodiment of the liquid ejection device, it can also be set that when the number of the driven capacitive loads is large, the correction circuit outputs the corrected basic drive signal that is corrected in a manner that reduces the amplitude of the basic drive signal.

[0188] In one embodiment of the liquid ejection device, it can also be set that when the number of the driven capacitive loads is small, the correction circuit outputs the corrected basic drive signal that is corrected in such a manner that the amplitude of the basic drive signal becomes larger.

[0189] One form of a capacitive load driving circuit is a capacitive load driving circuit that outputs a driving signal to a liquid ejection head, wherein the liquid ejection head has a plurality of capacitive loads that are driven by being supplied with the driving signal and ejects liquid by driving the plurality of capacitive loads, and the capacitive load driving circuit has: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal that is the basis of the driving signal; a modulation circuit that outputs a modulated signal obtained by modulating the corrected basic driving signal; an amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit that includes a capacitor and outputs the driving signal by demodulating the amplified modulated signal; and a feedback circuit that feeds back the driving signal to the correction circuit, the correction circuit outputting the corrected basic driving signal that is corrected according to the number of driving capacitive loads driven by the driving signal among the plurality of capacitive loads.

[0190] According to this capacitive load driving circuit, the correction circuit corrects the base driving signal, which serves as the basis for the driving signal, according to the number of capacitive loads driven by the driving signal output by the capacitive load driving circuit, and outputs the corrected base driving signal. Thus, the driving signal generated based on the corrected base driving signal reduces the possibility of a change in the voltage value of the signal waveform of the driving signal, even when the capacitance component generated on the propagation path through which the driving signal propagates varies according to the number of capacitive loads driven. Consequently, the waveform accuracy of the driving signal output by the capacitive load driving circuit is improved.

[0191] Explanation of symbols

[0192] 1…Liquid ejecting device; 2…Moving body; 3…Moving unit; 4…Conveying unit; 10…Control unit; 11…Power supply circuit; 20…Head unit; 21…Liquid ejecting head; 24…Slide; 31…Slide motor; 32…Slide guide shaft; 33…Timing belt; 40…Platen; 41…Conveying motor; 42…Conveying roller; 50…Drive circuit; 60…Piezoelectric element; 70…Level conversion circuit; 100…Control unit; 190…Cable; 200…Drive signal selection circuit; 210…Selection control circuit; 212…Shift register; 214…Latch circuit; 216…Decoder; 230…Selection circuit; 232…Inverter; 234…Transmission gate; 500…Integrated circuit; 510…Basic drive signal correction circuit; 512…Drive element number counting circuit; 513…Correction value calculation circuit; 514-516…Adders 520…modulation circuit; 521…inverter; 530…gate driver circuit; 531, 532…gate driver; 541…integrating attenuator; 542…attenuator; 550…amplifier circuit; 560…demodulation circuit; 570…first feedback circuit; 572…second feedback circuit; 600…ejector; 601…piezoelectric element; 611, 612…electrodes; 621…vibration plate; 631…chamber; 63 2…nozzle plate; 641…liquid reservoir; 651…nozzle; 710…reference level switching circuit; 721…inverter; 730…gate driver circuit; 731, 732…gate drivers; BS…bootstrap circuit; C1–C5, C11–C13…capacitors; D1, D11–D13…diodes; L…nozzle array; L1…inductor; M1–M4…transistors; P…dielectric; R1–R6…resistors.

Claims

1. A liquid ejection device, characterized in that: have: a liquid ejection head having a plurality of capacitive loads driven by supplying a driving signal, and ejecting liquid by driving the plurality of capacitive loads; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal serving as a basis for the driving signal; a modulation circuit which outputs a modulation signal obtained by modulating the correction basic drive signal; an amplifier circuit configured to output an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit comprising a capacitor and outputting the driving signal by demodulating the amplified modulation signal; a feedback circuit, which feeds back the driving signal to the correction circuit, The correction circuit outputs the correction basic drive signal corrected according to the number of driving capacitive loads driven by the drive signal among the plurality of capacitive loads. When the number of the driven capacitive loads is large, the correction circuit outputs the corrected basic drive signal that is corrected so as to reduce the amplitude of the basic drive signal.

2. The liquid ejection device according to claim 1, wherein A switching circuit is provided for switching the supply of the driving signal to the plurality of capacitive loads based on ejection data, The correction circuit calculates the number of the driven capacitive loads among the plurality of capacitive loads based on the ejection data.

3. The liquid ejection device according to claim 1 or 2, wherein: The feedback circuit includes a high pass filter.

4. The liquid ejecting device according to claim 3, wherein The feedback circuit includes a low-pass filter.

5. The liquid ejecting device according to claim 1, wherein Each of the plurality of capacitive loads is a piezoelectric element.

6. The liquid ejecting device according to claim 1, wherein When the number of the driven capacitive loads is small, the correction circuit outputs the corrected basic drive signal that is corrected so as to increase the amplitude of the basic drive signal.

7. A capacitive load driving circuit, characterized in that: The liquid ejection head outputs a driving signal to the liquid ejection head. The liquid ejection head has a plurality of capacitive loads driven by the driving signal and ejects liquid by driving the plurality of capacitive loads. The capacitive load driving circuit comprises: a correction circuit that outputs a corrected basic driving signal obtained by correcting a basic driving signal serving as a basis for the driving signal; a modulation circuit which outputs a modulation signal obtained by modulating the correction basic drive signal; an amplifier circuit configured to output an amplified modulated signal obtained by amplifying the modulated signal; a demodulation circuit comprising a capacitor and outputting the driving signal by demodulating the amplified modulation signal; a feedback circuit, which feeds back the driving signal to the correction circuit, The correction circuit outputs the correction basic drive signal corrected according to the number of driving capacitive loads driven by the drive signal among the plurality of capacitive loads. When the number of the driven capacitive loads is large, the correction circuit outputs the corrected basic drive signal that is corrected so as to reduce the amplitude of the basic drive signal.

Images