Four-frequency reconfigurable mmic power amplifier and its regulation method

Abstract

The application discloses a four-frequency reconfigurable MMIC power amplifier and a regulation method thereof, aims at overcoming the problems of low gain and low efficiency of a wideband power amplifier in the prior art, and comprises a reconfigurable input matching network, a driving stage circuit bias network, a reconfigurable inter-stage matching network, an amplification stage circuit bias network and a reconfigurable output matching network which are electrically connected in sequence, wherein the compact reconfigurable matching network is used to improve the gain, output power and efficiency of the power amplifier, and the power amplifier has higher practicability and expandability.

Description

Technical Field

[0001] This invention relates to the field of radio frequency communication, and in particular to a quad-band reconfigurable MMIC power amplifier and its control method, which utilizes reconfigurable switching technology to support four different operating frequency bands while maintaining output power and efficiency. Background Technology

[0002] Radio frequency (RF) power amplifiers (PAs), as one of the key components in the RF front-end, amplify the power of RF signals to provide sufficient power for signal propagation in space. They are typically located at the end of the transmit channel (Tx) gain chain. The performance of the power amplifier directly determines the communication distance, signal quality, and operational lifespan of the microwave system. Therefore, the design of high-performance power amplifiers is of great interest.

[0003] As a power amplification device in the transmit channel of a transceiver module (T / R module) chip / communication transceiver front-end, the power amplifier is generally located after the driver amplifier and before the transmitting antenna, in the transmit path. It amplifies the radio frequency signal to be transmitted and transmits it to the antenna for final radiation into space. The operating frequency and output power of the power amplifier directly determine the operating conditions and applicable environment of the transceiver system, while its efficiency determines the battery life of the system. Furthermore, the linearity of the power amplifier also determines the quality of the transmitted signal. Therefore, a power amplifier with a wide operating frequency range, high output power, high efficiency, and good linearity is a constantly evolving goal.

[0004] The technological advancements driven by user demands for information transmission and sensing place higher demands on the high-frequency performance and output power of electronic devices. In recent years, microwave monolithic integrated circuits (MMICs) based on High Electron Mobility Transistor (HEMT) technology have emerged as a leading technology, offering superior and more stable high-frequency performance, higher integration density, and better process consistency compared to traditional RF board-level PCB processes.

[0005] Radio frequency power amplifiers are typically composed of two or three stages of transistor circuits connected in series. They can be divided into gain stage circuits, driver stage circuits, and amplification stage circuits. The former provides sufficient input power for the saturation output of the latter and improves the overall gain of the circuit. The latter determines the output power of the power amplifier. In addition, some matching structure networks are needed to realize impedance transformation in order to achieve maximum power transmission and reduce losses.

[0006] The 5G NR standard includes Sub-6GHz bands and millimeter-wave bands. Each band contains several communication channels, and the bandwidth of each channel is significantly increased compared to the 4G LTE standard. A highly integrated 5G NR transceiver should operate in frequency bands that cover both Sub-6GHz and millimeter-wave bands as much as possible. Therefore, there is a huge demand for broadband power amplifiers in the industry.

[0007] According to the finite gain-bandwidth product theory, the bandwidth of a power amplifier is usually contradictory to its gain. Under the same transistor process size, bias and other conditions, a broadband amplifier has lower gain, lower output power and lower operating efficiency than a narrowband amplifier, which contradicts the industry's goal of developing high-performance power amplifiers.

[0008] Therefore, there is an urgent need to propose a multi-frequency reconfigurable MMIC power amplifier and its control method. By reconfiguring a wideband into multiple narrowbands to meet communication and other requirements, the amplifier can achieve high gain and efficiency while maintaining wide bandwidth, thus solving the problems of low gain and low efficiency in traditional wideband power amplifiers. Furthermore, by utilizing a compact reconfigurable matching network structure, the matching network can achieve optimal impedance matching and power matching within the narrowband while realizing the simplest circuit topology, thereby solving the problems of bandwidth limitation in traditional matching networks and large chip area in traditional reconfigurable power amplifier circuits. Summary of the Invention

[0009] To overcome the shortcomings and problems of existing technologies, this invention provides a four-band reconfigurable MMIC power amplifier and its control method. By utilizing reconfigurable switching technology, a single broadband frequency band is discretized into multiple narrowband frequencies. While meeting the required operating frequency bands, the gain, efficiency, and other performance of the power amplifier are improved, significantly increasing the integration of the power amplifier in the transceiver assembly and reducing costs.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A quad-band reconfigurable MMIC power amplifier includes a reconfigurable input matching network, a driver stage circuit bias network, a reconfigurable inter-stage matching network, an amplifier stage circuit bias network, and a reconfigurable output matching network that are electrically connected together in sequence.

[0012] Preferably, the reconfigurable input matching network includes a reconfigurable bridge switched capacitor structure, comprising capacitors C2, C3, C4, and C5, and switches S1 and S2. Capacitors C2, C3, and S1 are connected end-to-end to form a first loop structure, and capacitors C4, C5, and S2 are connected end-to-end to form a second loop structure. The first loop structure, the second loop structure, and the driver stage circuit bias network are sequentially electrically connected together. The line between capacitor C2 and switch S1 is electrically connected to the line between capacitor C4 and switch S2, and the driver stage circuit bias network is electrically connected between capacitors C4 and C5.

[0013] Preferably, the reconfigurable input matching network further includes a capacitor C1 and an inductor L1. One end of the capacitor C1 is electrically connected to the source port, and the other end of the capacitor C1 is electrically connected to the reconfigurable bridge switched capacitor structure. The inductor L1 is disposed in the bypass of the reconfigurable input matching network. One end of the inductor L1 is electrically connected between the capacitor C1 and the reconfigurable bridge switched capacitor structure, and the other end of the inductor L1 is electrically connected to the ground line.

[0014] Preferably, the reconfigurable input matching network further includes an inductor L2 and a capacitor C6. One end of the capacitor C6 is electrically connected to the reconfigurable bridge switched capacitor structure, and the other end of the capacitor C6 is electrically connected to the driver stage circuit bias network. One end of the inductor L2 is electrically connected between the capacitor C6 and the reconfigurable bridge switched capacitor structure, and the other end of the inductor L2 is electrically connected to the ground line.

[0015] Preferably, the driver stage circuit bias network includes a first transistor, a reconfigurable input matching network electrically connected to the gate of the first transistor, a reconfigurable inter-stage matching network electrically connected to the drain of the first transistor, and the source of the first transistor electrically connected to ground.

[0016] Preferably, the driver stage circuit bias network further includes a first gate bias portion, the reconfigurable input matching network is electrically connected to the first gate bias portion, the first gate bias portion is also electrically connected to the gate of the first transistor, the first gate bias portion is disposed between the reconfigurable input matching network and the gate of the first transistor, and the first gate bias portion adopts a resistor-inductor circuit structure.

[0017] Preferably, the first gate bias portion includes a resistor R1, an inductor L3, a resistor R2, and a capacitor C7. One end of the resistor R1 is electrically connected between the reconfigurable input matching network and the gate of the first transistor, and the other end of the resistor R1 is electrically connected to the inductor L3. One end of the resistor R2 is electrically connected to the inductor L3, and the other end of the resistor R2 is used to electrically connect to the gate-source voltage source VGS. One end of the capacitor C7 is electrically connected between the inductor L3 and the resistor R2, and the other end of the capacitor C7 is electrically connected to the ground line.

[0018] Preferably, the driver stage circuit bias network further includes a first transmission line matching bias structure, which is electrically connected to the drain of the first transistor.

[0019] Preferably, the first transmission line matching bias structure includes a transmission line L4, a capacitor C8, a resistor R3, and a capacitor C9. One end of the transmission line L4 is electrically connected to the drain of the first transistor, and the other end of the transmission line L4 is used to electrically connect to the drain-source voltage source VDS. One end of the capacitor C8 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of the capacitor C8 is electrically connected to ground. The resistor R3 and the capacitor C9 are connected in series. One end of the resistor R3 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of the resistor R3 is electrically connected to the capacitor C9, which is also electrically connected to ground.

[0020] Preferably, the reconfigurable inter-stage matching network includes capacitor C10, inductor L5, resistor R4, capacitors C11, C12, C13, C14, C15, and C16, transmission line L6, switch S3, and switch S4. One end of capacitor C10 is electrically connected to the driver stage circuit bias network, and the other end of capacitor C10 is electrically connected to inductor L5. One end of resistor R4 is electrically connected to inductor L5, and the other end of resistor R4 is electrically connected to capacitor C11. One end of capacitor C11 is electrically connected to resistor R4, and the other end of capacitor C11 is electrically connected to transmission line L6. Capacitor C12 is connected in parallel with the circuit containing resistor R4 and capacitor C11. One end of capacitor C12 is electrically connected to inductor L5. The other end is electrically connected to transmission line L6. Capacitors C13 and C14 are connected in series. One end of capacitor C13 is electrically connected between capacitor C11 and transmission line L6, and the other end of capacitor C13 is electrically connected to capacitor C14. Capacitor C14 is also electrically connected to the ground wire. One end of switch S3 is electrically connected between capacitors C13 and C14, and the other end of switch S3 is electrically connected to the ground wire. Capacitors C15 and C16 are connected in series. One end of capacitor C15 is electrically connected between capacitor C11 and transmission line L6, and the other end of capacitor C15 is electrically connected to capacitor C16. Capacitor C16 is also electrically connected to the ground wire. One end of switch S4 is electrically connected between capacitors C15 and C16, and the other end of switch S4 is electrically connected to the ground wire.

[0021] Preferably, the bias network of the amplifier stage circuit includes a second transistor, a reconfigurable interstage matching network is electrically connected to the gate of the second transistor, the drain of the second transistor is electrically connected to the reconfigurable output matching network, and the source of the second transistor is electrically connected to ground.

[0022] Preferably, the amplification stage circuit bias network further includes a second gate bias portion, which is disposed between the reconfigurable interstage matching network and the second transistor. The second gate bias portion adopts a resistor-inductor circuit structure.

[0023] Preferably, the second gate bias portion includes a resistor R5, an inductor L7, and a capacitor C17. One end of the resistor R5 is electrically connected between the reconfigurable interstage matching network and the second transistor. One end of the inductor L7 is electrically connected to the resistor R5, and the other end of the inductor L7 is used to electrically connect to the gate-source voltage source VGS. One end of the capacitor C17 is electrically connected between the inductor L7 and the gate-source voltage source VGS, and the other end of the capacitor C17 is electrically connected to the ground line.

[0024] Preferably, the amplification stage circuit bias network further includes a second transmission line matching bias structure, which is electrically connected to the drain of the second transistor.

[0025] Preferably, the second transmission line bias structure includes a transmission line L8, a capacitor C18, a resistor R8, and a capacitor C19. One end of the transmission line L8 is electrically connected to the drain of the second transistor, and the other end of the transmission line L8 is used to electrically connect to the drain-source voltage source VDS. One end of the capacitor C18 is electrically connected between the transmission line and the drain-source voltage source VDS, and the other end of the capacitor C18 is electrically connected to the ground line. The resistor R8 and the capacitor C19 are connected in series and are placed in the bypass of the circuit where the transmission line L8 and the drain-source voltage source VDS are located. One end of the resistor R8 is electrically connected between the capacitor C18 and the drain-source voltage source VDS, and the other end of the resistor R8 is electrically connected to the capacitor C19, which is also electrically connected to the ground line.

[0026] Preferably, the reconfigurable output matching network includes transmission line L9, transmission line L10, capacitors C20, C21, C22, C23, and C24, switch S5, and switch S6. One end of transmission line L9 is electrically connected to the bias network of the amplifier stage circuit, and the other end of transmission line L9 is electrically connected to transmission line L10. One end of capacitor C24 is electrically connected to transmission line L10, and the other end of capacitor C24 is used to electrically connect to the load port. Transmission line L9, transmission line L10, capacitor C24, and the load port are connected in series. Capacitors C20 and C21 are connected in parallel. One end of capacitor C20 is electrically connected between transmission line L9 and transmission line L10. The other end of capacitor C20 is electrically connected to capacitor C22. One end of capacitor C21 is electrically connected between transmission line L10 and capacitor C24. The other end of capacitor C21 is electrically connected to capacitor C22. One end of capacitor C22 is electrically connected to capacitors C20 and C21. The other end of capacitor C22 is electrically connected to capacitor C23. One end of capacitor C23 is electrically connected to capacitor C22. The other end of capacitor C23 is electrically connected to ground. Switch S5 is connected in series with capacitor C20. Switch S5 is positioned between capacitors C20 and C22. Switch S6 is connected in parallel with capacitor C23. One end of switch S6 is electrically connected between capacitors C22 and C23. The other end of switch S6 is electrically connected to ground.

[0027] This invention also provides a method for controlling a four-band reconfigurable MMIC power amplifier, based on the above-mentioned four-band reconfigurable MMIC power amplifier, comprising:

[0028] If switch S1 is short-circuited, switch S2 is short-circuited, switch S3 is open-circuited, switch S4 is open-circuited, switch S5 is short-circuited, and switch S6 is short-circuited, the four-band reconfigurable MMIC power amplifier operates in the first frequency band.

[0029] If switch S1 is short-circuited, switch S2 is open-circuited, switch S3 is short-circuited, switch S4 is short-circuited, switch S5 is short-circuited, and switch S6 is open-circuited, the four-band reconfigurable MMIC power amplifier operates in the second frequency band.

[0030] If switch S1 is open, switch S2 is short, switch S3 is short, switch S4 is open, switch S5 is open and switch S6 is short, the four-band reconfigurable MMIC power amplifier operates in the third frequency band.

[0031] If switch S1 is open, switch S2 is open, switch S3 is open, switch S4 is short-circuited, switch S5 is open, and switch S6 is open, the four-band reconfigurable MMIC power amplifier operates in the fourth frequency band.

[0032] Preferably, the opening and closing states of switches S1, S2, S3, S4, S5, and S6 are controlled by control signals A and B, specifically including:

[0033] If control signal A is high and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the first frequency band.

[0034] If control signal A is high and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the second frequency band.

[0035] If control signal A is low and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the third frequency band.

[0036] If control signal A is low and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the fourth frequency band.

[0037] The outstanding and beneficial technical effects of this invention compared to the prior art are:

[0038] In this invention, the input radio frequency signal passes through a reconfigurable input matching network, enters the bias network of the driver stage circuit for pre-amplification to achieve the saturated input power required by the bias network of the amplifier stage circuit, passes through a reconfigurable inter-stage matching network, enters the bias network of the amplifier stage circuit for amplification, and is output to the load through a reconfigurable output matching network, thus realizing the power amplification of the radio frequency signal. Furthermore, by controlling the opening and closing states of switches S1, S2, S3, S4, S5, and S6, the power amplifier can operate in four frequency bands.

[0039] In this invention, a reconfigurable input matching network is used to achieve bandpass input matching and bandpass gain; a reconfigurable inter-stage matching network is used to achieve impedance matching of the optimal load impedance of the driver stage circuit and the optimal source impedance of the amplifier stage circuit; and a reconfigurable output matching network is used to achieve the optimal load impedance of the amplifier stage circuit. By controlling switches S1, S2, S3, S4, S5, and S6, the power amplifier can switch between four frequency bands. By using reconfigurable switching technology, a single broadband amplifier is discretized into multiple narrowband amplifiers, overcoming the problems of low gain and low efficiency in broadband power amplifiers. The compact reconfigurable matching network improves the gain, output power, operating efficiency, integration, and reduces the cost of the power amplifier, making it highly practical and scalable.

[0040] In this invention, two independent control signals A and B are used to realize the switching of the four-band reconfigurable MMIC power amplifier in four frequency bands. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the circuit principle of the four-frequency reconfigurable MMIC power amplifier of the present invention;

[0042] Figure 2 This is a schematic diagram of the S-parameter performance results of the present invention in ADS data testing;

[0043] Figure 3 This is a schematic diagram of the power performance results of the present invention tested in ADS;

[0044] Figure 4 This is a schematic diagram illustrating the efficiency performance results of data testing in ADS according to the present invention. Detailed Implementation

[0045] To facilitate understanding by those skilled in the art, the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0046] like Figure 1 As shown, this embodiment provides a quad-band reconfigurable MMIC power amplifier to support four different frequency bands. It includes a reconfigurable input matching network, a driver stage bias network, a reconfigurable inter-stage matching network, an amplifier stage bias network, and a reconfigurable output matching network. The reconfigurable input matching network is electrically connected to an active port, and the reconfigurable output matching network is electrically connected to a load port. The active port, reconfigurable input matching network, driver stage bias network, reconfigurable inter-stage matching network, amplifier stage bias network, reconfigurable output matching network, and load port are sequentially electrically connected together.

[0047] The reconfigurable input matching network is used to achieve bandpass input matching and bandpass gain of the power amplifier in different frequency bands. The reconfigurable input matching network is positioned between the source port and the driver stage bias network. In this embodiment, a standard 50-ohm source port is selected. In practical applications, by controlling the reconfigurable input matching network, the input impedance of the power amplifier and the impedance of the source port can be conjugate-matched at different frequency bands, achieving bandpass gain effects at different frequency bands. In this embodiment, the reconfigurable input matching network is used to achieve bandpass input matching and bandpass gain of the power amplifier in four different frequency bands.

[0048] The reconfigurable input matching network includes a reconfigurable bridge switched capacitor structure. The reconfigurable bridge switched capacitor is used to ensure that the input impedance and source port impedance of the power amplifier can be conjugate matched in four different frequency bands, thereby achieving the bandpass gain effect of the power amplifier in the four frequency bands.

[0049] The reconfigurable bridge-type switched-capacitor structure includes capacitors C2, C3, C4, and C5, and switches S1 and S2. Capacitors C2, C3, and S1 are connected end-to-end to form a first loop structure, and capacitors C4, C5, and S2 are connected end-to-end to form a second loop structure. The source port, the first loop structure, the second loop structure, and the driver stage bias network are sequentially electrically connected together. The source port is electrically connected between capacitors C2 and C3. The line between capacitor C2 and switch S1 is electrically connected to the line between capacitor C4 and switch S2. The driver stage bias network is electrically connected between capacitors C4 and C5. In practical applications, by controlling switches S1 and S2, optimal conjugate matching of the power amplifier is achieved across four frequency bands.

[0050] The reconfigurable input matching network also includes a capacitor C1 and an inductor L1, which together form a high-pass matching network. One end of the capacitor C1 is electrically connected to the source port, and the other end of the capacitor C1 is electrically connected to the reconfigurable bridge switched capacitor structure. The inductor L1 is placed in the bypass of the reconfigurable input matching network. One end of the inductor L1 is electrically connected between the capacitor C1 and the reconfigurable bridge switched capacitor structure, and the other end of the inductor L1 is electrically connected to the ground line.

[0051] The reconfigurable input matching network also includes inductor L2 and capacitor C6, which together form a high-pass matching network. Capacitor C6 is a DC blocking capacitor; one end of capacitor C6 is electrically connected to the reconfigurable bridge switched capacitor structure, and the other end is electrically connected to the driver stage circuit bias network. Inductor L2 is placed in the bypass of the reconfigurable input matching network; one end of inductor L2 is electrically connected between capacitor C6 and the reconfigurable bridge switched capacitor structure, and the other end is electrically connected to ground.

[0052] Specifically, the power amplifier has four different frequency bands, including a first band, a second band, a third band, and a fourth band, denoted by f1, f2, f3, and f4, respectively. In this embodiment, the first band is 1.95-2.50 GHz, the second band is 2.60-3.40 GHz, the third band is 3.60-4.40 GHz, and the fourth band is 4.40-5.10 GHz. In practical use, the reconfigurable input matching network can provide four series susceptances to correspond to the four frequency bands of the power amplifier's four operating states. If both the first switch S1 and the second switch S2 are short-circuited, the series susceptance is calculated using the following formula:

[0053]

[0054] If the first switch S1 is in a short circuit and the second switch S2 is in an open circuit, the series susceptance is calculated using the following formula:

[0055]

[0056] If the first switch S1 is in an open circuit and the second switch S2 is in a short circuit, the series susceptance is calculated using the following formula:

[0057]

[0058] If both the first switch S1 and the second switch S2 are in an open circuit state, their series susceptance can be calculated using the following formula:

[0059]

[0060] Where j is the imaginary unit, Y in1 Y is the series susceptance provided by the reconfigurable input matching network when both the first switch S1 and the second switch S2 are short-circuited. in2 Y is the series susceptance provided by the reconfigurable input matching network when the first switch S1 is short-circuited and the second switch S2 is open-circuited. in3 Y is the series susceptance provided by the reconfigurable input matching network when the first switch S1 is open and the second switch S2 is short-circuited. in4 The series susceptance provided by the reconfigurable input matching network when both the first switch S1 and the second switch S2 are open circuits; C2 is the capacitance of the second capacitor C2; C3 is the capacitance of the third capacitor C3; C4 is the capacitance of the fourth capacitor C4; S1=ON means switch S1 is short-circuited, S1=OFF means switch S1 is open circuit; S2=ON means switch S2 is short-circuited, S2=OFF means switch S2 is open circuit. After tuning the 50-ohm source port through the reconfigurable input matching network, the transmission matrix of the source port is transformed as follows:

[0061]

[0062] in, Y is the transmission matrix of the source port. in There are four options for the series susceptance of the current reconfigurable input matching network, f is the frequency band of the current power amplifier, C1 is the capacitance value of capacitor C1, C6 is the capacitance value of capacitor C6, L1 is the inductance value of inductor L1, and L2 is the inductance value of inductor L2.

[0063] The bias network of the drive stage circuit is used to achieve optimal modulation of the fundamental and second harmonic load impedances and to keep its own power consumption within an acceptable range.

[0064] The bias network of the driving stage circuit includes a first transistor, which is a field-effect transistor and has a class AB or class B operating state. The reconfigurable input matching network is electrically connected to the gate of the first transistor, the reconfigurable inter-stage matching network is electrically connected to the drain of the first transistor, and the source of the first transistor is electrically connected to ground.

[0065] The driver stage circuit bias network further includes a first gate bias section. A reconfigurable input matching network is electrically connected to the first gate bias section, which is also electrically connected to the gate of the first transistor. The first gate bias section is positioned between the reconfigurable input matching network and the gate of the first transistor. The first gate bias section employs a resistor-inductor circuit structure, including resistor R1, inductor L3, resistor R2, and capacitor C7. One end of resistor R1 is electrically connected between the reconfigurable input matching network and the gate of the first transistor, and the other end of resistor R1 is electrically connected to inductor L3. One end of inductor L3 is electrically connected to resistor R1, and the other end of inductor L3 is electrically connected to resistor R2. One end of resistor R2 is electrically connected to inductor L3, and the other end of resistor R2 is used to electrically connect to the gate-source voltage source VGS. Capacitor C7 is positioned as a bypass in the circuit containing resistors R1, L3, and R2. One end of capacitor C7 is electrically connected between inductor L3 and resistor R2, and the other end of capacitor C7 is electrically connected to ground.

[0066] The driver stage circuit bias network further includes a first transmission line matching bias structure, which is electrically connected to the drain of the first transistor. The first transmission line matching bias structure achieves low loss in the driver stage circuit bias network.

[0067] The first transmission line matching bias structure includes a transmission line L4, a capacitor C8, a resistor R3, and a capacitor C9. One end of the transmission line L4 is electrically connected to the drain of the first transistor, and the other end of the transmission line L4 is used to electrically connect to the drain-source voltage source VDS. Capacitor C8 is located in the bypass position; one end of capacitor C8 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of capacitor C8 is electrically connected to ground. Resistor R3 and capacitor C9 are connected in series; one end of resistor R3 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of resistor R3 is electrically connected to capacitor C9, which is also electrically connected to ground.

[0068] The reconfigurable interstage matching network is electrically connected between the driver stage circuit bias network and the amplifier stage circuit bias network to achieve optimal source impedance matching between the driver stage circuit bias network and the amplifier stage circuit bias network for four different frequency bands.

[0069] The reconfigurable interstage matching network includes capacitor C10, inductor L5, resistor R4, capacitors C11, C12, C13, C14, C15, and C16, transmission line L6, switch S3, and switch S4. One end of capacitor C10 is electrically connected to the gate of the first transistor in the driver stage circuit bias network, and the other end of capacitor C10 is electrically connected to inductor L5. Capacitors C10 and L5 function as a high-pass matching network. Inductor L5 is placed in the bypass and is also electrically connected to ground. One end of resistor R4 is electrically connected to inductor L5, and the other end of resistor R4 is electrically connected to capacitor C11. Resistor R4 and capacitor C11 are connected in series, forming an RC series structure. One end of capacitor C11 is electrically connected to resistor R4, and the other end of capacitor C11 is electrically connected to transmission line L6. The circuit containing capacitor C12, resistor R4, and capacitor C11 is connected in parallel. One end of capacitor C12 is electrically connected to inductor L5, and the other end is electrically connected to transmission line L6. Capacitor C12, resistor R4, and capacitor C11 form an RC parallel structure. Capacitors C13 and C14 are located as bypasses in the circuit containing capacitor C10, resistor R4, capacitor C11, and transmission line L6. Capacitors C13 and C14 are connected in series. One end of capacitor C13 is electrically connected between capacitor C11 and transmission line L6, and the other end is electrically connected to capacitor C14. Capacitor C14 is also electrically connected to ground. One end of switch S3 is electrically connected between capacitors C13 and C14, and the other end is electrically connected to ground. Switch S3 is used to reconfigure the bypass connection of capacitors C13 and C14 into the main circuit. Capacitors C15 and C16 are located in the bypass circuit containing capacitor C10, resistor R4, capacitor C11, and transmission line L6. Capacitors C15 and C16 are connected in series. One end of capacitor C15 is electrically connected between capacitor C11 and transmission line L6, and the other end of capacitor C15 is electrically connected to capacitor C16. Capacitor C16 is also electrically connected to ground. One end of switch S4 is electrically connected between capacitors C15 and C16, and the other end of switch S4 is electrically connected to ground. In practical applications, by controlling switches S3 and S4, the reconfigurable interstage matching network can provide four different parallel susceptances, corresponding to four different frequency bands of the power amplifier.

[0070] Specifically, in practical applications, the reconfigurable interstage matching network can provide four parallel susceptances to correspond to the frequency bands of the four operating states of the power amplifier. If both switches are short-circuited in S3 and S4, the parallel susceptance provided by the reconfigurable interstage matching network can be calculated using the following formula:

[0071] Y inter1 =j*2πf1(C 13 +C 15S3 = ON, S4 = ON;

[0072] If switch S3 is in a short circuit and switch S4 is in an open circuit, the parallel susceptance can be calculated using the following formula:

[0073]

[0074] If switch S3 is open and switch S4 is short-circuited, the parallel susceptance provided by the reconfigurable interstage matching network can be calculated using the following formula:

[0075]

[0076] If both switch S3 and switch S4 are in an open circuit, the parallel susceptance provided by the reconfigurable interstage matching network can be calculated using the following formula:

[0077]

[0078] Among them, Y inter1 Y is the parallel susceptance provided by the reconfigurable interstage matching network when both switches S3 and S4 are short-circuited. inter2 Y is the parallel susceptance provided by the reconfigurable interstage matching network when switch S3 is short-circuited and switch S4 is open-circuited. inter3 Y is the parallel susceptance provided by the reconfigurable interstage matching network when switch S3 is in an open circuit and switch S4 is in a short circuit. inter4 C is the parallel susceptance provided by the reconfigurable interstage matching network when both switches S3 and S4 are open. 13 Here is the capacitance value of capacitor C13, C 14 Here is the capacitance value of capacitor C14, C 15 Here is the capacitance value of capacitor C15, C 16 Here is the capacitance value of capacitor C16. S3=ON means switch S3 is short-circuited, S3=OFF means switch S3 is open-circuited, S4=ON means switch S4 is short-circuited, and S4=OFF means switch S4 is open-circuited.

[0079] The bias network of the amplifier stage circuit includes a second transistor, which is a field-effect transistor (FET) with either Class AB or Class B operating mode. Transmission line L6 is electrically connected to the gate of the second transistor, the drain of the second transistor is electrically connected to the reconfigurable output matching network, and the source of the second transistor is electrically connected to ground. In this embodiment, at least two second transistors are used in parallel, thereby improving the current amplification effect of the bias network of the amplifier stage circuit and shunting the current to avoid heat buildup.

[0080] The amplification stage circuit bias network also includes a second gate bias section. A reconfigurable inter-stage matching network is electrically connected to the second gate bias section, which is also electrically connected to the gate of the second transistor. The second gate bias section is positioned between the reconfigurable inter-stage matching network and the second transistor. The second gate bias section also employs a resistor-inductor circuit structure, including resistor R6, resistor R5, inductor L7, and capacitor C17. One end of resistor R5 is electrically connected between the reconfigurable inter-stage matching network and the second transistor, and the other end of resistor R5 is electrically connected to inductor L7. One end of inductor L7 is electrically connected to resistor R5, and the other end of inductor L7 is used to electrically connect to the gate-source voltage source VGS. Capacitor C17 is positioned as a bypass in the circuit containing resistor R5 and inductor L7. One end of capacitor C17 is electrically connected between inductor L7 and the gate-source voltage source VGS, and the other end of capacitor C17 is electrically connected to ground. Resistor R6 is placed between the gates of the two second transistors. One end of resistor R6 is electrically connected to the gate of one second transistor, and the other end of resistor R6 is electrically connected to the gate of the other second transistor.

[0081] The amplifier stage circuit bias network also includes a second transmission line matching bias structure, which is electrically connected to the drain of the second transistor. The second transmission line matching bias structure realizes low loss of the amplifier stage circuit bias network, achieves modulation of the optimal fundamental and second harmonic load impedance, and supplies power to the drain of the second transistor.

[0082] The second transmission line bias structure includes a resistor R7, a transmission line L8, a capacitor C18, and a capacitor C19. Resistor R7 is positioned between the drains of the two second transistors, with one end electrically connected to the drain of one second transistor and the other end electrically connected to the drain of the other. One end of transmission line L8 is electrically connected to the drain of the second transistor, and the other end is used to electrically connect to the drain-source voltage source VDS. Capacitor C18 is positioned as a bypass in the circuit containing the transmission line and the drain-source voltage source VDS, with one end electrically connected between the transmission line and the drain-source voltage source VDS, and the other end electrically connected to ground. Resistor R8 and capacitor C19 are connected in series. Resistor R8 and capacitor C19 are placed on the bypass of the circuit where the transmission line and the drain-source voltage source VDS are located. One end of resistor R8 is electrically connected between capacitor C18 and the drain-source voltage source VDS, and the other end of resistor R8 is electrically connected to capacitor C19. Capacitor C19 is also electrically connected to the ground line.

[0083] The reconfigurable output matching network is used to achieve the optimal load impedance for the bias network of the amplifier stage circuit. The reconfigurable output matching network adopts a reconfigurable switch-capacitor-microstrip line matching structure, thereby achieving the optimal load impedance provided to the bias network of the amplifier stage circuit at four frequency bands of the power amplifier.

[0084] The reconfigurable output matching network includes transmission line L9, transmission line L10, capacitors C20, C21, C22, C23, and C24, switch S5, and switch S6. One end of transmission line L9 is electrically connected to the bias network of the amplifier stage circuit, specifically to the drain of the second transistor, and the other end of transmission line L9 is electrically connected to transmission line L10. One end of transmission line L10 is electrically connected to transmission line L9, and the other end of transmission line L10 is electrically connected to capacitor C24. One end of capacitor C24 is electrically connected to transmission line L10, and the other end of capacitor C24 is used to electrically connect to the load port, which is also 50 ohms. Transmission lines L9, L10, capacitor C24, and the load port are connected in series. Capacitors C20, C21, C22, and C23, along with switches S5 and S6, are configured as a bypass in the circuit containing transmission lines L9 and L10 and capacitor C24. By controlling switches S5 and S6, the total capacitance of the bypass can be adjusted, thereby providing the optimal load impedance for the bias network of the amplifier stage circuit. Capacitors C20 and C21 are connected in parallel. One end of capacitor C20 is electrically connected between transmission lines L9 and L10, and the other end is electrically connected to capacitor C22. One end of capacitor C21 is electrically connected between transmission line L10 and capacitor C24, and the other end is electrically connected to capacitor C22. One end of capacitor C22 is electrically connected to capacitors C20 and C21, and the other end is electrically connected to capacitor C23. One end of capacitor C23 is electrically connected to capacitor C22, and the other end is connected to ground. Switch S5 is connected in series with capacitor C20, and is positioned between capacitors C20 and C22. Switch S6 is connected in parallel with capacitor C23, with one end of switch S6 electrically connected between capacitors C22 and C23, and the other end of switch S6 electrically connected to ground.

[0085] In practical applications, by controlling switches S5 and S6, the reconfigurable output matching network can provide four series impedances to match the four frequency bands of the power amplifier. If both switches S5 and S6 are short-circuited, the series impedance provided by the reconfigurable output matching network can be calculated using the following formula:

[0086]

[0087] If switch S5 is in a short circuit and switch S6 is in an open circuit, the series impedance provided by the reconfigurable output matching network can be calculated using the following formula:

[0088]

[0089] If switch S5 is in an open circuit and switch S6 is in a short circuit, the series impedance provided by the reconfigurable output matching network can be calculated using the following formula:

[0090]

[0091] If both switches S5 and S6 are open circuits, the series impedance provided by the reconfigurable output matching network can be calculated using the following formula:

[0092]

[0093] Among them, Z out1 Z is the series impedance provided by the reconfigurable output matching network when both switches S5 and S6 are short-circuited. out2 Z is the series impedance provided by the reconfigurable output matching network when switch S5 is short-circuited and switch S6 is open-circuited. out3 Z is the series impedance provided by the reconfigurable output matching network when switch S5 is open and switch S6 is short-circuited. out4 C is the series impedance provided by the reconfigurable output matching network when both switches S5 and S6 are open. 20 Here is the capacitance value of capacitor C20, C 21 Here is the capacitance value of capacitor C21, C 22 Here is the capacitance value of capacitor C22, C 23 Here is the capacitance value of capacitor C23, C 24 Here is the capacitance value of capacitor C24. S5=ON means switch S5 is short-circuited, S5=OFF means switch S5 is open-circuited, S6=ON means switch S6 is short-circuited, and S6=OFF means switch S6 is open-circuited.

[0094] This embodiment also provides a design method for a quad-band reconfigurable MMIC power amplifier, which is used to design the aforementioned quad-band reconfigurable MMIC power amplifier, and is achieved through the following steps:

[0095] Step 1: Design the peripheral dimensions of the first and second transistors, and determine the resistance values ​​of resistors R6 and R7 while meeting their output power and power gain requirements.

[0096] Step 2: Design the bias network for the driver stage circuit and the bias network for the amplifier stage circuit to ensure that the first transistor and the second transistor meet the design requirements in Class AB or Class B operating conditions. Adjust resistors R1 and R5 to ensure that the output resistances of the bias network for the driver stage circuit and the bias network for the amplifier stage circuit are positive.

[0097] Step 3: Design a reconfigurable output matching network. Perform load pulling tests on the bias network of the amplifier stage circuit under four frequency bands of the power amplifier. Substitute the four optimal load impedances obtained into the corresponding series impedance calculation formulas to optimize and solve for the capacitance values ​​of capacitor C21, C22, C23, and C24, as well as the inductance value of transmission line L10. Also determine the on / off states of switches S5 and S6 under the four frequency bands.

[0098] Step 4: Design a reconfigurable interstage matching network. Perform source pull tests on the bias network of the amplifier stage circuit and load pull tests on the bias network of the driver stage circuit under four frequency bands of the power amplifier. Substitute the four optimal source impedances and optimal load impedances into the transmission matrix formula of the reconfigurable interstage matching network to optimize and solve for the capacitance values ​​of capacitors C10, C11, C12, C13, C14, C15, and C16, the resistance value of resistor R4, the inductance value of inductor L5, the phase constant of transmission line L6, the length of transmission line L6, the characteristic impedance of transmission line L6, and the characteristic admittance of transmission line L6. Also determine the on / off states of switches S4 and S5 under the four frequency bands.

[0099] Step 5: Design a reconfigurable input matching network. Measure the input impedance of the driver stage bias network in the four frequency bands of the power amplifier. Substitute the obtained input impedance into the transfer matrix formula of the reconfigurable input matching network to optimize and solve for the capacitance values ​​of capacitors C1, C2, C3, C4, C5, and C6, as well as the inductance values ​​of inductors L1 and L2. Also determine the on / off states of switches S1 and S2 in the four frequency bands.

[0100] Step 6: Combine the debugged reconfigurable input matching network, driver stage circuit bias network, reconfigurable inter-stage matching network, amplifier stage circuit bias network, and reconfigurable output matching network together and perform final debugging.

[0101] This embodiment also provides a method for controlling a four-band reconfigurable MMIC power amplifier, based on the above-described four-band reconfigurable MMIC power amplifier, including:

[0102] If switch S1 is short-circuited, switch S2 is short-circuited, switch S3 is open-circuited, switch S4 is open-circuited, switch S5 is short-circuited, and switch S6 is short-circuited, the four-band reconfigurable MMIC power amplifier operates in the first frequency band.

[0103] If switch S1 is short-circuited, switch S2 is open-circuited, switch S3 is short-circuited, switch S4 is short-circuited, switch S5 is short-circuited, and switch S6 is open-circuited, the four-band reconfigurable MMIC power amplifier operates in the second frequency band.

[0104] If switch S1 is open, switch S2 is short, switch S3 is short, switch S4 is open, switch S5 is open and switch S6 is short, the four-band reconfigurable MMIC power amplifier operates in the third frequency band.

[0105] If switch S1 is open, switch S2 is open, switch S3 is open, switch S4 is short-circuited, switch S5 is open, and switch S6 is open, the four-band reconfigurable MMIC power amplifier operates in the fourth frequency band.

[0106] The control method of the four-frequency reconfigurable MMIC power amplifier controls the opening and closing states of switches S1, S2, S3, S4, S5, and S6 through control signals A and B, specifically including:

[0107] If control signal A is high and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the first frequency band.

[0108] If control signal A is high and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the second frequency band.

[0109] If control signal A is low and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the third frequency band.

[0110] If control signal A is low and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the fourth frequency band.

[0111] In the above steps, control signal A and control signal B are independent of each other.

[0112] To verify the actual performance of this quad-band reconfigurable MMIC power amplifier, it was tested, and the test results are as follows: Figures 2 to 4 As shown in the diagram:

[0113] Figure 2 This diagram illustrates the S-parameter performance results of the present invention tested in the ADS (Advanced Design system). As shown in the diagram, when the power amplifier operates in the first frequency band (1.95-2.50 GHz), the input return loss S11 is greater than -10.5 dB, and the positive gain S21 is greater than 19.3 dB; when the power amplifier operates in the second frequency band (2.60-3.40 GHz), the input return loss S11 is greater than -10.8 dB, and the positive gain S21 is greater than 18.8 dB; when the amplifier operates in the third frequency band (3.60-4.40 GHz), the input return loss S11 is greater than -15 dB, and the positive gain S21 is greater than 18.6 dB; when the power amplifier operates in the fourth frequency band (4.40-5.10 GHz), the input return loss S11 is greater than -11.3 dB, and the positive gain S21 is greater than 19.3 dB.

[0114] Figure 3 This diagram illustrates the efficiency performance results of the present invention tested in the ADS (Advanced Design system). As shown in the diagram, the power amplifier operates with a saturated output power greater than 29 dBm in the first frequency band (1.95-2.50 GHz); greater than 29 dBm in the second frequency band (2.60-3.40 GHz); greater than 29 dBm in the third frequency band (3.60-4.40 GHz); and greater than 29.5 dBm in the fourth frequency band (4.40-5.10 GHz).

[0115] Figure 4 This diagram illustrates the efficiency performance results of the present invention tested in the ADS (Advanced Design system). As shown in the diagram, the power amplifier achieves a saturated power-added efficiency (PPE) greater than 45% when operating in the first frequency band (1.95-2.50 GHz); greater than 47% when operating in the second frequency band (2.60-3.40 GHz); greater than 44% when operating in the third frequency band (3.60-4.40 GHz); and greater than 44% when operating in the fourth frequency band (4.40-5.10 GHz).

[0116] Depend on Figures 2 to 4Test results show that this power amplifier utilizes reconfigurable technology to achieve bandpass input matching and bandpass gain, enabling it to reliably function in all four frequency bands.

[0117] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape, and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A four-band reconfigurable MMIC power amplifier, characterized in that, It includes a reconfigurable input matching network, a driver stage circuit bias network, a reconfigurable inter-stage matching network, an amplifier stage circuit bias network, and a reconfigurable output matching network that are electrically connected together in sequence. The reconfigurable input matching network includes a reconfigurable bridge switched capacitor structure, consisting of capacitors C2, C3, C4, and C5, and switches S1 and S2. Capacitors C2, C3, and S1 are connected end-to-end to form a first loop structure, and capacitors C4, C5, and S2 are connected end-to-end to form a second loop structure. The first loop structure, the second loop structure, and the driver stage circuit bias network are sequentially electrically connected together. The line between capacitor C2 and switch S1 is electrically connected to the line between capacitor C4 and switch S2, and capacitor C6 is electrically connected between capacitors C4 and C5. The reconfigurable inter-stage matching network includes capacitor C10, inductor L5, resistor R4, capacitors C11, C12, C13, C14, C15, and C16, transmission line L6, switch S3, and switch S4. One end of capacitor C10 is electrically connected to the bias network of the driver stage circuit, and the other end of capacitor C10 is electrically connected to inductor L5. One end of resistor R4 is electrically connected to inductor L5, and the other end of resistor R4 is electrically connected to capacitor C11. One end of capacitor C11 is electrically connected to resistor R4, and the other end of capacitor C11 is electrically connected to transmission line L6. Capacitor C12 is connected in parallel with the circuit containing resistor R4 and capacitor C11. One end of capacitor C12 is electrically connected to inductor L5, and the other end of capacitor C12 is electrically connected to inductor L5. A series of capacitors C13 and C14 are connected to the transmission line L6. One end of capacitor C13 is connected between capacitor C11 and the transmission line L6, and the other end of capacitor C13 is connected to capacitor C14. Capacitor C14 is also connected to the ground wire. One end of switch S3 is connected between capacitors C13 and C14, and the other end of switch S3 is connected to the ground wire. A series of capacitors C15 and C16 are connected to the transmission line L6. One end of capacitor C15 is connected between capacitor C11 and the transmission line L6, and the other end of capacitor C15 is connected to capacitor C16. Capacitor C16 is also connected to the ground wire. One end of switch S4 is connected between capacitors C15 and C16, and the other end of switch S4 is connected to the ground wire. The reconfigurable output matching network includes transmission lines L9 and L10, capacitors C20, C21, C22, C23, and C24, and switches S5 and S6. One end of transmission line L9 is electrically connected to the bias network of the amplifier stage circuit, and the other end of transmission line L9 is electrically connected to transmission line L10. One end of capacitor C24 is electrically connected to transmission line L10, and the other end of capacitor C24 is used to electrically connect to the load port. Transmission lines L9, L10, C24, and the load port are connected in series. One end of capacitor C20 is electrically connected between transmission lines L9 and L10, and the other end of capacitor C20 is connected through the switch S5. Switch S5 is electrically connected between capacitors C22 and C21. One end of capacitor C21 is electrically connected between transmission line L10 and capacitor C24, and the other end of capacitor C21 is electrically connected to capacitor C22. One end of capacitor C22 is electrically connected to capacitor C21, and the other end of capacitor C22 is electrically connected to capacitor C23. One end of capacitor C23 is electrically connected to capacitor C22, and the other end of capacitor C23 is electrically connected to the ground wire. Switch S5 is located between capacitors C20 and C22. Switch S6 is connected in parallel to capacitor C23. One end of switch S6 is electrically connected between capacitors C22 and C23, and the other end of switch S6 is electrically connected to the ground wire. The reconfigurable input matching network also includes a capacitor C1 and an inductor L1. One end of the capacitor C1 is electrically connected to the source port, and the other end of the capacitor C1 is electrically connected to the reconfigurable bridge switched capacitor structure. The inductor L1 is set in the bypass of the reconfigurable input matching network. One end of the inductor L1 is electrically connected between the capacitor C1 and the reconfigurable bridge switched capacitor structure, and the other end of the inductor L1 is electrically connected to the ground line. The reconfigurable input matching network also includes an inductor L2 and a capacitor C6. One end of the capacitor C6 is electrically connected to the reconfigurable bridge switched capacitor structure, and the other end of the capacitor C6 is electrically connected to the bias network of the driver stage circuit. One end of the inductor L2 is electrically connected between the capacitor C6 and the reconfigurable bridge switched capacitor structure, and the other end of the inductor L2 is electrically connected to the ground line.

2. The quad-band reconfigurable MMIC power amplifier according to claim 1, characterized in that, The driver stage circuit bias network includes a first transistor and a first gate bias portion. A reconfigurable input matching network is electrically connected to the gate of the first transistor, a reconfigurable inter-stage matching network is electrically connected to the drain of the first transistor, the source of the first transistor is electrically connected to ground, the reconfigurable input matching network is electrically connected to the first gate bias portion, and the first gate bias portion is also electrically connected to the gate of the first transistor. The first gate bias portion is disposed between the reconfigurable input matching network and the gate of the first transistor, and the first gate bias portion adopts a resistor-inductor circuit structure.

3. A four-band reconfigurable MMIC power amplifier according to claim 2, characterized in that, The first gate bias portion includes a resistor R1, an inductor L3, a resistor R2, and a capacitor C7. One end of the resistor R1 is electrically connected between the reconfigurable input matching network and the gate of the first transistor, and the other end of the resistor R1 is electrically connected to the inductor L3. One end of the resistor R2 is electrically connected to the inductor L3, and the other end of the resistor R2 is used to electrically connect to the gate-source voltage source VGS. One end of the capacitor C7 is electrically connected between the inductor L3 and the resistor R2, and the other end of the capacitor C7 is electrically connected to the ground line.

4. A four-band reconfigurable MMIC power amplifier according to claim 1, 2, or 3, characterized in that, The driver stage circuit bias network further includes a first transmission line matching bias structure, which is electrically connected to the drain of the first transistor. The first transmission line matching bias structure includes a transmission line L4, a capacitor C8, a resistor R3, and a capacitor C9. One end of the transmission line L4 is electrically connected to the drain of the first transistor, and the other end of the transmission line L4 is used to electrically connect to the drain-source voltage source VDS. One end of the capacitor C8 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of the capacitor C8 is electrically connected to ground. The resistor R3 and the capacitor C9 are connected in series. One end of the resistor R3 is electrically connected between the transmission line L4 and the drain-source voltage source VDS, and the other end of the resistor R3 is electrically connected to the capacitor C9, which is also electrically connected to ground.

5. A quad-band reconfigurable MMIC power amplifier according to claim 1, characterized in that, The amplification stage circuit bias network includes a second transistor and a second gate bias section. The reconfigurable interstage matching network is electrically connected to the gate of the second transistor, the drain of the second transistor is electrically connected to the reconfigurable output matching network, the source of the second transistor is electrically connected to ground, and the second gate bias section is disposed between the reconfigurable interstage matching network and the second transistor. The second gate bias section adopts a resistor-inductor circuit structure.

6. A quad-band reconfigurable MMIC power amplifier according to claim 5, characterized in that, The second gate bias portion includes a resistor R5, an inductor L7, and a capacitor C17. One end of the resistor R5 is electrically connected between the reconfigurable interstage matching network and the second transistor. One end of the inductor L7 is electrically connected to the resistor R5, and the other end of the inductor L7 is used to electrically connect to the gate-source voltage source VGS. One end of the capacitor C17 is electrically connected between the inductor L7 and the gate-source voltage source VGS, and the other end of the capacitor C17 is electrically connected to the ground line.

7. A method for controlling a four-frequency reconfigurable MMIC power amplifier, characterized in that, A quad-band reconfigurable MMIC power amplifier based on any one of claims 1 to 6, comprising: If switch S1 is short-circuited, switch S2 is short-circuited, switch S3 is open-circuited, switch S4 is open-circuited, switch S5 is short-circuited, and switch S6 is short-circuited, the four-band reconfigurable MMIC power amplifier operates in the first frequency band. If switch S1 is short-circuited, switch S2 is open-circuited, switch S3 is short-circuited, switch S4 is short-circuited, switch S5 is short-circuited, and switch S6 is open-circuited, the four-band reconfigurable MMIC power amplifier operates in the second frequency band. If switch S1 is open, switch S2 is short, switch S3 is short, switch S4 is open, switch S5 is open and switch S6 is short, the four-band reconfigurable MMIC power amplifier operates in the third frequency band. If switch S1 is open, switch S2 is open, switch S3 is open, switch S4 is short-circuited, switch S5 is open, and switch S6 is open, the four-band reconfigurable MMIC power amplifier operates in the fourth frequency band.

8. The control method for a four-frequency reconfigurable MMIC power amplifier according to claim 7, characterized in that, The opening and closing states of switches S1, S2, S3, S4, S5, and S6 are controlled by control signals A and B, specifically including: If control signal A is high and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the first frequency band. If control signal A is high and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-frequency reconfigurable MMIC power amplifier will operate in the second frequency band. If control signal A is low and control signal B is high, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the third frequency band. If control signal A is low and control signal B is low, then switches S1, S2, S3, S4, S5, and S6 will be switched to their respective open / closed states, and the four-band reconfigurable MMIC power amplifier will operate in the fourth frequency band.

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