Overcurrent protection method, device, equipment and storage medium

Abstract

The present invention discloses an overcurrent protection method, device, equipment and storage medium for a BUCK-BOOST circuit. The overcurrent protection method comprises the following steps: obtaining an absolute value U1 of a voltage difference between a first port and a second port, obtaining an absolute value U2 of a voltage difference between a third port and a fourth port, obtaining a current value I_ad passing through an inductor L; and reducing the current of the circuit for overcurrent protection based on the current values ​​I_ad, U1 and U2. Thus, the BUCK-BOOST circuit can be protected from overcurrent.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an overcurrent protection method, device, equipment and storage medium. Background Art

[0002] In high-power bidirectional charging power supply circuits, DC / DC circuits use BUCK-BOOST circuits. BUCK-BOOST circuits can be used for both voltage reduction and voltage increase, but when used, overcurrent may occur.

[0003] Therefore, it becomes an urgent problem to deal with the overcurrent phenomenon in the BUCK-BOOST circuit. Summary of the invention

[0004] In view of this, the main purpose of the present invention is to provide an overcurrent protection method, device, equipment and storage medium.

[0005] To achieve the above object, the technical solution of the present invention is implemented as follows: An overcurrent protection method for a BUCK-BOOST circuit, the BUCK-BOOST circuit includes: an inductor L, a MOS transistor Q1, a MOS transistor Q2, a first port P1, a second port P2, a third port P3, and a fourth port P4; the first port P1 is connected to the first end of the inductor L, the gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L, and the drain of the MOS transistor Q2 is electrically connected to the third port P3; the second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2; in the inductor L, the first and second ports are two different ends; the method includes the following steps: obtaining the absolute value U1 of the voltage difference between the first and second ports, obtaining the absolute value U2 of the voltage difference between the third and fourth ports, obtaining the current value I_ad passing through the inductor L; when it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1≤U2, continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest, where I1_ref0 is the first initial overcurrent threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest; when it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1>U2, continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref, where the overcurrent threshold corresponding to U1 is I1_ref, 0<I1_ref_rest<I1_ref; when it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1>U2, continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest, where I2_ref0 is the second initial overcurrent threshold, and the current hysteresis point corresponding to U2 is I2_ref_rest; when it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1≤U2, continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref, where the overcurrent threshold corresponding to U2 is I2_ref, 0<I2_ref_rest<I2_ref.

[0006] As an improvement of an embodiment of the present invention, the steps of "acquiring the absolute value U1 of the voltage difference between the first and second ports, and acquiring the absolute value U2 of the voltage difference between the third and fourth ports" specifically include: acquiring the absolute value U1 of the voltage difference between the first and second ports at a first time T1, and acquiring the absolute value U2 of the voltage difference between the third and fourth ports at a second time T2; the step of "determining to input direct current at the first and second ports" specifically includes: when the first time T1 is earlier than the second time T2, determining to input direct current at the first and second ports and output direct current at the third and fourth ports; the step of "determining to input direct current at the third and fourth ports" specifically includes: when it is determined that the first time T1 is later than the second time T2, determining to input direct current at the third and fourth ports and output direct current at the first and second ports.

[0007] As an improvement of an embodiment of the present invention, it further includes: a current sensor, and all current sensors are used to measure the current flowing into the inductor L; the step of "the current value I_ad passing through the inductor L" specifically includes: acquiring the current value I_ad passing through the inductor L through the current sensor.

[0008] As an improvement of an embodiment of the present invention, the step of "continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest" specifically includes: continuously reducing the duty cycle of the PWM signal of the MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest; the step of "continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref" specifically includes: continuously reducing the duty cycle of the PWM signal of the MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of the MOS transistor Q2 until the current value passing through the inductor L < I1_ref; the step of "continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest" specifically includes: continuously reducing the duty cycle of the PWM signal of the MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest; the step of "continuously controlling the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref" specifically includes: continuously reducing the duty cycle of the PWM signal of the MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of the MOS transistor Q2 until the current value passing through the inductor L < I2_ref.

[0009] As an improvement to an embodiment of the present invention, I1_ref=F1(U1), I1_ref_rest=F2(U1), and when function F1() and function F2() both input the same value x, F2(x)≤F1(x); I2_ref=G1(U2), I2_ref_rest=G2(U2), and when function G1() and function G2() both input the same value x, G2(x)≤G1(x).

[0010] As an improvement to the embodiment of the present invention, F1(), F2(), G1() and function G2() are all monotonically increasing functions.

[0011] As an improvement to the embodiment of the present invention, F1(), F2(), G1() and function G2() are all step functions.

[0012] An embodiment of the present invention further provides an overcurrent protection device for a BUCK-BOOST circuit. The BUCK-BOOST circuit includes: an inductor L, a MOS transistor Q1, a MOS transistor Q2, a first port P1, a second port P2, a third port P3, and a fourth port P4; the first port P1 is connected to the first end of the inductor L, the gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L, and the drain of the MOS transistor Q2 is electrically connected to the third port P3; the second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2; in the inductor L, the first and second ports are two different ends; it includes the following modules: an information acquisition module, configured to acquire the absolute value U1 of the voltage difference between the first and second ports, acquire the absolute value U2 of the voltage difference between the third and fourth ports, and acquire the current value I_ad passing through the inductor L; a first processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 ≤ U2, where I1_ref0 is the first initial overcurrent threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest; a second processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 > U2, where the overcurrent threshold corresponding to U1 is I1_ref, and 0 < I1_ref_rest < I1_ref; a third processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 > U2, where I2_ref0 is the second initial overcurrent threshold, and the current hysteresis point corresponding to U2 is I2_ref_rest; a fourth processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 ≤ U2, where the overcurrent threshold corresponding to U2 is I2_ref, and 0 < I2_ref_rest < I2_ref.

[0013] An embodiment of the present invention also provides a device for overcurrent protection of a BUCK-BOOST circuit, comprising: a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein the program, when executed by the processor, realizes the overcurrent protection method as described above.

[0014] An embodiment of the present invention also provides a computer-readable and writable storage medium for overcurrent protection of a BUCK-BOOST circuit, which is used for computer storage. The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the overcurrent protection method as described above.

[0015] The overcurrent protection method, device, equipment and storage medium provided by the embodiment of the present invention have the following advantages: The embodiment of the present invention discloses an overcurrent protection method, device, equipment and storage medium for a BUCK-BOOST circuit. The overcurrent protection method includes the following steps: obtaining the absolute value U1 of the voltage difference between the first and second ports, obtaining the absolute value U2 of the voltage difference between the third and fourth ports, and obtaining the current value I_ad passing through the inductor L; based on the current values ​​I_ad, U1 and U2, the current of the circuit is reduced to perform overcurrent protection. Thus, the BUCK-BOOST circuit can be protected from overcurrent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of the BUCK-BOOST circuit in the embodiment;

[0017] Figure 2 Schematic diagram of the flow of the overcurrent protection method for the BUCK-BOOST circuit in the embodiment. DETAILED DESCRIPTION

[0018] The present invention will be described in detail below in conjunction with the embodiments shown in the accompanying drawings. However, the embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on the embodiments are all within the protection scope of the present invention.

[0019] The following description and accompanying drawings fully illustrate the specific embodiments of this article so that those skilled in the art can practice them. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The scope of the embodiments of this article includes the entire scope of the claims, as well as all available equivalents of the claims. Herein, the terms "first", "second", etc. are only used to distinguish one element from another, without requiring or implying any actual relationship or order between these elements. In fact, the first element can also be called the second element, and vice versa. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the structure, device or equipment including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such structure, device or equipment. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the structure, device or equipment including the elements. Each embodiment is described in a progressive manner herein, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other.

[0020] The terms "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. in this document indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing this document and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of this document, unless otherwise specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, it can also be the internal communication of two elements, it can be a direct connection, or it can be an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0021] Embodiment 1 of the present invention provides an overcurrent protection method for a BUCK-BOOST circuit, such as Figure 1As shown, the BUCK-BOOST circuit includes: an inductor L, a MOS transistor Q1, a MOS transistor Q2, a first port P1, a second port P2, a third port P3, and a fourth port P4; the first port P1 is connected to the first end of the inductor L, the gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L, and the drain of the MOS transistor Q2 is electrically connected to the third port P3; the second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2; in the inductor L, the first and second ports are two different ends. Here, as Figure 1 shown, when direct current is input through the first port P1 and the second port P2 and direct current is output through the third port P3 and the fourth port P4, then this circuit is a Boost circuit. When direct current is input through the third port P3 and the fourth port P4 and direct current is output through the first port P1 and the second port P2, then this circuit is a Buck circuit.

[0022] As Figure 2 shown, it includes the following steps:

[0023] Step 201: Obtain the absolute value U1 of the voltage difference between the first and second ports, obtain the absolute value U2 of the voltage difference between the third and fourth ports, and obtain the current value I_ad passing through the inductor L; here, a voltage sensor can be provided between the first and second ports, so that the voltage difference U1 between the first and second ports can be obtained; similarly, a voltage sensor can be provided between the second and third ports, so that the voltage difference U2 between the second and third ports can be obtained; it can be understood that U1≥0 and U2≥0.

[0024] Step 202: When it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1≤U2, continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest, where I1_ref0 is the first initial overcurrent threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest;

[0025] Here, MOS is the abbreviation of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the full English name of PWM is: Pulse Width Modulation, and the Chinese name is: Pulse Width Modulation.

[0026] Here, the purpose of reducing the current value passing through the inductor L can be achieved by reducing the duty cycle of the PWM signal of MOS transistor Q1 and the duty cycle of the PWM signal of MOS transistor Q2. In step 201, the current value I_ad passing through the inductor L is obtained. It is necessary to obtain the current value passing through the inductor L in real time and determine whether this current value is less than I1_ref_rest. Optionally, the current value passing through the inductor L is obtained every preset time.

[0027] Here, I1_ref0 is the first initial overcurrent threshold value, that is, when I_ad≥I1_ref0, it means that the circuit is overcurrent and overcurrent protection processing needs to be performed. When the first and second ports are input direct current and the third and fourth ports output direct current, this current is a Boost circuit. Therefore, it is normal that U1≤U2. Therefore, the current value of the inductor L < I1_ref_rest can be allowed, which helps the recovery of the circuit.

[0028] Step 203: When it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1>U2, continuously control the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I1_ref, where the overcurrent threshold value corresponding to U1 is I1_ref, 0 < I1_ref_rest < I1_ref. Here, the purpose of reducing the current value passing through the inductor L can be achieved by reducing the duty cycle of the PWM signal of MOS transistor Q1 and the duty cycle of the PWM signal of MOS transistor Q2. In step 201, the current value I_ad passing through the inductor L is obtained. It is necessary to obtain the current value passing through the inductor L in real time and determine whether this current value is less than I1_ref. Optionally, the current value passing through the inductor L is obtained every preset time.

[0029] Here, I1_ref0 is the first initial overcurrent threshold value, that is, when I_ad≥I1_ref0, it means that the circuit is overcurrent and overcurrent protection processing needs to be performed. When the first and second ports are input direct current and the third and fourth ports output direct current, this current is a Boost circuit. Therefore, it is abnormal that U1>U2. Therefore, the current value of the inductor L < I1_ref can be allowed.

[0030] Step 204: When it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1>U2, continuously control the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest, where I2_ref0 is the second initial overcurrent threshold value and the current hysteresis point corresponding to U2 is I2_ref_rest;

[0031] Here, the purpose of reducing the current value passing through the inductor L can be achieved by reducing the duty cycle of the PWM signal of MOS transistor Q1 and the duty cycle of the PWM signal of MOS transistor Q2; in step 201, the current value I_ad passing through the inductor L will be obtained. It is necessary to obtain the current value passing through the inductor L in real time and determine whether this current value is less than I2_ref. Optionally, the current value passing through the inductor L is obtained every preset time.

[0032] Here, I2_ref0 is the second initial overcurrent threshold value, that is, when I_ad≥I2_ref0, it means that the circuit is overcurrent and overcurrent protection processing needs to be carried out. When the third and fourth ports are input with direct current and the first and second ports output direct current, this current is a BUCK circuit. Therefore, it is normal that U1>U2. Therefore, the current value of the inductor L can be <I2_ref_rest, which helps the recovery of this circuit.

[0033] Step 205: When it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1≤U2, continuously control the PWM signal of MOS transistor Q1 and the PWM signal of MOS transistor Q2 until the current value passing through the inductor L <I2_ref, where the overcurrent threshold value corresponding to U2 is I2_ref, and 0<I2_ref_rest<I2_ref.

[0034] Here, the purpose of reducing the current value passing through the inductor L can be achieved by reducing the duty cycle of the PWM signal of MOS transistor Q1 and the duty cycle of the PWM signal of MOS transistor Q2; in step 201, the current value I_ad passing through the inductor L will be obtained. It is necessary to obtain the current value passing through the inductor L in real time and determine whether this current value is less than I2_ref_rest. Optionally, the current value passing through the inductor L is obtained every preset time.

[0035] Here, I2_ref0 is the second initial overcurrent threshold value, that is, when I_ad≥I2_ref0, it means that the circuit is overcurrent and overcurrent protection processing needs to be carried out. When the third and fourth ports are input with direct current and the first and second ports output direct current, this current is a BUCK circuit. Therefore, it is abnormal that U1≤U2. Therefore, the current value of the inductor L can be <I2_ref_rest.

[0036] In this embodiment, the "obtaining the absolute value U1 of the voltage difference between the first and second ports and obtaining the absolute value U2 of the voltage difference between the third and fourth ports" specifically includes: obtaining the absolute value U1 of the voltage difference between the first and second ports at the first time T1, and obtaining the absolute value U2 of the voltage difference between the third and fourth ports at the second time T2;

[0037] The "determining to input direct current at the first and second ports" specifically includes: when the first time T1 is earlier than the second time T2, it is determined to input direct current at the first and second ports and output direct current at the third and fourth ports; here, when direct current is input at the first and second ports, it takes some time to obtain a voltage difference at the third and fourth ports.

[0038] The "determining to input direct current at the third and fourth ports" specifically includes: when it is determined that the first time T1 is later than the second time T2, it is determined to input direct current at the third and fourth ports and output direct current at the first and second ports. Here, when direct current is input at the third and fourth ports, it takes some time to obtain a voltage difference at the first and second ports.

[0039] In this embodiment, it further includes: current sensors, and all current sensors are used to measure the current flowing into the inductor L; the "current value I_ad passing through the inductor L" specifically includes: obtaining the current value I_ad passing through the inductor L through the current sensors.

[0040] In this embodiment, the "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest" specifically includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest;

[0041] The "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I1_ref" specifically includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I1_ref;

[0042] The "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest" specifically includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest;

[0043] The "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I2_ref" specifically includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I2_ref.

[0044] In this embodiment, I1_ref = F1(U1), I1_ref_rest = F2(U1), and when the functions F1() and F2() are both input with the same value x, F2(x) ≤ F1(x).

[0045] I2_ref = G1(U2), I2_ref_rest = G2(U2), and when the functions G1() and G2() are both input with the same value x, G2(x) ≤ G1(x).

[0046] In this embodiment, F1(), F2(), G1(), and the function G2() are all monotonically increasing functions.

[0047] In this embodiment, F1(), F2(), G1(), and the function G2() are all step functions.

[0048] Optionally, the domains of F1(), F2(), G1(), and the function G2() can be divided into several intervals, and each interval corresponds to the same output value. They are all step functions.

[0049] Embodiment 2 of the present invention provides an overcurrent protection device for a BUCK - BOOST circuit. The BUCK - BOOST circuit includes: an inductor L, a MOS transistor Q1, a MOS transistor Q2, a first port P1, a second port P2, a third port P3, and a fourth port P4; the first port P1 is connected to the first end of the inductor L, the gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L, and the drain of the MOS transistor Q2 is electrically connected to the third port P3; the second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2; in the inductor L, the first and second ports are two different ends; it includes the following modules:

[0050] An information acquisition module, configured to acquire the absolute value U1 of the voltage difference between the first and second ports, acquire the absolute value U2 of the voltage difference between the third and fourth ports, and acquire the current value I_ad passing through the inductor L.

[0051] A first processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 ≤ U2, where I1_ref0 is the first initial over - current threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest.

[0052] A second processing module, configured to continuously control the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through inductor L < I1_ref when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 > U2, where the overcurrent threshold corresponding to U1 is I1_ref, and 0 < I1_ref_rest < I1_ref;

[0053] A third processing module, configured to continuously control the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through inductor L < I2_ref_rest when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 > U2, where I2_ref0 is the second initial overcurrent threshold, and the current hysteresis point corresponding to U2 is I2_ref_rest;

[0054] A fourth processing module, configured to continuously control the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through inductor L < I2_ref when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 ≤ U2, where the overcurrent threshold corresponding to U2 is I2_ref, and 0 < I2_ref_rest < I2_ref.

[0055] Embodiment 3 of the present invention provides a device for overcurrent protection of a BUCK - BOOST circuit, including: a memory, a processor, a program stored on the memory and executable on the processor, and a data bus for realizing connection communication between the processor and the memory. When the program is executed by the processor, it implements the overcurrent protection method in Embodiment 1.

[0056] Embodiment 4 of the present invention provides a computer - readable and writable storage medium for overcurrent protection of a BUCK - BOOST circuit, used for computer storage. The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the overcurrent protection method in Embodiment 1.

[0057] It should be noted that although the above - mentioned steps are described in a specific order, it does not mean that the steps must be executed in the above - mentioned specific order. In fact, some of these steps can be executed concurrently or even the order can be changed as long as the required functions can be achieved.

[0058] The present invention can be a system, a method, and / or a computer program product. The computer program product can include a readable storage medium having computer - readable program instructions thereon for causing a processor to implement various aspects of the present invention.

[0059] The readable storage medium can be a tangible device that holds and stores instructions used by the instruction execution device. The readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0060] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An overcurrent protection method for a BUCK-BOOST circuit, the BUCK-BOOST circuit comprising: Inductor L, MOS transistor Q1, MOS transistor Q2, first port P1, second port P2, third port P3 and fourth port P4; The first port P1 is connected to the first end of the inductor L. The gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L. The drain of the MOS transistor Q2 is electrically connected to the third port P3. The second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2. In the inductor L, the first and second ports are two different ends. It is characterized by including the following steps: Obtain the absolute value U1 of the voltage difference between the first and second ports, obtain the absolute value U2 of the voltage difference between the third and fourth ports, and obtain the current value I_ad passing through the inductor L; When it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1≤U2, continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest, where I1_ref0 is the first initial overcurrent threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest; When it is determined that direct current is input at the first and second ports, and I_ad≥I1_ref0, and U1>U2, continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref, where the overcurrent threshold corresponding to U1 is I1_ref, and 0 < I1_ref_rest < I1_ref; When it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1>U2, continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest, where I2_ref0 is the second initial overcurrent threshold, and the current hysteresis point corresponding to U2 is I2_ref_rest; When it is determined that direct current is input at the third and fourth ports, and I_ad≥I2_ref0, and U1≤U2, continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref, where the overcurrent threshold corresponding to U2 is I2_ref, and 0 < I2_ref_rest < I2_ref.

2. The overcurrent protection method according to claim 1, characterized in that The "obtain the absolute value U1 of the voltage difference between the first and second ports, obtain the absolute value U2 of the voltage difference between the third and fourth ports" specifically includes: obtaining the absolute value U1 of the voltage difference between the first and second ports at the first time T1, and obtaining the absolute value U2 of the voltage difference between the third and fourth ports at the second time T2; The "determine that direct current is input at the first and second ports" specifically includes: when the first time T1 is earlier than the second time T2, it is determined that direct current is input at the first and second ports, and direct current is output at the third and fourth ports; The specific operation of "determining to input direct current at the third and fourth ports" includes: when it is determined that the first time T1 is later than the second time T2, then it is determined to input direct current at the third and fourth ports and output direct current at the first and second ports.

3. The overcurrent protection method according to claim 1, characterized in that: It further includes: Current sensors, all of which are used to measure the current flowing into the inductor L; The specific operation of "the current value I_ad passing through the inductor L" includes: obtaining the current value I_ad passing through the inductor L through the current sensor.

4. The overcurrent protection method according to claim 1, characterized in that The specific operation of "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest" includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest; The specific operation of "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I1_ref" includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I1_ref; The specific operation of "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest" includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest; The specific operation of "continuously controlling the PWM signals of MOS transistor Q1 and MOS transistor Q2 until the current value passing through the inductor L < I2_ref" includes: continuously reducing the duty cycle of the PWM signal of MOS transistor Q1 and continuously reducing the duty cycle of the PWM signal of MOS transistor Q2 until the current value passing through the inductor L < I2_ref.

5. The overcurrent protection method according to claim 1, characterized in that I1_ref = F1(U1), I1_ref_rest = F2(U1), and when both the function F1() and the function F2() input the same value x, F2(x) ≤ F1(x); I2_ref = G1(U2), I2_ref_rest = G2(U2), and when both the function G1() and the function G2() input the same value x, G2(x) ≤ G1(x).

6. The overcurrent protection method according to claim 5, characterized in that F1(), F2(), G1() and the function G2() are all monotonically increasing functions.

7. The overcurrent protection method according to claim 6, characterized in that F1(), F2(), G1() and the function G2() are all step functions.

8. An overcurrent protection device for a BUCK-BOOST circuit, the BUCK-BOOST circuit comprising: Inductor L, MOS transistor Q1, MOS transistor Q2, first port P1, second port P2, third port P3 and fourth port P4; The first port P1 is connected to the first end of the inductor L. The gates of the MOS transistor Q1 and the MOS transistor Q2 are both electrically connected to the second end of the inductor L. The drain of the MOS transistor Q2 is electrically connected to the third port P3. The second port P2 and the fourth port P4 are both electrically connected to the drain of the MOS transistor Q2. In the inductor L, the first and second ports are two different ends. It is characterized by including the following modules: An information acquisition module, configured to acquire the absolute value U1 of the voltage difference between the first and second ports, acquire the absolute value U2 of the voltage difference between the third and fourth ports, and acquire the current value I_ad passing through the inductor L. A first processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref_rest when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 ≤ U2, where I1_ref0 is the first initial overcurrent threshold, and the current hysteresis point corresponding to U1 is I1_ref_rest. A second processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I1_ref when it is determined that direct current is input at the first and second ports, and I_ad ≥ I1_ref0, and U1 > U2, where the overcurrent threshold corresponding to U1 is I1_ref, and 0 < I1_ref_rest < I1_ref. A third processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref_rest when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 > U2, where I2_ref0 is the second initial overcurrent threshold, and the current hysteresis point corresponding to U2 is I2_ref_rest. A fourth processing module, configured to continuously control the PWM signals of the MOS transistor Q1 and the MOS transistor Q2 until the current value passing through the inductor L < I2_ref when it is determined that direct current is input at the third and fourth ports, and I_ad ≥ I2_ref0, and U1 ≤ U2, where the overcurrent threshold corresponding to U2 is I2_ref, and 0 < I2_ref_rest < I2_ref.

9. A device for overcurrent protection of a BUCK-BOOST circuit, characterized in that: Including: A memory, a processor, a program stored on the memory and executable on the processor, and a data bus for realizing the connection and communication between the processor and the memory. When the program is executed by the processor, it realizes the overcurrent protection method according to any one of claims 1-7.

10. A computer readable and writable storage medium for overcurrent protection of a BUCK-BOOST circuit, used for computer storage, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to realize the overcurrent protection method according to any one of claims 1-7.

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