A circuit fault self-checking method, device and controller

Abstract

The application provides a circuit fault self-checking method, device and controller. The method mainly comprises the following steps: after one-time power-on, a first control unit and a second control unit are configured; the first control unit and the second control unit correspond to each other and mutually monitor circuit abnormalities; after two-time power-on, the first control unit completes one-time self-checking, and according to a one-time self-checking result, a fault mechanism or a normal mechanism is selected to start; only when the normal mechanism, the second control unit completes two-time self-checking, and according to a two-time self-checking result, normal output or disconnection of a power supply is controlled. In the application, the first control unit not only manages and provides power supply for the second control unit, but also mutually monitors the second control unit, so that the functional safety of the power supply system is ensured, and the stability and reliability of the power supply system are jointly constructed through multiple self-checking and mutual checking of the first control unit and the second control unit.

Description

Technical Field

[0001] This application belongs to the field of circuit fault self-testing technology, and particularly relates to a circuit fault self-testing method, device and controller. Background Technology

[0002] Power management ICs are increasingly used in automotive electronic design. Every microcontroller (MCU) has a corresponding power management IC to supply power and manage and monitor the power. However, since the power rail output of the power management IC (PMU) is limited, even though the output power is managed, it is also necessary to design to maximize resources and reliability. In the increasingly complex design of automotive electronic products, it is important to improve the rationality and reliability of power design. When a circuit fails, it is difficult for on-site personnel to determine the cause of the failure without the help of professional personnel, resulting in high system maintenance costs. Summary of the Invention

[0003] To address the shortcomings of the prior art, this application provides a circuit fault self-testing method, device, and controller. In this method, the first control unit not only manages the power supply of the second control unit but also monitors the second control unit. Through multiple self-tests and mutual tests between the first and second control units, the functional safety of the power system is ensured, the stability of the power system is improved, and the maintenance cost of the system is reduced.

[0004] To achieve the above objectives, this application provides a circuit fault self-testing method, comprising:

[0005] After power-on, the first control unit and the second control unit are configured; wherein the first control unit and the second control unit correspond one-to-one and monitor each other for circuit abnormalities.

[0006] After the second power-on, the first control unit completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result; only when the normal mechanism is activated, the second control unit completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result.

[0007] Before configuring the first control unit and the second control unit, the method further includes performing a circuit self-test on the first control unit.

[0008] In this application, the primary circuit self-test specifically includes:

[0009] When the result of the primary circuit self-test is normal, the second control unit is activated.

[0010] If the result of the first circuit self-test is abnormal, repeat the first circuit self-test. If the result of the first circuit self-test is still abnormal, do not start the second control unit.

[0011] In this application, the configuration of the first control unit and the second control unit specifically includes:

[0012] After the second control unit is started, the second control unit configures the first control unit through a preset serial external device interface.

[0013] In this application, the first control unit and the second control unit can monitor each other after being configured.

[0014] In this application, the PMU power management module and the MCU control module establish a safety function configuration through the SPI or IIC interface. After configuration, the system will enter a sleep state. After a preset time, the PMU power management module will perform a self-test after the system is woken up again.

[0015] In this application, the self-test includes at least detecting the system power status of the first control unit.

[0016] Furthermore, the system power status includes normal status, first-level fault status, and second-level fault status.

[0017] In this application, the first self-test result is obtained based on the system power status.

[0018] In this application, the fault mechanism includes at least a primary fault mechanism and a secondary fault mechanism.

[0019] The first-level fault mechanism includes: when a self-test result indicates that the system power state is in a first-level fault state, the second control unit receives a preset instruction from the first control unit through a preset serial external device interface, and reads and records the current fault information.

[0020] The secondary fault mechanism includes: when a self-test result indicates that the system power status is in a secondary fault state, restarting the system power of the first control unit; if the system power status is still in a secondary fault state after restarting, shutting down the system power of the first control unit; the number of times the system power of the first control unit is restarted is at least once.

[0021] In this application, when the system power state is in a first-level fault state, the second control unit reads and records the current fault information, and the power system continues to operate. The first-level fault does not cause the power system to fail to operate.

[0022] In this application, the normal mechanism is activated when the self-test result is normal.

[0023] In this application, the secondary self-test includes at least detecting the signal status of the second control unit and / or the system power status of the second control unit.

[0024] The signal status includes a normal signal status and a normal signal status; the system power status of the second control unit includes a normal system power status and a normal system power status.

[0025] The secondary self-test result is obtained based on the signal status of the second control unit and / or the system power status of the second control unit.

[0026] Specifically, the detection of the system power status of the second control unit is initiated only when the signal status is in a normal state.

[0027] In this application, the step of controlling the normal output or disconnection of the power supply based on the secondary self-test result includes:

[0028] When the signal state is in an abnormal state, the first controller unit receives the preset level signal output by the second control unit through the preset serial external device interface, and then outputs a preset reset command to the second control unit to reset the second control unit.

[0029] When the result of the secondary self-test is that the signal status is in a normal state and the system power status of the second control unit is in a normal state, the system power of the second control unit is controlled to output normally.

[0030] When the result of the secondary self-test is that the signal status is in a normal state and the system power status of the second control unit is in an abnormal state, the system power is restarted. If the system power status of the second control unit is still in an abnormal state after restarting, the system power of the first control unit is shut down. The number of times the system power is restarted is at least once.

[0031] To achieve the above objectives, this application also provides a circuit fault self-testing device, comprising:

[0032] The system comprises a first control module, a second control module, and a fault self-testing module; the fault self-testing module includes a first fault self-testing module and a second fault self-testing module.

[0033] The first control module and the second control module are configured by connecting through a preset serial external device interface; wherein, the first control unit and the second control unit correspond one-to-one and perform circuit anomaly monitoring on each other.

[0034] The first fault self-test module is used for at least one circuit self-test and one self-test of the first control module.

[0035] The second fault self-test module is used for the second self-test of the second control module.

[0036] When the first control module performs a circuit self-test and finds it to be normal, the second control module is started. After the second power-on, the first control module completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result. Only when the normal mechanism is in use, the second control module completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result.

[0037] To achieve the above objectives, this application also provides a circuit fault self-test controller, comprising:

[0038] The system consists of a first controller, a second controller, and a fault self-test circuit.

[0039] The first controller and the second controller are respectively connected to the fault self-test circuit and are configured to connect through the preset serial external device interface of the fault self-test circuit. When the first controller self-tests normally, the second controller is started. The first controller and the second controller correspond one-to-one and monitor each other for circuit abnormalities.

[0040] After the first controller completes a self-test, it initiates a fault mechanism or a normal mechanism based on the self-test result. Only when the normal mechanism is activated, the second controller completes a second self-test and controls the normal output or disconnection of the power supply based on the second self-test result.

[0041] Compared with the prior art, the advantages of this application are as follows:

[0042] This application proposes a circuit fault self-testing method, device, and controller. The method mainly achieves the following:

[0043] 1. The first control unit and the second control unit are configured to start the second controller when the first controller self-tests normally. The first controller and the second controller correspond one-to-one and monitor each other for circuit abnormalities, which ensures the functional safety of the power system and improves the stability of the power system.

[0044] 2. The self-test of the first control unit, the self-test of the second control unit, and the mutual test between the first control unit and the second control unit after configuration enable circuit fault self-testing without the need for external testing equipment, timely protection of the power supply circuit, and feedback and storage of fault information, thereby improving the rationality and reliability of power supply design in electronic products and greatly reducing production costs. Attached Figure Description

[0045] Figure 1 This is an overall flowchart of a circuit fault self-testing method in one embodiment of this application.

[0046] Figure 2 This is a flowchart illustrating the power-on configuration of a circuit fault self-testing method according to an embodiment of this application.

[0047] Figure 3 This is a flowchart of the self-test process of the first control unit during secondary power-on of a circuit fault self-test method according to an embodiment of this application.

[0048] Figure 4 This is a flowchart of the self-test process of the second control unit during secondary power-on of a circuit fault self-test method according to an embodiment of this application.

[0049] Figure 5 This is a schematic diagram of the structure of a circuit fault self-testing device in one embodiment of this application.

[0050] Figure 6 This is a schematic diagram of the structure of a circuit fault self-test controller in one embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0052] Example 1:

[0053] As attached Figure 1 As shown, in order to solve the above-mentioned technical problems, this application provides a circuit fault self-testing method, including:

[0054] After power-on, the first control unit and the second control unit are configured; wherein the first control unit and the second control unit correspond one-to-one and monitor each other for circuit abnormalities.

[0055] After the second power-on, the first control unit completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result; only when the normal mechanism is activated, the second control unit completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result.

[0056] Preferably, the first control unit can be a PMU power management unit, and the second control unit can be an MCU control unit, but neither is limited to these.

[0057] Before configuring the PMU power management unit and the MCU control unit, a circuit self-test of the PMU power management unit is also included.

[0058] In this application, the primary circuit self-test specifically includes:

[0059] When the circuit self-test result is normal, the MCU control unit is activated.

[0060] If the result of a circuit self-test is abnormal, repeat the circuit self-test. If the result of the circuit self-test is still abnormal, do not start the MCU control unit. At this time, turn off the output of the PMU power management unit.

[0061] Preferably, the number of times the circuit self-test is repeated can be set to any parameter, such as 6, 10 or 12, etc., and is not limited to this.

[0062] As attached Figure 2 As shown, in this application, the PMU power management unit and MCU control unit are configured as follows:

[0063] After the MCU control unit is started, it configures the PMU power management unit through a preset serial external device interface.

[0064] Preferably, the preset serial external device interface can be an SPI or an IIC interface for transmitting security function configuration data and information, but is not limited to these.

[0065] Preferably, the PMU power management module and the MCU control module establish a safety function configuration through the SPI or IIC interface. After configuration, the system will enter a sleep state. After a preset time, such as 10 minutes, the PMU power management module will perform a self-test after the system is woken up again.

[0066] As attached Figure 3 As shown in this application, a self-test includes at least detecting the system power status of the first control unit.

[0067] Furthermore, the system power status includes normal status, first-level fault status, and second-level fault status.

[0068] Preferably, a first-level fault condition may be that the level signal output of a certain pin is unstable. The abnormal function of the pin will not cause the power system to malfunction. For example, the level signal output of the LED pin may be abnormal, but this is not the only possibility.

[0069] Preferably, the secondary fault state can be a display screen failure, system crash, interruption of communication pin signals, etc., and is not limited to these.

[0070] In this application, the self-test result is obtained based on the system power status.

[0071] In this application, the fault mechanism includes at least a primary fault mechanism and a secondary fault mechanism.

[0072] The first-level fault mechanism includes: when a self-test result indicates that the system power status is in a first-level fault state, the MCU control unit receives a preset instruction from the PMU power management unit through the SPI interface, reads and records the current fault information.

[0073] Preferably, the preset instruction can be to trigger the INT database, the PMU power management unit outputs the fault information in the INT database to the MCU control unit, and then the MCU control unit reads and records the fault information.

[0074] The level 2 fault mechanism includes: when a self-test result indicates that the system power status is in a level 2 fault state, restart the system power of the PMU power management unit; if the system power status is still in a level 2 fault state after restarting, shut down the system power of the PMU power management unit; the system power of the PMU power management unit is restarted at least once.

[0075] Preferably, the number of restarts can be any parameter, such as 7, 8, 9, and 10, and is not limited to this.

[0076] In this application, the normal mechanism is activated when a self-test result is normal.

[0077] As attached Figure 4 As shown in this application, the secondary self-test includes at least detecting the signal status of the MCU control unit and / or the system power status of the MCU control unit.

[0078] The signal status includes normal signal status and abnormal signal status; the system power status of the MCU control unit includes normal system power status and abnormal system power status.

[0079] The secondary self-test result is obtained based on the signal status of the MCU control unit and / or the system power status of the MCU control unit.

[0080] Specifically, the detection of the system power status of the MCU control unit is only initiated when the signal status is in a normal state.

[0081] In this application, the normal output or disconnection of the power supply is controlled based on the results of the secondary self-test, specifically as follows:

[0082] When the signal status is in an abnormal state, the PMU power management unit receives the preset level signal output by the MCU control unit through the ERR pin interface, and then outputs a preset reset command to the MCU control unit to reset the MCU control unit.

[0083] Preferably, the preset level signal can be an ERR signal, and the preset reset command can be an RST reset signal. When the PMU power management unit receives the ERR signal, it outputs an RST reset signal to the MCU control unit and then performs signal status detection. If the signal status is normal, it performs system power status detection on the MCU control unit.

[0084] When the secondary self-test result shows that the signal status is normal and the system power status of the MCU control unit is normal, the system power of the MCU control unit will output normally.

[0085] When the secondary self-test result shows that the signal status is in a normal state and the system power status of the MCU control unit is in an abnormal state, the system power of the PMU power management unit is restarted. If the system power status of the MCU control unit is still in an abnormal state after restarting, the system power of the PMU power management unit is shut down. The system power is restarted at least once.

[0086] Preferably, a power supply abnormality can manifest as the VMON signal between the MCU control unit and the PMU power management unit being pulled low or having a frequency error, but this is not limited to these examples.

[0087] In summary, Example 1 provides a detailed analysis and illustration of the circuit fault self-testing method proposed in this application. This application achieves circuit fault self-testing without the need for external detection equipment by establishing mutual monitoring between the PMU power management unit and the MCU control unit after configuration, PMU power management unit self-testing, MCU control unit self-testing, and mutual testing. It also promptly protects the power circuit and feeds back and saves fault information, thereby improving the stability of the power system.

[0088] Example 2:

[0089] As attached Figure 4 As shown, in order to solve the above-mentioned technical problems, this application also proposes a circuit fault self-testing device, comprising:

[0090] The system comprises a first control module, a second control module, and a fault self-testing module; the fault self-testing module includes a first fault self-testing module and a second fault self-testing module.

[0091] Preferably, the first control module can be a PMU power management module, and the second control module can be an MCU control module.

[0092] In this application, the first control module and the second control module are configured by connecting through a preset serial external device interface; wherein, the first control unit and the second control unit correspond one-to-one and perform circuit anomaly monitoring on each other.

[0093] Preferably, the preset serial external device interface can be an SPI or an IIC interface, but is not limited to these.

[0094] The first fault self-test module is used for at least one circuit self-test and one self-test of the first control module.

[0095] The second fault self-test module is used for the secondary self-test of the second control module.

[0096] In this application, when the first control module performs a circuit self-test and finds it to be normal, the second control module is started; after the second power-on, the first control module completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result; only when the normal mechanism is in use, the second control module completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result.

[0097] When the PMU power management module's primary circuit self-test is normal, the MCU control module is started. Then, the PMU power management module and the MCU control module establish a safety function configuration through the SPI or IIC interface. After configuration, the system will enter a sleep state. After a preset time, such as 10 minutes, the system will be woken up again. The PMU power management module will perform a self-test. If the primary self-test is normal, the MCU control unit will perform a secondary self-test. If the secondary self-test result is normal, the control power will output normally.

[0098] When the PMU power management module fails the first circuit self-test, it repeats the circuit self-test. If the result of the first circuit self-test is still abnormal, the MCU control unit is not started. At this time, the output of the PMU power management unit is turned off.

[0099] Preferably, the number of times the circuit self-test is repeated can be set to any parameter, such as 8, 9 or 10, etc., and is not limited to this.

[0100] When a self-test result indicates that the system power status is in a first-level fault state, the MCU control unit receives a preset instruction from the PMU power management unit through the SPI interface, reads and records the current fault information.

[0101] When a self-test result indicates that the system power status is in a level 2 fault state, restart the system power of the PMU power management unit. If the system power status is still in a level 2 fault state after restarting, shut down the system power of the PMU power management unit. The system power of the PMU power management unit should be restarted at least once.

[0102] Preferably, the number of restarts can be any parameter, such as 5, 6, 7 and 8, and is not limited to this.

[0103] When the signal status is in an abnormal state, the PMU power management unit receives the preset level signal output by the MCU control unit through the ERR pin interface, and then outputs a preset reset command to the MCU control unit to reset the MCU control unit.

[0104] Preferably, the preset level signal can be an ERR signal, and the preset reset command can be an RST reset signal. When the PMU power management unit receives the ERR signal, it outputs an RST reset signal to the MCU control unit and then performs signal status detection. If the signal status is normal, it performs system power status detection on the MCU control unit.

[0105] When the secondary self-test result shows that the signal status is in a normal state and the system power status of the MCU control unit is in an abnormal state, the system power of the PMU power management unit is restarted. If the system power status of the MCU control unit is still in an abnormal state after restarting, the system power of the PMU power management unit is shut down. The system power is restarted at least once.

[0106] Preferably, a power supply abnormality can manifest as the VMON signal between the MCU control unit and the PMU power management unit being pulled low or having a frequency error, but this is not limited to these examples.

[0107] In summary, Embodiment 2 provides a detailed analysis and illustrative description of the circuit fault self-testing device proposed in this application, facilitating an intuitive understanding of the connections and functions of each unit in the entire device. Combined with the aforementioned circuit fault self-testing method, it can more clearly demonstrate the solution of this invention.

[0108] Example 3:

[0109] As attached Figure 5 As shown, in order to solve the above-mentioned technical problems, this application also proposes a circuit fault self-test controller, including:

[0110] The system consists of a first controller, a second controller, and a fault self-test circuit.

[0111] Preferably, the first controller can be a PMU power management controller, and the second controller can be an MCU controller.

[0112] The first controller and the second controller are respectively connected to the fault self-test circuit and are configured to connect through the preset serial external device interface of the fault self-test circuit. When the first controller self-tests normally, the second controller is started. The first controller and the second controller correspond one-to-one and monitor each other for circuit abnormalities.

[0113] After the first controller completes a self-test, it initiates a fault mechanism or a normal mechanism based on the self-test result. Only when the normal mechanism is activated, the second controller completes a second self-test and controls the normal output or disconnection of the power supply based on the second self-test result.

[0114] Preferably, the fault self-test circuit is mainly manifested in the corresponding connection of each pin in the PMU power management controller and the MCU controller, for example:

[0115] The SPI / IIC pin is used for communication between the PMU power management controller and the MCU controller, transmitting commands and reading information.

[0116] The WD pin in the PMU power management controller is connected to the GPIO pin in the MCU controller and is used as a watchdog timer. When the MCU controller detects an abnormality, it triggers the watchdog timer, and the PMU power management controller is reset after receiving the signal.

[0117] The FS pin in the PMU power management controller is used as the error action pin of the PMU power management controller. When an error occurs, this pin is pulled low.

[0118] The VMON pin in the MCU controller is connected to the FM pin in the PMU power management controller. The signals monitored by the MCU controller are transmitted to the PMU power management controller through this pin.

[0119] The ERR pin is located in both the PMU power management controller and the MCU controller. When the MCU controller detects a fault, it directly outputs the corresponding level signal to the PMU power management controller.

[0120] The INT pin is located in the PMU power management controller and the MCU controller. When the PMU power management controller detects a non-fatal fault, it informs the MCU controller so that the MCU controller can read the non-fatal information.

[0121] The RST pin is located in the PMU power management controller and the MCU controller. In the event of a fault, the PMU power management controller resets the MCU controller.

[0122] In this application, when the computer program is executed by a processor, it implements the various processes of the above-described interface display method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here. The computer-readable storage medium mentioned includes, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0123] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0125] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A circuit fault self-testing method, characterized in that, include: After power-on, the first control unit and the second control unit are configured; wherein the first control unit and the second control unit correspond one-to-one and monitor each other for circuit abnormalities. After the second power-on, the first control unit completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result; only when the normal mechanism is activated, the second control unit completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result. The fault mechanism includes at least a primary fault mechanism and a secondary fault mechanism; The first-level fault mechanism includes: when a self-test result indicates that the system power state is in a first-level fault state, the second control unit receives a preset instruction from the first control unit through a preset serial external device interface, and reads and records the current fault information; The secondary fault mechanism includes: when a self-test result indicates that the system power status is in a secondary fault state, restarting the system power of the first control unit; if the system power status is still in a severe fault state after restarting, shutting down the system power of the first control unit; the number of times the system power of the first control unit is restarted is at least once. The secondary self-test includes at least detecting the signal status of the second control unit and / or the system power status of the second control unit; The signal status includes normal signal status and abnormal signal status; the system power status of the second control unit includes normal system power status and abnormal system power status. The secondary self-test result is obtained based on the signal status of the second control unit and / or the system power status of the second control unit; Specifically, the detection of the system power status of the second control unit is initiated only when the signal status is in a normal state.

2. The circuit fault self-testing method according to claim 1, characterized in that, Before configuring the first control unit and the second control unit, It also includes: performing a circuit self-test on the first control unit; The primary circuit self-test is as follows: When the result of the primary circuit self-test is normal, the second control unit is activated; If the result of the first circuit self-test is abnormal, repeat the first circuit self-test. If the result of the first circuit self-test is still abnormal, do not start the second control unit.

3. The circuit fault self-testing method according to claim 2, characterized in that, The configuration of the first control unit and the second control unit specifically involves: After the second control unit is started, the second control unit configures the first control unit through a preset serial external device interface.

4. The circuit fault self-testing method according to claim 3, characterized in that, The self-test includes at least detecting the system power status of the first control unit; The system power status includes normal status, first-level fault status, and second-level fault status; The self-test result is obtained based on the system power status.

5. A circuit fault self-testing method according to claim 4, characterized in that, When the self-test result is normal, the normal mechanism is activated.

6. A circuit fault self-testing method according to claim 5, characterized in that, The method of controlling the normal output or disconnection of the power supply based on the secondary self-test results includes: When the signal state is in an abnormal state, the first control unit receives the preset level signal output by the second control unit through the preset serial external device interface, and then outputs a preset reset command to the second control unit to reset the second control unit. When the result of the secondary self-test is that the signal status is in a normal state and the system power status of the second control unit is in a normal state, the system power of the second control unit is controlled to output normally. When the result of the secondary self-test is that the signal status is in a normal state and the system power status of the second control unit is in an abnormal state, the system power is restarted. If the system power status of the second control unit is still in an abnormal state after restarting, the system power of the first control unit is shut down. The number of times the system power is restarted is at least once.

7. A circuit fault self-testing device, capable of implementing the circuit fault self-testing method as described in any one of claims 1-6, characterized in that, include: The system comprises a first control module, a second control module, and a fault self-test module. The fault self-test module includes a first fault self-test. Module and second fault self-test module; The first control module and the second control module are connected and configured through a preset serial external device interface; wherein, the first control unit and the second control unit correspond one-to-one and perform circuit anomaly monitoring on each other; The first fault self-test module is used for at least one circuit self-test and one self-test of the first control module; The second fault self-test module is used for the secondary self-test of the second control module; When the first control module performs a circuit self-test and finds it to be normal, the second control module is started. After the second power-on, the first control module completes a self-test and selects to start the fault mechanism or the normal mechanism based on the self-test result. Only when the normal mechanism is in use, the second control module completes a second self-test and controls the normal output of the power supply or disconnects it based on the second self-test result.

8. A circuit fault self-test controller, capable of implementing the circuit fault self-test method as described in any one of claims 1-6, characterized in that, include: First controller, second controller, and fault self-test circuit; The first controller and the second controller are respectively connected to the fault self-test circuit and are configured to connect through the preset serial external device interface of the fault self-test circuit. When the first controller self-tests normally, the second controller is started. The first controller and the second controller correspond one-to-one and monitor each other for circuit abnormalities. After the first controller completes a self-test, it initiates a fault mechanism or a normal mechanism based on the self-test result. Only when the normal mechanism is activated, the second controller completes a second self-test and controls the normal output or disconnection of the power supply based on the second self-test result.

Images