Data access method and apparatus, data storage method and apparatus

Abstract

This disclosure relates to the field of data processing technology, specifically to a data access method and apparatus, a computer-readable storage medium, and an electronic device. The method is applied to a processor, which is connected to a memory expansion module via the CXL protocol. The method includes: receiving a data access request and determining the latency requirement of the data access request; responding when the latency requirement is greater than a latency threshold and determining the access device type corresponding to the data access request; determining the data type based on the access device type; and accessing the memory expansion module based on the data type to obtain the target data. The technical solution of the embodiments of this disclosure improves the efficiency of data acquisition.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and more specifically, to a data access method, a data access device, a data storage method, a data storage device, a computer-readable storage medium, and an electronic device. Background Technology

[0002] With the growth of application computing and data scale, the memory space of traditional single-machine servers is insufficient to meet the needs of businesses with large memory requirements. At the same time, in the era of heterogeneous computing, many acceleration devices, such as GPUs (graphics processing units) and NPUs (neural-network process units), incorporate a lot of their own memory.

[0003] However, heterogeneous devices also bring a lot of memory, and the inability to allocate multiple types of memory in a unified manner and the low efficiency of their use result in low data acquisition efficiency.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a data access method, a data access device, a data storage method, a data storage device, a computer-readable storage medium, and an electronic device, thereby improving the efficiency of data acquisition to at least a certain extent.

[0006] According to a first aspect of this disclosure, a data access method is provided, applied to a processor, wherein the processor and a memory expansion module are connected via the CXL (Compute Express Link) protocol, comprising: receiving a data access request and determining the latency requirement of the data access request; responding that the latency requirement is greater than a latency threshold and determining the access device type corresponding to the data access request; determining the data type according to the access device type; and accessing the memory expansion module according to the data type to obtain target data.

[0007] According to a second aspect of this disclosure, a data storage method is provided, applied to a processor, wherein the processor and a memory expansion module are connected via the CXL protocol, comprising: a request receiving module for receiving a data access request and determining the latency requirement of the data access request; a type determining module for determining the access device type corresponding to the data access request in response to a latency requirement exceeding a latency threshold; and a data acquisition module for determining the data type based on the access device type and accessing the memory expansion module to acquire target data based on the data type.

[0008] According to a third aspect of this disclosure, a data access device is provided, applied to a processor, wherein the processor and a memory expansion module are connected via the CXL protocol. The data access device includes: a request receiving module, configured to receive a data access request and determine the latency requirement of the data access request; a type determining module, configured to determine the access device type corresponding to the data access request in response to a latency requirement exceeding a latency threshold; and a data acquisition module, configured to determine the data type based on the access device type and access the memory expansion module based on the data type to acquire target data.

[0009] According to a fourth aspect of this disclosure, a data access device is provided, applied to a processor, wherein the processor and a memory expansion module are connected via the CXL protocol. The data access device includes: a data receiving module, configured to receive a data storage request and data to be stored, and determine the latency requirement of the data storage request; a data classification module, configured to determine the storage device type corresponding to the data storage request in response to a latency requirement exceeding a latency threshold; and a data storage module, configured to determine the data type according to the storage device type, and store the data to be stored in the memory expansion module according to the data type.

[0010] According to a fifth aspect of this disclosure, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0011] According to a sixth aspect of this disclosure, an electronic device is provided, characterized in that it includes: one or more processors; and a memory for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the method described above.

[0012] One embodiment of this disclosure provides a data access method that configures a processor with a memory expansion module connected using the CXL protocol, thereby increasing the storage space available to the processor. On the other hand, it determines the latency requirement of the data access request, and only accesses the memory expansion module when the latency requirement is greater than a latency threshold. This expands the memory while preventing low data acquisition efficiency due to accessing the memory expansion module. Furthermore, accessing the memory expansion module based on the data type enables the rapid retrieval of accurate data when accessing the memory expansion module, thus improving the efficiency of data acquisition.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] Figure 1 A schematic diagram of an exemplary system architecture to which embodiments of the present disclosure may be applied is shown.

[0016] Figure 2 A flowchart illustrating a data access method in an exemplary embodiment of this disclosure is shown schematically.

[0017] Figure 3 A schematic diagram of another exemplary system architecture to which embodiments of the present disclosure can be applied is shown.

[0018] Figure 4 A schematic diagram of another exemplary system architecture to which embodiments of the present disclosure can be applied is shown.

[0019] Figure 5 A schematic diagram of yet another exemplary system architecture to which embodiments of the present disclosure may be applied is shown.

[0020] Figure 6 A schematic diagram of another exemplary system architecture to which embodiments of the present disclosure may be applied is shown.

[0021] Figure 7 A schematic diagram is shown of a memory expansion unit connection method that can be applied to embodiments of the present disclosure.

[0022] Figure 8 A flowchart illustrating another data access method in an exemplary embodiment of this disclosure is shown schematically.

[0023] Figure 9 A flowchart illustrating a data storage method in an exemplary embodiment of the present disclosure is shown schematically.

[0024] Figure 10 This schematic diagram illustrates the composition of a data access apparatus in an exemplary embodiment of the present disclosure.

[0025] Figure 11 This schematic diagram illustrates the composition of a data storage device in an exemplary embodiment of the present disclosure.

[0026] Figure 12 A schematic diagram of an electronic device to which embodiments of the present disclosure may be applied is shown. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0029] The memory space of a single server is insufficient to meet the needs of services with large memory requirements. At the same time, in the era of heterogeneous computing, many acceleration devices, such as GPUs and NPUs, introduce a lot of their own memory. Heterogeneous devices also bring a lot of memory. Multiple types of memory cannot be uniformly allocated and have low utilization efficiency, resulting in low data acquisition efficiency. In addition, the transfer of memory data will also seriously affect the power consumption of the system.

[0030] In view of the above-mentioned shortcomings, this disclosure provides a data access method. Figure 1 A schematic diagram of a system architecture that can implement the above-described data access method is shown. This system architecture may include a processor 110 and a memory expansion module 120. The memory expansion module 120 is connected to the processor 110 via the CXL protocol. The memory expansion module 120 provides usable storage space for the processor 110 to store data. The processor 110 can write data to and read data from the memory expansion module 120. The processor 110 can receive data access requests and determine the latency requirements of the data access requests; if the latency requirement is greater than a latency threshold, it determines the access device type corresponding to the data access request; it determines the data type based on the access device type; and it accesses the memory expansion module 120 to obtain the target data based on the data type.

[0031] The following is combined with Figure 2 The data access method in this exemplary embodiment will be described. Figure 2 An exemplary flow of the data access method is shown, which may include steps S210 to S230.

[0032] In step S210, a data access request is received, and the delay requirement of the data access request is determined.

[0033] In one exemplary embodiment of this disclosure, the processor can receive a data access request sent by a user through another device, wherein, referring to Figure 3 As shown, the number of processors can be one or more. When there are multiple processors, they can be connected through a CPU interconnect protocol. The CPU (Central Processing Unit) interconnect protocol can be the CXL protocol, the GEN-Z protocol, etc. Different CPU interconnect protocols can be selected according to the model of the processor. In this example implementation, no specific limitation is made.

[0034] All of the aforementioned processors can receive the aforementioned data access request, and upon receiving the request, can parse it to obtain the latency requirement. Specifically, the latency requirement is described as the maximum available time for data retrieval. For example, the maximum available time for data retrieval in the data access request is determined, and this maximum available time is used as the latency requirement.

[0035] For example, if device A sends a data access request to the processor, and the data access request includes the maximum available time for device A to obtain the data, such as 20 milliseconds, then 20 milliseconds can be used as the aforementioned latency requirement.

[0036] It should be noted that the latency requirements in data access requests sent by different devices may be different or the same, and can be customized according to user needs. No specific limitation is made in this example implementation.

[0037] In step S220, if the response delay requirement is greater than the delay threshold, the access device type corresponding to the data access request is determined.

[0038] In this example implementation, the processor is configured with a local memory unit. The processor can first set a delay threshold. The delay threshold can be determined based on the storage space of the local memory unit and the memory expansion module, or it can be set to a fixed value. The delay threshold can be customized according to user needs, and no specific limitation is made in this example implementation.

[0039] After receiving the above latency request, the processor can determine whether the latency request is greater than the above latency threshold. If the latency request is greater than the latency threshold, it indicates that there is sufficient time for data acquisition, and the corresponding data can be obtained from the memory expansion module through the CXL protocol. At this time, the access device type corresponding to the above data access request can be determined.

[0040] Specifically, the above device access types correspond to different data types. Specifically, device access types can include non-volatile and volatile, and the corresponding data types can also include non-volatile and volatile.

[0041] In one example implementation, if the latency requirement is less than or equal to the latency threshold, the processor can directly retrieve data from local memory to satisfy the request for low-latency data retrieval.

[0042] In one exemplary embodiment of this disclosure, reference is made to Figure 4 As shown, the processor is also connected to an accelerator memory pool, which may include memory internally configured in GPUs (graphics processing units), NPUs (neural-network process units), etc.

[0043] In this example implementation, when the latency requirement exceeds the latency threshold, the access address of the data access request can be determined first. If the access address is the memory expansion module, the access device type corresponding to the data access request is determined. If the access address is the accelerator memory pool, the target data is obtained by accessing the accelerator memory pool according to the data access request. The accelerator memory pool can be interconnected with the processor via the CXL protocol, and can uniformly manage the memory of other heterogeneous acceleration devices through CXL, supporting unified memory pooling.

[0044] In step S230, the data type is determined according to the access device type, and the memory expansion module is accessed according to the data type to obtain the target data.

[0045] In this example implementation, after determining the user access device type, the data type corresponding to the data access request can be determined based on the access device type, and then the memory expansion module can be accessed based on the data type to obtain the target data.

[0046] Specifically, the aforementioned data types can include both non-volatile and volatile types. If the data type is non-volatile, the processor can access the SCM memory in the memory expansion module according to the data access request. Specifically, after the processor determines that the aforementioned data type is non-volatile, it can generate a corresponding data acquisition address based on the aforementioned data type and the aforementioned data access request. This data acquisition address is used to access the SCM memory in the memory expansion module to obtain the target data with a non-volatile data type.

[0047] If the processor responds to a data type that is volatile, it can access the DDR memory in the memory expansion module according to the data access request. Specifically, after the processor determines that the data type is volatile, it can generate a corresponding data acquisition address based on the data type and the data access request. This data acquisition address is used to access the DDR memory in the memory expansion module to obtain the target data that is volatile.

[0048] In one exemplary embodiment of this disclosure, reference is made to Figure 5 As shown, the memory expansion module may include at least one memory expansion unit, wherein the memory expansion unit includes a near-memory calculation unit, and the data access request includes an instruction on whether near-memory calculation is required for the extracted data. If the data access request includes a near-memory calculation instruction, then near-memory calculation is performed on the data at the address corresponding to the data access request to obtain the target data.

[0049] It should be noted that the aforementioned near-memory computing unit can be implemented using an FPGA (Field Programmable Gate Array), or a processor such as an MCU or CPU, or it can be customized according to user needs. No specific limitations are made in this example implementation.

[0050] The aforementioned near-memory computation instructions can be commands such as compression and decompression, or they can be customized according to user needs; no specific limitations are imposed in this example implementation. Performing relevant data computations at the near-data end reduces data transmission volume and lowers data transmission power consumption.

[0051] In one example implementation, the memory expansion module includes multiple memory expansion units, as shown below. Figure 6 As shown, any of the above processors can be connected to one of the memory expansion units. Specifically, a common interface can be set on the processor, and a common interface can also be set on the memory expansion unit for the interconnection between the processor and the memory expansion unit.

[0052] Reference Figure 7 As shown, multiple memory expansion units are interconnected. Specifically, they can be interconnected through a CXL / Gen-Z switch (converter) so that the processor can access data within any memory expansion unit.

[0053] The following is combined with Figure 8 The above data access methods are explained in general.

[0054] Reference Figure 8As shown, the processor can first execute step S801 to receive a data access request, then execute step S802 to determine whether the latency requirement is greater than the latency threshold. If not, it executes step S803 to obtain DDR data from the local storage unit. If yes, it executes step S804 to access the memory expansion unit according to the data access request, and executes step S805 to determine whether the access device type of the data access request is non-volatile. If yes, it executes step S806 to access the SCM memory of the memory expansion module. If no, it executes step S807 to access the DDR memory of the memory expansion module. Then, it executes step S808 to determine whether there is a near-memory calculation instruction in the data access request. If yes, it executes step S809 to obtain the target data processed by the near-memory calculation unit. If no, it executes step S810 to directly return the target data.

[0055] In summary, this exemplary embodiment, on the one hand, configures a memory expansion module connected via the CXL protocol for the processor, enhancing the processor's usable storage space. On the other hand, it determines the latency requirements of data access requests, only accessing the memory expansion module when the latency requirement exceeds a latency threshold. This expands memory while preventing low data acquisition efficiency due to accessing the memory expansion module. Furthermore, accessing the memory expansion module based on data type enables rapid and accurate data retrieval, improving data acquisition efficiency. Moreover, when the latency requirement is less than or equal to the latency threshold, data is directly retrieved from local memory, improving memory acquisition efficiency. Furthermore, a near-memory computing unit is set up in the memory expansion unit, performing relevant data calculations near the data end first, thereby reducing data transfer volume and power consumption. Furthermore, it supports unified management of other heterogeneous acceleration device memory via CXL, supporting unified memory pooling.

[0056] Furthermore, this disclosure also provides a data storage method applied to a processor, wherein the processor and the memory expansion module are connected via the CXL protocol, as described above. Figure 9 As shown, it may specifically include steps S910 to S930.

[0057] In step S910, a data storage request and the data to be stored are received, and the delay requirement of the data storage request is determined.

[0058] In one exemplary embodiment of this disclosure, the processor can receive a data storage request and data to be stored sent by a user through another device, wherein, referring to Figure 3As shown, the number of processors can be one or more. When there are multiple processors, they can be connected through a CPU interconnect protocol. The CPU (Central Processing Unit) interconnect protocol can be the CXL protocol, the GEN-Z protocol, etc. Different CPU interconnect protocols can be selected according to the model of the processor. In this example implementation, no specific limitation is made.

[0059] All of the aforementioned processors can receive the data storage request and the data to be stored. Upon receiving the data storage request, they can parse the request to obtain the latency requirement. Specifically, the latency requirement is described as the available time for data retrieval. For example, the maximum available time for data retrieval in the data storage request is determined, and this maximum available time is used as the latency requirement.

[0060] In step S920, if the response latency requirement is greater than the latency threshold, the storage device type corresponding to the data storage request is determined.

[0061] In this example implementation, the processor is configured with a local memory unit. The processor can first set a delay threshold. The delay threshold can be determined based on the storage space of the local memory unit and the memory expansion module, or it can be set to a fixed value. The delay threshold can be customized according to user needs, and no specific limitation is made in this example implementation.

[0062] After receiving the above latency request, the processor can determine whether the latency request is greater than the above latency threshold. If the latency request is greater than the latency threshold, it indicates that there is sufficient time for data storage. The data to be stored can be stored to the memory expansion module through the CXL protocol. At this time, the storage device type corresponding to the above data storage request can be determined.

[0063] Specifically, the above device access types correspond to different data types. Specifically, device access types can include non-volatile and volatile, and the corresponding data types can also include non-volatile and volatile.

[0064] In one example implementation, if the latency requirement is less than or equal to the latency threshold, the processor can directly store the data to be stored in the local memory unit to satisfy the request for low-latency data storage.

[0065] In one exemplary embodiment of this disclosure, reference is made to Figure 5As shown, the processor is also connected to an accelerator memory pool, which may include memory internally configured in GPUs (graphics processing units), NPUs (neural-network process units), etc.

[0066] In this example implementation, when the latency requirement exceeds the latency threshold, the access address of the data storage request can be determined first. If the access address is the memory expansion module, the storage device type corresponding to the data storage request is determined. If the access address is the accelerator memory pool, the data to be stored is stored in the accelerator memory pool according to the data storage request. The accelerator memory pool can be interconnected with the processor via the CXL protocol, and can uniformly manage the memory of other heterogeneous acceleration devices through CXL, supporting unified memory pooling.

[0067] In step S930, the data type is determined according to the storage device type, and the data to be stored is stored in the memory expansion module according to the data type.

[0068] In this example implementation, after determining the type of the user storage device, the data type corresponding to the data storage request can be determined based on the storage device type, and then the data to be stored can be stored in the memory expansion module based on the data type.

[0069] Specifically, the aforementioned data types can include both non-volatile and volatile types. If the data type is non-volatile, the processor can store the data to be stored in the SCM memory in the memory expansion module according to the data storage request. Specifically, after the processor determines that the aforementioned data type is non-volatile, it can generate a corresponding data storage address based on the aforementioned data type and the aforementioned data storage request. This data storage address is used to store the data to be stored in the SCM memory in the memory expansion module.

[0070] If the processor responds to a data type that is volatile, it will store the data to be stored in the DDR memory in the memory expansion module according to the data storage request. Specifically, after the processor determines that the data type is volatile, it can generate a corresponding data storage address based on the data type and the data storage request. This data storage address is used to store the data to be stored in the DDR memory in the memory expansion module.

[0071] In one exemplary embodiment of this disclosure, reference is made to Figure 4As shown, the memory expansion module may include at least one memory expansion unit, wherein the memory expansion unit includes a near-memory calculation unit. The data storage request includes an instruction on whether near-memory calculation is required for the data to be stored. If the data storage request includes a near-memory calculation instruction, the near-memory calculation unit performs near-memory calculation on the data to be stored and then stores it in the memory expansion module.

[0072] It should be noted that the aforementioned near-memory computing unit can be implemented using an FPGA, or a processor such as an MCU or CPU, or it can be customized according to user needs. No specific limitations are made in this example implementation.

[0073] The aforementioned near-memory computation instructions can be commands such as compression and decompression, or they can be customized according to user needs; no specific limitations are imposed in this example implementation. Performing relevant data computations at the near-data end reduces data transmission volume and lowers data transmission power consumption.

[0074] In one example implementation, the memory expansion module includes multiple memory expansion units, as shown below. Figure 6 As shown, any of the above processors can be connected to one of the memory expansion units. Specifically, a common interface can be set on the processor, and a common interface can also be set on the memory expansion unit for the interconnection between the processor and the memory expansion unit.

[0075] Reference Figure 7 As shown, multiple memory expansion units are interconnected. Specifically, they can be interconnected through a CXL / Gen-Z switch (converter) so that the processor can access data within any memory expansion unit.

[0076] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0077] Further reference Figure 10 As shown, this example embodiment also provides a data access device 1000, applied to a processor. The processor and the memory expansion module are connected via the CXL protocol. The data access device 1000 includes a request receiving module 1010, a type determination module 1020, and a data acquisition module 1030. Wherein:

[0078] The request receiving module 1010 can be used to receive data access requests and determine the latency requirements of the data access requests; the type determination module 1020 can be used to respond when the latency requirement is greater than the latency threshold and determine the access device type corresponding to the data access request; the data acquisition module can be used to determine the data type according to the access device type and access the memory expansion module according to the data type to obtain the target data.

[0079] In one example implementation, the type determination module 1020 can be configured to determine the access address of the data access request when the response latency requirement is greater than the latency threshold; the response access address is a memory expansion module, which determines the access device type corresponding to the data access request.

[0080] In one example implementation, the data acquisition module 1030 can be configured to respond to non-volatile data types, for example, to access the SCM memory in the memory expansion module according to a data access request; and to respond to volatile data types, for example, to access the DDR memory in the memory expansion module according to a data access request.

[0081] In one example implementation, the data acquisition module 1030 can be configured to determine whether a near-memory computation instruction exists in the data access request; send the near-memory computation instruction to the near-memory computation unit; and access the memory expansion module according to the data type to obtain the target data processed by the near-memory computation unit. The processor can access any memory expansion unit in the memory expansion module to obtain the target data according to the data access type.

[0082] The data access device 1000 can also be used to access the accelerator memory pool to obtain the target data in response to an access address of the accelerator memory pool.

[0083] The specific details of each module in the above-mentioned device have been described in detail in the method section of the implementation. For any undisclosed details, please refer to the implementation content of the method section, and therefore will not be repeated here.

[0084] Further, further, reference Figure 11 As shown, this example embodiment also provides a data storage device 1100, applied to a processor. The processor and the memory expansion module are connected via the CXL protocol. The data storage device 1100 includes a data receiving module 1110, a data classification module 1120, and a data storage module 1130. Wherein:

[0085] The data storage device 1100 can be used to receive data storage requests and data to be stored, and determine the latency requirements of the data storage requests; the data classification module 1120 can be used to respond when the latency requirements are greater than the latency threshold and determine the storage device type corresponding to the data storage request; the data storage module 1130 can be used to determine the data type according to the storage device type and store the data to be stored in the memory expansion module according to the data type.

[0086] The specific details of each module in the above-mentioned device have been described in detail in the method section of the implementation. For any undisclosed details, please refer to the implementation content of the method section, and therefore will not be repeated here.

[0087] The following is based on Figure 12 Taking the mobile terminal 1200 as an example, the construction of this electronic device will be described by way of example. Those skilled in the art will understand that, apart from components specifically designed for mobile purposes, Figure 12 The structure can also be applied to fixed types of equipment.

[0088] like Figure 12 As shown, the mobile terminal 1200 may specifically include: a processor 1201, a memory 1202, a bus 1203, a mobile communication module 1204, an antenna 1, a wireless communication module 1205, an antenna 2, a display screen 1206, a camera module 1207, an audio module 1208, a power module 1209, and a sensor module 1210.

[0089] The processor 1201 may include one or more processing units, such as an AP (Application Processor), a modem processor, a GPU (Graphics Processing Unit), an ISP (Image Signal Processor), a controller, an encoder, a decoder, a DSP (Digital Signal Processor), a baseband processor, and / or an NPU (Neural-Network Processing Unit).

[0090] The processor 1201 can be connected to the memory 1202 or other components via the bus 1203.

[0091] The memory 1202 can be used to store computer executable program code, which includes instructions. The processor 1201 executes various functional applications and data processing of the mobile terminal 1200 by running the instructions stored in the memory 1202. The memory 1202 can also store application data, such as images, videos, and other files.

[0092] The communication function of mobile terminal 1200 can be implemented through mobile communication module 1204, antenna 1, wireless communication module 1205, antenna 2, modem processor, and baseband processor. Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Mobile communication module 1204 can provide 2G, 3G, 4G, and 5G mobile communication solutions for mobile terminal 1200. Wireless communication module 1205 can provide wireless communication solutions such as wireless LAN, Bluetooth, and near-field communication for mobile terminal 1200.

[0093] The display screen 1206 is used to implement display functions, such as displaying the user interface, images, and videos. The camera module 1207 is used to implement shooting functions, such as capturing images and videos. The audio module 1208 is used to implement audio functions, such as playing audio and capturing voice. The power module 1209 is used to implement power management functions, such as charging the battery, powering the device, and monitoring the battery status. The sensor module 1210 may include a depth sensor 12101, a pressure sensor 12102, a gyroscope sensor 12103, a barometric pressure sensor 12104, etc., to implement corresponding sensing and detection functions.

[0094] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0095] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0096] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0097] In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0098] Furthermore, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0099] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0100] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data access method applied to a processor, characterized in that, The processor and memory expansion module are connected via the CXL protocol, and the processor includes a local memory unit. The method includes: Receive a data access request and determine the latency requirement of the data access request; When the latency requirement is less than or equal to the latency threshold, the local memory unit is accessed to obtain the target data; If the latency requirement is greater than the latency threshold, determine the access device type corresponding to the data access request; The data type is determined according to the access device type, and the memory expansion module is accessed according to the data type to obtain the target data; the data type includes non-volatile and volatile, and accessing the memory expansion module according to the data type includes: in response to the data type being non-volatile, accessing the SCM memory in the memory expansion module according to the data access request; in response to the data type being volatile, accessing the DDR memory in the memory expansion module according to the data access request.

2. The method according to claim 1, characterized in that, The memory expansion module includes a near-memory computing unit, and accessing the memory expansion module according to the data type to obtain the target data includes: Determine whether the data access request contains a near-memory computation instruction; The near-memory calculation instruction is sent to the near-memory calculation unit, and the memory expansion module is accessed according to the data type to obtain the target data processed by the near-memory calculation unit.

3. The method according to claim 1, characterized in that, When the response delay requirement is greater than the delay threshold, determining the access device type corresponding to the data access request includes: If the delay requirement is greater than the delay threshold, determine the access address of the data access request; In response to the access address being the memory expansion module, the access device type corresponding to the data access request is determined.

4. The method according to claim 3, characterized in that, The processor is connected to the accelerator memory pool, and the method further includes: If the access address is an accelerator memory pool, then the accelerator memory pool is accessed according to the data access request to obtain the target data.

5. The method according to claim 1, characterized in that, The memory expansion module includes multiple interconnected memory expansion units, and the processor is connected to one of the memory expansion units; accessing the memory expansion module to obtain target data according to the data type includes: The processor can access any memory expansion unit in the memory expansion module to obtain target data according to the data access type.

6. A data storage method applied to a processor, characterized in that, The processor and memory expansion module are connected via the CXL protocol, and the processor includes a local memory unit. The method includes: Receive data storage request and data to be stored, and determine the latency requirement of the data storage request; When the latency requirement is less than or equal to the latency threshold, the data to be stored is stored in the local memory unit. In response to the latency requirement being greater than the latency threshold, the storage device type corresponding to the data storage request is determined; The data type is determined according to the storage device type, and the data to be stored is stored in the memory expansion module according to the data type; the data type includes non-volatile and volatile, and storing the data to be stored in the memory expansion module according to the data type includes: in response to the data type being non-volatile, storing the data to be stored in the SCM memory in the memory expansion module; in response to the data type being volatile, storing the data to be stored in the DDR memory in the memory expansion module.

7. A data access device applied to a processor, characterized in that, The processor and memory expansion module are connected via the CXL protocol, and the processor includes a local memory unit. The data access device includes: A request receiving module is used to receive data access requests and determine the delay requirements of the data access requests; The data acquisition module is used to access the local memory unit to obtain target data when the delay requirement is less than or equal to the delay threshold. The type determination module is used to determine the access device type corresponding to the data access request in response to the delay requirement being greater than the delay threshold. A data acquisition module is used to determine the data type according to the access device type, and access the memory expansion module to obtain target data according to the data type; the data type includes non-volatile and volatile, and accessing the memory expansion module according to the data type includes: in response to the data type being non-volatile, accessing the SCM memory in the memory expansion module according to the data access request; in response to the data type being volatile, accessing the DDR memory in the memory expansion module according to the data access request.

8. A data storage device applied to a processor, characterized in that, The processor and memory expansion module are connected via the CXL protocol, and the processor includes a local memory unit. The data storage device includes: A data receiving module is used to receive data storage requests and data to be stored, and to determine the delay requirements of the data storage requests; The data storage module is used to store the data to be stored in the local memory unit when the latency requirement is less than or equal to the latency threshold. The data classification module is used to determine the storage device type corresponding to the data storage request in response to the latency requirement being greater than the latency threshold. A data storage module is configured to determine the data type based on the storage device type, and store the data to be stored in the memory expansion module according to the data type; the data type includes non-volatile and volatile, and storing the data to be stored in the memory expansion module according to the data type includes: in response to the data type being non-volatile, storing the data to be stored in the SCM memory in the memory expansion module; in response to the data type being volatile, storing the data to be stored in the DDR memory in the memory expansion module.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 6.

10. An electronic device, characterized in that, include: One or more processors; as well as A memory for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the method as described in any one of claims 1 to 6.

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