Bonding method and bonding structure

Abstract

The present disclosure relates to a bonding method and a bonding structure. The bonding method includes the following steps: providing a first wafer and a second wafer, the first wafer including a first dielectric layer and a first conductive layer exposed on the surface of the first dielectric layer, and the second wafer including a second dielectric layer and a second conductive layer exposed on the surface of the second dielectric layer; performing surface treatment on the first wafer and the second wafer to form a first bonding layer covering the first dielectric layer and a first treatment layer covering the first conductive layer, and forming a second bonding layer covering the second dielectric layer and a second treatment layer covering the second conductive layer; removing the first treatment layer and the second treatment layer, and bonding the first bonding layer to the second bonding layer, and bonding the first conductive layer and the second conductive layer. The present disclosure enhances the bonding strength of the bonding structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a bonding method and a bonding structure. Background Art

[0002] The bonding process is a commonly used process technology in the semiconductor manufacturing process. Through the bonding process, multiple wafers can be connected together to form a stacked structure. Hybrid Bond is a process that simultaneously performs bonding between dielectric layers and bonding between metal layers. It is widely used in bonding between wafers and between wafers and chips. Before hybrid bonding, in order to enhance the bonding strength between dielectric layers, it is usually necessary to perform surface treatment on the wafer or chip. Although the surface treatment process can enhance the bonding strength between dielectric layers, it will weaken the bonding strength between metal layers, thereby affecting the performance of the entire bonding structure. After the hybrid bonding process is completed, it is usually necessary to anneal the bonding structure formed by the bonding process to enhance the bonding strength between metal layers. However, the high-temperature annealing process will affect the performance of the device layer in the bonding structure. In particular, as the size of the semiconductor structure continues to shrink, the damage caused by high temperature will be more obvious, which is easy to cause defects inside the bonding structure, affecting the performance of the bonding structure.

[0003] Therefore, how to simultaneously enhance the bonding strength between dielectric layers and the bonding strength between metal layers, thereby improving the performance of the bonding structure, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] Some embodiments of the present disclosure provide a bonding method and a bonding structure for simultaneously enhancing the bonding strength between dielectric layers and the bonding strength between conductive layers, thereby improving the performance of the bonding structure.

[0005] According to some embodiments, the present disclosure provides a bonding method, comprising the following steps:

[0006] Providing a first wafer and a second wafer, wherein the first wafer comprises a first dielectric layer and a first conductive layer exposed on a surface of the first dielectric layer, and the second wafer comprises a second dielectric layer and a second conductive layer exposed on a surface of the second dielectric layer;

[0007] Performing surface treatment on the first wafer and the second wafer to form a first bonding layer covering the first dielectric layer and a first processing layer covering the first conductive layer, and forming a second bonding layer covering the second dielectric layer and a second processing layer covering the second conductive layer;

[0008] Remove the first processing layer and the second processing layer, and bond the first bonding layer to the second bonding layer, and bond the first conductive layer to the second conductive layer.

[0009] In some embodiments, the specific steps for surface treatment of the first wafer and the second wafer include:

[0010] Perform surface treatment on the first wafer and the second wafer in a nitrogen-containing atmosphere to form the first bonding layer, the first processing layer, the second bonding layer, and the second processing layer.

[0011] In some embodiments, the specific steps for removing the first processing layer and the second processing layer, and bonding the first bonding layer to the second bonding layer, and bonding the first conductive layer to the second conductive layer include:

[0012] Remove the first processing layer and the second processing layer;

[0013] Bond the first wafer and the second wafer so that the first bonding layer is bonded to the second bonding layer, and the first conductive layer is bonded to the second conductive layer.

[0014] In some embodiments, the specific steps for removing the first processing layer and the second processing layer include:

[0015] Use a laser to irradiate only the first processing layer and the second processing layer, so that both the first processing layer and the second processing layer undergo a reduction reaction.

[0016] In some embodiments, the specific steps for removing the first processing layer and the second processing layer, and bonding the first bonding layer to the second bonding layer, and bonding the first conductive layer to the second conductive layer include:

[0017] Bond the first wafer and the second wafer so that the first bonding layer is bonded to the second bonding layer, and the first processing layer is bonded to the second processing layer;

[0018] Remove the first processing layer and the second processing layer, and electrically connect the first conductive layer and the second conductive layer.

[0019] In some embodiments, the specific steps for removing the first processing layer and the second processing layer include:

[0020] Use a laser annealing process to remove the first processing layer and the second processing layer.

[0021] In some embodiments, the first wafer further includes a first interconnect structure, the first interconnect structure is connected to a side of the first conductive layer away from the first processing layer, the second wafer further includes a second interconnect structure, and the second interconnect structure is connected to a side of the second conductive layer away from the second processing layer; the specific steps of removing the first processing layer and the second processing layer by using a laser annealing process include:

[0022] Irradiate a side of the first interconnect structure away from the first conductive layer and a side of the second interconnect structure away from the second conductive layer with a laser, so that a reduction reaction occurs in both the first processing layer and the second processing layer.

[0023] In some embodiments, the laser is an infrared laser, and the materials of the first interconnect structure and the second interconnect structure are both metal materials.

[0024] According to some other embodiments, the present disclosure further provides a bonding structure, including:

[0025] A first wafer, including a first dielectric layer, a first bonding layer covering the first dielectric layer, and a first conductive layer exposed on a surface of the first bonding layer;

[0026] A second wafer, including a second dielectric layer, a second bonding layer covering the second dielectric layer, and a second conductive layer exposed on a surface of the second bonding layer, the first bonding layer is bonded to the second bonding layer, and the first conductive layer is bonded to the second conductive layer.

[0027] In some embodiments, the first wafer further includes a first spacer and a first interconnect structure, one end of the first interconnect structure is electrically connected to the first conductive layer, and the other end is electrically connected to the first spacer, and the first spacer is used for receiving laser energy;

[0028] The second wafer further includes a second spacer and a second interconnect structure, one end of the second interconnect structure is electrically connected to the second conductive layer, and the other end is electrically connected to the second spacer, and the second spacer is used for receiving laser energy.

[0029] The bonding method and bonding structure provided by some embodiments of the present disclosure, after surface treatment of the first wafer and the second wafer to be bonded, form a first bonding layer covering the first dielectric layer in the first wafer, and a first treatment layer covering the first conductive layer in the first wafer, and form a second bonding layer covering the second dielectric layer in the second wafer, and a second treatment layer covering the second conductive layer in the second wafer. In the process of bonding the first wafer and the second wafer, by removing the first treatment layer and the second treatment layer, the first bonding layer is bonded to the second bonding layer, and at the same time the first conductive layer is bonded to the second conductive layer, so that in the hybrid bonding process, the bonding strength between the first dielectric layer and the second dielectric layer is enhanced, and the bonding strength between the first conductive layer and the second conductive layer is also enhanced, realizing the improvement of the overall bonding strength of the bonding structure and improving the performance of the bonding structure. In some other embodiments of the present disclosure, in the process of removing the first treatment layer and the second treatment layer, only the first conductive layer and the second conductive layer are heat-treated, avoiding damage to the device structure in the first wafer and the device structure in the second wafer, thereby reducing the generation of internal defects in the bonding structure and further improving the performance of the bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. Figure 1 is a flowchart of the bonding method in the specific embodiment of the present disclosure;

[0031] FIG. Figure 2 - FIG. Figure 7 is a schematic diagram of the main process structure in the process of bonding the first wafer and the second wafer in the specific embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following will make a detailed description of the specific embodiments of the bonding method and bonding structure provided by the present disclosure with reference to the drawings.

[0033] The present specific embodiment provides a bonding method, FIG. Figure 1 is a flowchart of the bonding method in the specific embodiment of the present disclosure, FIG. Figure 2 - FIG. Figure 7 is a schematic diagram of the main process structure in the process of bonding the first wafer and the second wafer in the specific embodiment of the present disclosure. As Figures 1-7 shown, the bonding method includes the following steps:

[0034] Step S11, providing a first wafer W1 and a second wafer W2, the first wafer W1 includes a first dielectric layer 21 and a first conductive layer 23 exposed on the surface of the first dielectric layer 21, and the second wafer W2 includes a second dielectric layer 31 and a second conductive layer 33 exposed on the surface of the second dielectric layer 31. As Figure 2 shown, wherein, Figure 2In (a) is a schematic cross-sectional view of the first wafer W1, Figure 2 and in (b) is a schematic cross-sectional view of the second wafer W2;

[0035] Step S12: Perform surface treatment on the first wafer W1 and the second wafer W2 to form a first bonding layer 40 covering the first dielectric layer 21 and a first treatment layer 41 covering the first conductive layer 23, and form a second bonding layer 42 covering the second dielectric layer 31 and a second treatment layer 43 covering the second conductive layer 33, as Figure 3 shown, wherein, Figure 2 in (a) is a schematic cross-sectional view after surface treatment of the first wafer W1, Figure 2 and in (b) is a schematic cross-sectional view after surface treatment of the second wafer W2;

[0036] Step S13: Remove the first treatment layer 41 and the second treatment layer 43, and bond the first bonding layer 40 to the second bonding layer 42, and bond the first conductive layer 23 and the second conductive layer 33, as Figure 7 shown.

[0037] In some embodiments, the specific steps of performing surface treatment on the first wafer W1 and the second wafer W2 include:

[0038] Perform surface treatment on the first wafer W1 and the second wafer W2 in a nitrogen-containing atmosphere to form the first bonding layer 40, the first treatment layer 41, the second bonding layer 42, and the second treatment layer 43.

[0039] Specifically, as Figure 2As shown in (a) therein, the first wafer W1 includes a first substrate 20, a first device layer 22 on the upper surface of the first substrate 20, the first dielectric layer 21 on the upper surface of the first device layer 22, and the first conductive layer 23 exposed on the upper surface of the first dielectric layer 21. The first substrate 20 may be, but is not limited to, a silicon substrate. In this specific embodiment, the first substrate 20 is taken as an example of a silicon substrate for illustration. In other embodiments, the first substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The upper surface of the first substrate 20 refers to the surface of the first substrate 20 facing the first dielectric layer 21. The first device layer 22 includes a first device structure 24, and the first device structure 24 may be any device structure such as a memory cell structure, a control circuit structure, a transistor structure, etc. The first dielectric layer 21 covers the upper surface of the first device layer 22 (i.e., the surface of the first device layer 22 facing away from the first substrate 20). In one example, the material of the first dielectric layer 21 may be an insulating dielectric material such as silicon dioxide. The material of the first conductive layer 23 may be a metal material such as copper, and at least part of the first conductive layer 23 is exposed on the upper surface of the first dielectric layer 21 (i.e., the surface of the first dielectric layer 21 facing away from the first device layer 22). As Figure 2 As shown in (b) therein, the second wafer W2 includes a second substrate 30, a second device layer 32 on the upper surface of the second substrate 30, the second dielectric layer 31 on the upper surface of the second device layer 32, and the second conductive layer 33 exposed on the upper surface of the second dielectric layer 31. The second substrate 30 may be, but is not limited to, a silicon substrate. In this specific embodiment, the second substrate 30 is taken as an example of a silicon substrate for illustration. In other embodiments, the second substrate 30 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The upper surface of the second substrate 30 refers to the surface of the second substrate 30 facing the second dielectric layer 31. The second device layer 32 includes a second device structure 34, and the second device structure 34 may be any device structure such as a memory cell structure, a control circuit structure, a transistor structure, etc. The second dielectric layer 31 covers the upper surface of the second device layer 32 (i.e., the surface of the second device layer 32 facing away from the second substrate 30). In one example, the material of the second dielectric layer 31 may be an insulating dielectric material such as silicon dioxide. The material of the second conductive layer 33 may be a metal material such as copper, and at least part of the second conductive layer 33 is exposed on the upper surface of the second dielectric layer 31 (i.e., the surface of the second dielectric layer 31 facing away from the second device layer 32).

[0040] During the surface treatment of the first wafer W1 and the second wafer W2, the first wafer W1 and the second wafer W2 can be placed in a surface treatment chamber, and a nitrogen-containing atmosphere is used to treat the surfaces of the first dielectric layer 21 and the first conductive layer 23 in the first wafer W1, and to treat the surfaces of the second dielectric layer 31 and the second conductive layer 33 in the second wafer W2, so that the first dielectric layer 21, the first conductive layer 23, the second dielectric layer 31, and the second conductive layer 33 all chemically react with the nitrogen-containing atmosphere to form the first bonding layer 40 covering the first dielectric layer 21 and the first treatment layer 41 covering the first conductive layer 23, and to form the second bonding layer 42 covering the second dielectric layer 31 and the second treatment layer 43 covering the second conductive layer 33, as Figure 3 shown. In one example, the nitrogen-containing atmosphere is an atmosphere containing any one or a combination of two or more of N 2 , NH 3 , NH 4 , and NO. By forming the first bonding layer 40 and the second bonding layer 42, after the first wafer W1 and the second wafer W2 are bonded, the bonding strength between the first dielectric layer 21 and the second dielectric layer 31 can be enhanced, that is, the bonding strength between the first wafer W1 and the second wafer W2 can be enhanced.

[0041] Hereinafter, it is described by taking the materials of the first dielectric layer 21 and the second dielectric layer 31 as silicon dioxide and the materials of the first conductive layer 23 and the second conductive layer 33 as copper as an example. After the first wafer W1 and the second wafer W2 are surface-treated with a nitrogen-containing atmosphere, the first bonding layer 40 made of silicon oxynitride is formed on the surface of the first dielectric layer 21, the first treatment layer 41 made of copper nitride is formed on the surface of the first conductive layer 23, the second bonding layer 42 made of silicon oxynitride is formed on the surface of the second dielectric layer 31, and the second treatment layer 43 made of copper nitride is formed on the surface of the second conductive layer 33. The bonding strength between silicon oxynitride and silicon oxynitride is stronger than the bonding strength between silicon dioxide and silicon dioxide. Therefore, the bonding strength between the first dielectric layer 21 and the second dielectric layer 31 after the subsequent bonding of the first wafer W1 and the second wafer W2 can be enhanced by surface treatment.

[0042] In some embodiments, the specific steps of removing the first treatment layer 41 and the second treatment layer 43 and bonding the first bonding layer 40 to the second bonding layer 42 and bonding the first conductive layer 23 and the second conductive layer 33 include:

[0043] Remove the first processing layer 41 and the second processing layer 43, as Figure 4 shown, where Figure 4 (a) in is a cross-sectional schematic diagram after removing the first processing layer 41 on the first wafer W1, Figure 4 (b) in is a cross-sectional schematic diagram after removing the second processing layer 43 on the second wafer W2;

[0044] Bond the first wafer W1 and the second wafer W2 so that the first bonding layer 40 is bonded to the second bonding layer 42 and the first conductive layer 23 is bonded to the second conductive layer 33, as Figure 7 shown.

[0045] In some embodiments, the specific steps of removing the first processing layer 41 and the second processing layer 43 include:

[0046] Use a laser to irradiate only the first processing layer 41 and the second processing layer 43, so that both the first processing layer 41 and the second processing layer 43 undergo a reduction reaction.

[0047] For example, before bonding the first wafer W1 and the second wafer W2, a laser emitter 50 can be used to emit a first laser signal 51 toward the first processing layer 41 and the second processing layer 43. Through the first laser signal 51, the temperature of the first processing layer 41 is increased and the temperature of the second processing layer 43 is increased, so that the first processing layer 41 and the second processing layer 43 undergo a reduction reaction, as Figure 4 shown. Where Figure 4 (a) in is a cross-sectional schematic diagram after removing the first processing layer 41 on the first wafer W1 by laser irradiation, Figure 4 (b) in is a cross-sectional schematic diagram after removing the second processing layer 43 on the second wafer W2 by laser irradiation. For example, when the materials of both the first processing layer 41 and the second processing layer 43 are copper nitride, after being irradiated by the first laser signal 51, copper nitride is reduced to copper, thereby realizing the removal of the first processing layer 41 and the second processing layer 43. Since the first processing layer 41 and the second processing layer 43 will reduce the bonding strength between the first conductive layer 23 and the second conductive layer 33, by removing the first processing layer 41 and the second processing layer 43, the bonding strength between the first conductive layer 23 and the second conductive layer 33 can be increased.

[0048] In one example, as Figure 4As shown, the laser emitter 50 directly emits the first laser signal 51 towards the first processing layer 41 and the second processing layer 43, that is, the first laser signal 51 directly irradiates the first processing layer 41 and the second processing layer 43, thereby improving the heating efficiency of the first processing layer 41 and the second processing layer 43 and reducing heat loss.

[0049] In another example, the first wafer W1 further includes a first spacer 25 and a first interconnect structure. The first spacer 25 is located on a side of the first substrate 20 facing away from the first dielectric layer 21. One end of the first interconnect structure is electrically connected to the first spacer 25, and the other end is electrically connected to the first conductive layer 23. For example, the first interconnect structure includes a first connection post 27, a second connection post 28, and a first via layer 26. The first connection post 27 penetrates through the first substrate 20 and the first device layer 22. The first via layer 26 is located on the upper surface of the first device layer 22. One end of the first connection post 27 is electrically connected to the first spacer 25, and the other end is electrically connected to the first via layer 26. The second connection post 28 penetrates through the first dielectric layer 21, and one end of the second connection post 28 is electrically connected to the first via layer 26, and the other end is electrically connected to the first conductive layer 23. The first laser signal 51 emitted by the laser emitter 50 towards the first spacer 25 causes the temperature of the first spacer 25 to rise and generate heat. The heat generated in the first spacer 25 is sequentially transferred to the first processing layer 41 through the first connection post 27, the first via layer 26, the second connection post 28, and the first conductive layer 23, causing the temperature of the first processing layer 41 to rise, and further causing the first processing layer 41 to be removed due to a reduction reaction. The second wafer W2 further includes a second spacer 35 and a second interconnect structure. The second spacer 35 is located on a side of the second substrate 30 facing away from the second dielectric layer 31. One end of the second interconnect structure is electrically connected to the second spacer 35, and the other end is electrically connected to the second conductive layer 33. For example, the second interconnect structure includes a third connection post 37, a fourth connection post 38, and a second via layer 36. The third connection post 37 penetrates through the second substrate 30 and the second device layer 32. The second via layer 36 is located on the upper surface of the second device layer 32. One end of the third connection post 37 is electrically connected to the second spacer 35, and the other end is electrically connected to the second via layer 36. The fourth connection post 38 penetrates through the second dielectric layer 31, and one end of the fourth connection post 38 is electrically connected to the second via layer 36, and the other end is electrically connected to the second conductive layer 33. The first laser signal 51 emitted by the laser emitter 50 towards the second spacer 35 causes the temperature of the second spacer 35 to rise and generate heat. The heat generated in the second spacer 35 is sequentially transferred to the second processing layer 43 through the third connection post 37, the second via layer 36, the fourth connection post 38, and the second conductive layer 33, causing the temperature of the second processing layer 43 to rise, and further causing the second processing layer 43 to be removed due to a reduction reaction.

[0050] In this specific embodiment, the first laser signal 51 directly irradiates only the first processing layer 41 and the second processing layer 43, or the heat of the first laser signal 51 is transferred to the first processing layer 41 and the second processing layer 43 only through the first interconnecting structure and the second interconnecting structure, that is, only the first wafer W1 and the second wafer W2 are locally heated, so that while the first processing layer 41 and the second processing layer 43 can be removed, the heat generated by the laser can be avoided from damaging the first device structure 24 in the first wafer W1 and the second device structure 34 in the second wafer W2, ensuring the stability of the performance of the first device structure 24 and the second device structure 34.

[0051] After removing the first processing layer 41 and the second processing layer 43, the first wafer W1 and the second wafer W2 are bonded in the direction of the first dielectric layer 21 facing the second dielectric layer 31, so that the first bonding layer 40 is bonded to the second bonding layer 42, and the first conductive layer 23 is bonded to the second conductive layer 33, as Figure 7 shown. In an example, the surface of the first conductive layer 23 in the first wafer W1 has a dish-shaped depression, and the surface of the second conductive layer 33 in the second wafer W2 also has a dish-shaped depression, so that after the first wafer W1 and the second wafer W2 are bonded, there is a gap (such as an air gap) between the first conductive layer 23 and the second conductive layer 33. To further enhance the bonding strength between the first conductive layer 23 and the second conductive layer 33, after bonding the first wafer W1 and the second wafer W2, the second laser signal 53 can also be used to irradiate the first spacer 25 and the second spacer 35, so that the heat of the second laser signal 53 can be transmitted to the first conductive layer 23 through the first spacer 25 and the first interconnecting structure, and can be transmitted to the second conductive layer 33 through the second spacer 35 and the second interconnecting structure, to anneal the first conductive layer 23 and the second conductive layer 33, as Figure 5 shown. Through the annealing treatment, the first conductive layer 23 expands towards the second conductive layer 33, and the second conductive layer 33 expands towards the first conductive layer 23 until the gap between the first conductive layer 23 and the second conductive layer 33 is filled, as Figure 7 shown, to further enhance the bonding strength between the first conductive layer 23 and the second conductive layer 33.

[0052] In some other embodiments, the specific steps of removing the first processing layer 41 and the second processing layer 43, bonding the first bonding layer 40 to the second bonding layer 42, and bonding the first conductive layer 23 to the second conductive layer 33 include:

[0053] The first wafer W1 and the second wafer W2 are bonded so that the first bonding layer 40 is bonded to the second bonding layer 42, and the first processing layer 41 is bonded to the second processing layer 43. Figure 6 As shown;

[0054] The first processing layer 41 and the second processing layer 43 are removed, and the first conductive layer 23 and the second conductive layer 33 are electrically connected.

[0055] In some embodiments, the specific steps of removing the first processing layer 41 and the second processing layer 43 include:

[0056] The first processing layer 41 and the second processing layer 43 are removed by laser annealing process.

[0057] In some embodiments, the first wafer W1 further includes a first interconnect structure, the first interconnect structure is connected to a side of the first conductive layer 23 away from the first processing layer 41, and the second wafer W2 further includes a second interconnect structure, the second interconnect structure is connected to a side of the second conductive layer 33 away from the second processing layer 43; the specific steps of removing the first processing layer 41 and the second processing layer 43 by laser annealing process include:

[0058] Laser is used to irradiate a side of the first interconnect structure away from the first conductive layer 23 and a side of the second interconnect structure away from the second conductive layer 33 , so that both the first processed layer 41 and the second processed layer 43 undergo a reduction reaction.

[0059] For example, after the first wafer W1 and the second wafer W2 are bonded in the direction of the first dielectric layer 21 toward the second dielectric layer 31, the first bonding layer 40 and the second bonding layer 42 are bonded, and the first processing layer 41 and the second processing layer 43 are bonded. Figure 6As shown. Thereafter, local annealing treatment is performed on the bonded first wafer W1 and the second wafer W2. During the local annealing treatment, the third laser signal 60 emitted towards the first spacer 25 causes the temperature of the first spacer 25 to rise and generate heat. The heat generated in the first spacer 25 is sequentially transmitted to the first processing layer 41 through the first connecting column 27, the first transfer layer 26, the second connecting column 28, and the first conductive layer 23, causing the temperature of the first processing layer 41 to rise, and then causing the first processing layer 41 to be removed due to a reduction reaction. At the same time, the third laser signal 60 emitted towards the second spacer 35 causes the temperature of the second spacer 35 to rise and generate heat. The heat generated in the second spacer 35 is sequentially transmitted to the second processing layer 43 through the third connecting column 37, the second transfer layer 36, the fourth connecting column 38, and the second conductive layer 33, causing the temperature of the second processing layer 43 to rise, and then causing the second processing layer 43 to be removed due to a reduction reaction. After the first processing layer 41 and the second processing layer 43 are removed, the third laser signal 60 can continue to be emitted towards the first spacer 25 and the second spacer 35, causing the first conductive layer 23 with a dish-shaped depression to expand towards the second conductive layer 33, and the second conductive layer 33 with a dish-shaped depression to expand towards the first conductive layer 23 until the gap between the first conductive layer 23 and the second conductive layer 33 is filled, as Figure 7 shown to further enhance the bonding strength between the first conductive layer 23 and the second conductive layer 33.

[0060] In the present specific embodiment, the heat of the third laser signal 60 is only transmitted to the first conductive layer 23, the second conductive layer 33, the first processing layer 41, and the second processing layer 43 through the first interconnect structure and the second interconnect structure, that is, only local annealing treatment is performed on the first wafer W1 and the second wafer W2, so that while the first processing layer 41 and the second processing layer 43 can be removed, the heat generated by the laser can be avoided from damaging the first device structure 24 in the first wafer W1 and the second device structure 34 in the second wafer W2, ensuring the stability of the performance of the first device structure 24 and the second device structure 34.

[0061] In some embodiments, the laser is an infrared laser, and the materials of the first interconnect structure and the second interconnect structure are both metal materials. In one example, the first laser signal 51, the second laser signal 53, and the third laser signal 60 are all infrared laser signals with a wavelength of 980 nm to improve the removal efficiency of the first processing layer 41 and the second processing layer 43.

[0062] This specific embodiment also provides a bonding structure, and its structure can be referred to Figure 7 . The bonding structure provided by this specific embodiment can be formed by using a bonding method such as Figures 1-7 shown. As Figure 7 shown, the bonding structure includes:

[0063] A first wafer W1, including a first dielectric layer 21, a first bonding layer 40 covering the first dielectric layer 21, and a first conductive layer 23 exposed on the surface of the first bonding layer 40;

[0064] A second wafer W2, including a second dielectric layer 31, a second bonding layer 42 covering the second dielectric layer 31, and a second conductive layer 33 exposed on the surface of the second bonding layer 42. The first bonding layer 40 is bonded to the second bonding layer 42, and the first conductive layer 23 is bonded to the second conductive layer 33.

[0065] In some embodiments, the first wafer W1 further includes a first spacer 25 and a first interconnect structure. One end of the first interconnect structure is electrically connected to the first conductive layer 23, and the other end is electrically connected to the first spacer 25. The first spacer 25 is used to receive laser energy;

[0066] The second wafer W2 further includes a second spacer 35 and a second interconnect structure. One end of the second interconnect structure is electrically connected to the second conductive layer 33, and the other end is electrically connected to the second spacer 35. The second spacer 35 is used to receive laser energy.

[0067] The bonding method and bonding structure provided by some embodiments of the present specific implementation manner, after surface treatment of the first wafer and the second wafer to be bonded, form a first bonding layer covering the first dielectric layer in the first wafer, and a first treatment layer covering the first conductive layer in the first wafer, and form a second bonding layer covering the second dielectric layer in the second wafer, and a second treatment layer covering the second conductive layer in the second wafer. In the process of bonding the first wafer and the second wafer, by removing the first treatment layer and the second treatment layer, the first bonding layer is bonded to the second bonding layer, and at the same time the first conductive layer is bonded to the second conductive layer, thereby enhancing the bonding strength between the first dielectric layer and the second dielectric layer in the hybrid bonding process, and also enhancing the bonding strength between the first conductive layer and the second conductive layer, realizing the improvement of the overall bonding strength of the bonding structure and improving the performance of the bonding structure. In some other embodiments of the present specific implementation manner, in the process of removing the first treatment layer and the second treatment layer, only the first conductive layer and the second conductive layer are heat-treated, avoiding damage to the device structure in the first wafer and the device structure in the second wafer, thereby reducing the generation of internal defects in the bonding structure and further improving the performance of the bonding structure.

[0068] The above are only the preferred embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present disclosure, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present disclosure.

Claims

1. A bonding method, It is characterized in that The steps include: Providing a first wafer and a second wafer, wherein the first wafer comprises a first dielectric layer and a first conductive layer exposed on a surface of the first dielectric layer, and the second wafer comprises a second dielectric layer and a second conductive layer exposed on a surface of the second dielectric layer; Performing surface treatment on the first wafer and the second wafer to form a first bonding layer covering the first dielectric layer and a first processing layer covering the first conductive layer, and forming a second bonding layer covering the second dielectric layer and a second processing layer covering the second conductive layer; The first wafer further includes a first interconnect structure and a first gasket, wherein the first interconnect structure is connected to a side of the first conductive layer away from the first processing layer, and is located between the first conductive layer and the first gasket, and is electrically connected to the first gasket; the second wafer further includes a second interconnect structure and a second gasket, wherein the second interconnect structure is connected to a side of the second conductive layer away from the second processing layer, and is located between the second conductive layer and the second gasket, and is electrically connected to the second gasket; Bonding the first wafer and the second wafer so that the first bonding layer is bonded to the second bonding layer; A third laser signal is emitted toward the first gasket and the second gasket, so that the temperature of the first gasket and the second gasket increases and generates heat, and the heat is transferred to the first processing layer along the first interconnect structure and the first conductive layer, and is transferred to the second processing layer along the second interconnect structure and the second conductive layer, so that the temperature increase of the first processing layer and the second processing layer is removed, and the first conductive layer and the second conductive layer are bonded and connected.

2. The bonding method according to claim 1, It is characterized in that The specific steps of performing surface treatment on the first wafer and the second wafer include: The first wafer and the second wafer are subjected to surface treatment in a nitrogen-containing atmosphere to form the first bonding layer, the first processing layer, the second bonding layer and the second processing layer.

3. The bonding method according to claim 1, It is characterized in that The laser is an infrared laser, and the material of the first interconnect structure and the material of the second interconnect structure are both metal materials.

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