A small-area SAR ADC with offset voltage calibration based on charge pump

Abstract

The present application relates to a kind of small area SAR ADC based on charge pump's misadjustment voltage calibration.It includes DAC capacitor array, SAR logic control module, comparator, charge pump, charge pump control logic module.There is calibration mode and normal mode, before entering calibration mode, capacitor array is reset first, charge pump is charged simultaneously, after entering calibration mode, the result of comparator is charged and discharged to charge pump by logic, and then eliminate misadjustment voltage, after calibration mode ends, enter normal working state, after sampling input signal, it is compared in turn bit by bit, and then digital code is obtained.The comparator of the circuit is also using full dynamic comparator, without static power consumption, so that power consumption is greatly reduced.The present application is suitable for low speed, high precision, low power consumption SAR ADC.

Description

Technical Field

[0001] This invention relates to a small-area SAR ADC based on charge pump offset voltage calibration. Background Technology

[0002] With the rapid development of the integrated circuit industry, especially the rise of the Internet of Things (IoT), many new types of sensors have emerged. As the foundation of the entire IoT industry, sensors can receive and process external signals. In the real world, signals such as sound, heat, and electrical signals are analog information and need to be converted before they can be recognized and processed by digital circuits. Analog-to-digital converters (ADCs) are the fundamental modules for building sensors. They convert continuously varying analog signals over time and amplitude into discrete digital signals through sampling, holding, quantization, and encoding, thereby controlling digital circuits.

[0003] Successive Approximation Register ADCs, also known as SAR ADCs, are widely used in applications requiring high precision, low speed, and low power consumption. With the rapid development of portable and wearable devices in recent years, products are increasingly focused on miniaturization and low power consumption. Furthermore, in wearable devices, the signals requiring quantization exhibit smaller variations and narrower bandwidths, necessitating a shift in SAR ADC development towards lower power consumption and higher precision.

[0004] For high-precision SAR ADCs, non-ideal factors such as capacitor mismatch and comparator offset voltage determine the conversion accuracy of the entire system. The comparator, as the core module of the SAR ADC, directly impacts the overall power consumption and accuracy. During manufacturing, even identical components may exhibit random mismatches, leading to DC offset in the comparator. Most high-precision SAR ADCs currently use a static pre-amplification and dynamic latching approach. The presence of the static pre-amplification stage increases the overall circuit's static power consumption. In multi-stage pre-amplification comparators, two common offset cancellation techniques are Input Offset Storage (IOS) and Output Offset Storage (OOS). Both methods involve adding capacitors between stages of the multi-stage amplification structure to store the offset voltage, preventing it from affecting the input signal by controlling the switching of the switches. While both IOS and OOS effectively eliminate offset, both techniques require additional timing, making the logic circuitry more complex and increasing power consumption. In addition, current methods to reduce offset voltage by changing the substrate potential through charge pump charging and discharging require large additional capacitors, resulting in a large area and additional overhead. Summary of the Invention

[0005] The purpose of this invention is to eliminate the offset voltage of SAR ADC and improve the overall accuracy. It provides a small-area SAR ADC based on charge pump offset voltage calibration, which does not require the introduction of additional large capacitors to calibrate the offset voltage, reduces the area required by the circuit, and improves the accuracy of the overall circuit.

[0006] To achieve the above objectives, the technical solution of the present invention is: a small-area SAR ADC based on charge pump offset voltage calibration, comprising a DAC capacitor array, a SAR logic control module, a comparator, a charge pump, and a charge pump control logic module; the outputs VOUTP and VOUTN of the comparator are switched by the SAR logic control module through the switching of the lower plate of the capacitor DAC array from SWNn-2 to SWN1 and from SWPn-2 to SWP1, thereby changing the upper plate potentials VDACP and VDACN of the capacitor DAC array, where VDACP and VDACN serve as the two input signals of the comparator; the charge pump control logic module generates charge pump control signals C and NC under the joint control of the comparator outputs VOUTP and VOUTN and the enable signal EN, thereby controlling the charge pump to charge and discharge the calibration capacitor.

[0007] In one embodiment of the present invention, the DAC capacitor array includes capacitors CN1 to CNn-2, capacitor Cdn, capacitors CP1 to CPn-2, capacitor Cdp, switches SWN1 to SWNn-2, switch SWNer, switches SWP1 to SWPn-2, and switch SWPer. The upper plates of capacitors CN1 to CNn-2 and capacitor Cdn are connected and serve as the first input terminal of the DAC capacitor array, and are also connected to the first input terminal of the comparator as the VDACN signal output terminal of the DAC capacitor array. The lower plates of capacitors CN1 to CNn-2 are respectively connected to switches SWN1 to SWNn. -2 is connected to VREF, VCM, and GND. The lower plate of capacitor Cdn is connected to the first output terminal of the charge pump and VCM via switch SWNer. The upper plates of capacitors CP1 to CPn-2 and capacitor Cdp are connected and serve as the second input terminal of the DAC capacitor array. At the same time, they serve as the VDACP signal output terminal of the DAC capacitor array and are connected to the second input terminal of the comparator. The lower plates of capacitors CP1 to CPn-2 are connected to VREF, VCM, and GND via switches SWP1 to SWPn-2 respectively. The lower plate of capacitor Cdp is connected to the second output terminal of the charge pump and VCM via switch SWPer.

[0008] In one embodiment of the present invention, the switches SWN1 to SWNn-2 and SWP1 to SWPn-2 are all three-to-one switches; the switches SWNer and SWPer are two-to-one switches.

[0009] In one embodiment of the present invention, the comparator includes a preamplifier and a latch. The preamplifier includes transistors M0 to M4. The source of M0 is connected to the power supply. The drain of M0 is connected to the source of M1 and the source of M2. The drains of M1 and M2 are connected to the drains of M3 and M4, respectively. The sources of M3 and M4 are connected to GND. The gates of M0, M3, and M4 are all used as input terminals for the clock signal CLKC. The gates of M1 and M2 are used as input terminals for the VDACP and VDACN signals, respectively. The latch includes transistors M5 to M6. 12. The sources of M5, M6, M7, and M8 are connected to the power supply. The drains of M5, M6, M7, M10, and M11 are connected and used as the VOUTN signal output terminal. The drains of M6, M5, M8, M9, and M12 are connected and used as the VOUTP signal output terminal. The gates of M7 and M11 are connected. The gates of M8 and M12 are connected. The drain of M9 is connected to the source of M11. The drain of M10 is connected to the source of M12. The sources of M9 and M10 are connected to GND.

[0010] In one embodiment of the present invention, the charge pump includes transistors M13 to M20, OTA1, OTA2, calibration capacitor Ccn, calibration capacitor Ccp, the source of M13 connected to GND, the gate of M13 serving as the enable signal EN input terminal, the drain of M13 connected to the source of M14 and the source of M15, the gates of M14 and M15 serving as the input terminals of VOUTP and VOUTN signals respectively, the drains of M14 and M15 connected to the source of M16 and the source of M17 respectively, the gates of M16 and M17 serving as the input terminals of the charge pump control signal C, and the drains of M16, M18, M20, and C... One end of Ccp is connected to the non-inverting input of OTA1. The drains of M17, M19, and M21, and one end of Ccn are connected to the non-inverting input of OTA2. The sources of M18, M19, M20, and M21 are connected to the power supply. The gates of M18 and M19 serve as the inputs of the charge pump control signal NC. The gates of M20 and M21 serve as the inputs of the charge pump control signal PRE. Ccp and Ccn are connected to GND. The inverting input of OTA1 is connected to the output of OTA1 as the second output of the charge pump. The inverting input of OTA2 is connected to the output of OTA2 as the first output of the charge pump.

[0011] In one embodiment of the present invention, the charge pump control logic module includes AND gates AND1, AND2, and AND3, a buffer circuit buffer1, an XOR gate XOR1, an inverter INV1, VOUTP and VOUTN inputs through the two input terminals of AND1, an enable signal EN input through the second input terminal of AND2, the first input terminals of AND2 and AND3 connected to the output terminal of AND1, the output terminal of AND2 connected to the first input terminal of XOR1 through buffer1, the output terminal of AND2 also directly connected to the second input terminal of XOR1, the output terminal of XOR1 connected to the second input terminal of AND3, the output terminal of AND3 outputs a signal as the charge pump control signal C, and the output terminal of AND3 also outputs a signal through INV1 as the charge pump control signal NC.

[0012] In one embodiment of the present invention, the SAR ADC operates as follows:

[0013] For one side of the SAR ADC, in the initialization state, both the upper and lower plates of the capacitors in the DAC capacitor array are connected to VCM. At this time, PRE is low, controlling the charging of the calibration capacitor Ccn of the charge pump.

[0014] At the next moment, the enable signal EN controls the charge pump logic control module to enter calibration mode. At this time, the upper plate switch of the DAC capacitor array is turned off, and the lower plates of capacitors CNn-2 to CN1 remain connected to VCM. At this time, the lower plate of Cdn is connected to the output VX of OTA2. The potential of the upper plate of the DAC capacitor array changes, the comparator starts to work, and the comparator result is sent to the charge pump logic control module to generate charge pump control signals C and NC, which control the charge pump calibration capacitor Ccn to charge and discharge until the voltage difference on the calibration capacitor Ccn is less than 1 LSB. The calibration is completed and the offset voltage is stored in the calibration capacitor Ccn. Due to the presence of OTA2, Cdn is isolated, so Cdn will not affect the value of the calibration capacitor Ccn, thus ensuring that the offset voltage will not change and only one calibration is needed.

[0015] After the calibration mode ends, the DAC enters normal operation mode. At this time, the upper plate of the capacitor in the capacitor array will be connected to VIN, the lower plates of capacitors CNn-2 to CN1 will remain connected to VCM, and Cdn will remain connected to the output VX of OTA2 for sampling.

[0016] After sampling is completed, the upper plate of the capacitor in the DAC capacitor array is disconnected. Based on the comparison result, the comparator controls the lower plate of the capacitor in the DAC capacitor array to switch to VREF or GND one by one through the SAR logic control module.

[0017] Similarly, the other side of the SAR ADC works on a similar principle.

[0018] Compared to existing technologies, this invention offers the following advantages: This invention provides a small-area SAR ADC based on charge pump offset voltage calibration. It includes a DAC capacitor array, a SAR logic control module, a comparator, a charge pump, and a charge pump control logic module. This calibration circuit can calibrate the input offset voltage without adding large capacitors or complex digital logic circuits, reducing the overall SAR ADC power consumption and area, thus realizing an offset calibration circuit suitable for high-precision, low-power SAR ADCs. This invention has great application potential in low-power, high-precision SAR ADCs. Attached Figure Description

[0019] Figure 1 This is a block diagram of a SAR ADC system based on charge pump offset voltage cancellation technology.

[0020] Figure 2 It is a DAC capacitor array.

[0021] Figure 3 This is the comparator circuit structure.

[0022] Figure 4 This describes the detailed structure of the charge pump control logic.

[0023] Figure 5 This is a detailed description of the charge pump structure.

[0024] Figure 6 The switch is in a reset state and is in a toggle state.

[0025] Figure 7 The charge pump operates in calibration mode.

[0026] Figure 8 Sampling for the normal operating mode circuit.

[0027] Figure 9 Comparison of circuits in normal operating mode.

[0028] Figure 10 This is the PRE clock signal. Detailed Implementation

[0029] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] This invention provides a small-area SAR ADC based on charge pump offset voltage calibration, including a DAC capacitor array, a SAR logic control module, a comparator, a charge pump, and a charge pump control logic module. The comparator outputs VOUTP and VOUTN are switched by the SAR logic control module via the switching of the lower plate of the DAC capacitor array from SWNn-2 to SWN1 and from SWPn-2 to SWP1, thereby changing the upper plate potentials VDACP and VDACN of the DAC capacitor array. VDACP and VDACN serve as the two input signals of the comparator. The charge pump control logic module generates charge pump control signals C and NC under the combined control of the comparator outputs VOUTP and VOUTN and the enable signal EN, controlling the charge pump to charge and discharge the calibration capacitor.

[0031] The following is a detailed implementation process of the present invention.

[0032] To eliminate the offset voltage of SAR ADC and improve overall accuracy, this invention proposes a small-area SAR ADC with offset voltage calibration based on charge pump. Figure 1 As shown. The main modules consist of a DAC capacitor array, a SAR logic control module, a comparator, a charge pump, and a charge pump control logic module. The DAC capacitor array is shown below. Figure 2 As shown, the comparator's results VOUTP and VOUTN control the switching of the capacitor's lower plate switches SWNn and SWPn via SAR logic, thereby changing the upper plate potentials VDACP and VDACN. The comparator is as follows... Figure 3 As shown, it mainly consists of a preamplifier and a latch. The preamplifier provides a certain gain to the input signal, thus reducing the noise and offset of the latch stage equivalent to the input. The charge pump control logic is as follows: Figure 4 As shown, the charge pump structure is as follows Figure 5 As shown, the charge pump control logic generates charge pump control signals C and NC under the joint control of the comparator results VOUTP and VOUTN and the enable signal EN, thereby controlling the charge pump to charge and discharge the capacitor.

[0033] For ease of explanation, the single-sided operating principle of the SAR ADC will be used for illustration. In the initialization state, both the upper and lower plates of the SAR ADC's capacitor array are connected to VCM. At this time, the PRE signal is low, controlling the charging of the calibration capacitor Ccn of the charge pump, as shown below. Figure 6 As shown. The PRE signal can be generated by an external DIP switch. It is manually switched to ground before the chip is powered on and to power after power-on. Specifically, it takes the form of a rectangular pulse similar to a brief low level followed by a permanent high level, such as... Figure 10 As shown.

[0034] At the next moment, the EN signal controls the charge pump logic control module to enter calibration mode. At this time, the upper plate switch of the capacitors is open, and the lower plates of capacitor arrays CNn-2 to CN1 remain connected to the VCM potential. The lower plate of Cdn is then connected to the OTA outputs VX and VY. The potential of the upper plate of the capacitors changes, and the comparator starts working. The comparator result is sent to the subsequent logic control unit, generating control signals C and NC for the charge pump, controlling its charging and discharging. The capacitors at both ends continuously charge and discharge until the voltage difference across them is less than 1 LSB. At this point, calibration is complete, and the offset voltage is stored in the calibration capacitor Ccn. Because of the presence of the OTA, Cdn is isolated, so the upper capacitors do not affect the value of the calibration capacitor Ccn, thus ensuring that the offset voltage remains unchanged, requiring only one calibration. Furthermore, the value of the calibration capacitor Ccn can be very small, significantly reducing the layout area. Figure 7 As shown.

[0035] After calibration, the system enters normal operation. At this point, the upper plate of the capacitors will receive VIP and VIN inputs, while the lower plates of capacitor arrays CNn-2 to CN1 remain connected to the VCM potential. Cdn remains connected to the OTA outputs VX and VY for sampling. Figure 8 As shown.

[0036] After sampling, the upper plate is disconnected. Based on the comparison result, the comparator, through the SAR logic control unit, controls the lower plate of each capacitor to switch sequentially to VREF or GND. Figure 9 As shown.

[0037] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A small-area SAR ADC with offset voltage calibration based on charge pump, characterized in that, Includes a DAC capacitor array, SAR logic control module, comparator, charge pump, and charge pump control logic module; the comparator output result. and The potential of the upper capacitor plate in the DAC capacitor array is changed by switching the lower capacitor plate from SWNn-2 to SWN1 and from SWPn-2 to SWP1, which is controlled by the SAR logic control module. and , and The two input signals of the comparator; the charge pump control logic module uses the comparator's output result... and Under the combined control of the enable signal EN, charge pump control signals C and NC are generated to control the charge pump to charge and discharge its calibration capacitor; the DAC capacitor array includes capacitors CN1 to CNn-2, capacitor Cdn, capacitors CP1 to CPn-2, capacitor Cdp, switches SWN1 to SWNn-2, switch SWNer, switches SWP1 to SWPn-2, and switch SWPer; the upper plates of capacitors CN1 to CNn-2 and capacitor Cdn are connected and serve as the first input terminal of the DAC capacitor array, and also as the... The signal output terminal is connected to the first input terminal of the comparator. The lower plates of capacitors CN1 to CNn-2 are connected to VREF, VCM, and GND respectively via switches SWN1 to SWNn-2. ​​The lower plate of capacitor Cdn is connected to the first output terminal of the charge pump and VCM via switch SWNer. The upper plates of capacitors CP1 to CPn-2 and capacitor Cdp are connected and serve as the second input terminal of the DAC capacitor array, and also as the DAC capacitor array... The signal output terminal is connected to the second input terminal of the comparator. The lower plates of capacitors CP1 to CPn-2 are connected to VREF, VCM, and GND via switches SWP1 to SWPn-2, respectively. The lower plate of capacitor Cdp is connected to the second output terminal of the charge pump and VCM via switch SWPer.

2. The small-area SAR ADC based on charge pump offset voltage calibration according to claim 1, characterized in that, The switches SWN1 to SWNn-2 and SWP1 to SWPn-2 are all 1-to-3 switches; the switches SWNer and SWPer are all 1-to-2 switches.

3. A small-area SAR ADC based on charge pump offset voltage calibration according to claim 1, characterized in that, The comparator includes a preamplifier and a latch. The preamplifier includes transistors M0 to M4. The source of M0 is connected to the power supply. The drain of M0 is connected to the source of M1 and the source of M2. The drains of M1 and M2 are connected to the drains of M3 and M4, respectively. The sources of M3 and M4 are connected to GND. The gates of M0, M3, and M4 all serve as input terminals for the clock signal CLKC. The gates of M1 and M2 serve as input terminals for the clock signal CLKC. , Signal input terminal; the latch includes transistors M5 to M12. The sources of M5, M6, M7, and M8 are connected to the power supply. The drain of M5, the gate of M6, the drain of M7, the gate of M10, and the drain of M11 are connected together and serve as... At the signal output terminal, the drain of M6, the gate of M5, the drain of M8, the gate of M9, and the drain of M12 are connected and serve as... At the signal output terminal, the gate of M7 is connected to the gate of M11, the gate of M8 is connected to the gate of M12, the drain of M9 is connected to the source of M11, the drain of M10 is connected to the source of M12, and the source of M9 and the source of M10 are connected to GND.

4. A small-area SAR ADC based on charge pump offset voltage calibration according to claim 1, characterized in that, The charge pump includes transistors M13 to M20, OTA1, OTA2, calibration capacitor Ccn, calibration capacitor Ccp, the source of M13 connected to GND, the gate of M13 serving as the enable signal EN input, the drain of M13 connected to the source of M14 and the source of M15, and the gates of M14 and M15 respectively serving as... , At the signal input terminals, the drains of M14 and M15 are connected to the sources of M16 and M17, respectively. The gates of M16 and M17 serve as the input terminals of the charge pump control signal C. The drains of M16, M18, and M20, and one end of Ccp, are connected to the non-inverting input terminal of OTA1. The drains of M17, M19, and M21, and one end of Ccn, are connected to the non-inverting input terminal of OTA2. The sources of M18, M19, M20, and M21 are connected to the power supply. The gates of M18 and M19 serve as the input terminals of the charge pump control signal NC, and the gates of M20 and M21 serve as the input terminals of the charge pump control signal PRE. Ccp and Ccn are connected to GND. The inverting input terminal of OTA1 is connected to the output terminal of OTA1 as the second output terminal of the charge pump, and the inverting input terminal of OTA2 is connected to the output terminal of OTA2 as the first output terminal of the charge pump.

5. A small-area SAR ADC based on charge pump offset voltage calibration according to claim 1, characterized in that, The charge pump control logic module includes AND gates AND1, AND2, and AND3, a buffer circuit buffer1, an XOR gate XOR1, and an inverter INV1. and The enable signal EN is input through the two input terminals of AND1. The first input terminals of AND2 and AND3 are connected to the output terminal of AND1. The output terminal of AND2 is connected to the first input terminal of XOR1 through buffer1. The output terminal of AND2 is also directly connected to the second input terminal of XOR1. The output terminal of XOR1 is connected to the second input terminal of AND3. The output terminal of AND3 outputs a signal as the charge pump control signal C. The output terminal of AND3 also outputs a signal as the charge pump control signal NC through INV1.

6. A small-area SAR ADC with offset voltage calibration based on charge pump according to claim 4, characterized in that, The SAR ADC operates as follows: For one side of the SAR ADC, in the initialization state, both the upper and lower plates of the DAC capacitor array are connected... At this time, PRE is at a low level, which controls the charging of the calibration capacitor Ccn of the charge pump; At the next moment, the enable signal EN controls the charge pump logic control module to enter calibration mode. At this time, the upper plate switch of the DAC capacitor array is open, and the lower plates of capacitors CNn-2 to CN1 remain connected. At this point, the lower plate of Cdn is connected to the output VX of OTA2. The potential of the upper plate of the capacitor in the DAC capacitor array changes, and the comparator starts to work. The comparator result is sent to the charge pump logic control module to generate charge pump control signals C and NC, which control the charge pump calibration capacitor Ccn to charge and discharge until the voltage difference on the calibration capacitor Ccn is less than 1 LSB. The calibration is then complete, and the offset voltage is stored in the calibration capacitor Ccn. Due to the presence of OTA2, Cdn is isolated, so Cdn will not affect the value of the calibration capacitor Ccn, thus ensuring that the offset voltage will not change and only one calibration is needed. After the calibration mode ends, it enters normal operating mode. At this time, the upper plate of the capacitor in the DAC capacitor array will receive the input. The lower plate of capacitor CNn-2 to CN1 remains connected. Cdn continues to connect to the OTA2 output VX for sampling; After sampling, the upper plate of the capacitors in the DAC capacitor array is disconnected. Based on the comparison result, the comparator, through the SAR logic control module, controls the lower plate of the capacitors in the DAC capacitor array to switch one by one to the specified position. or ; Similarly, the other side of the SAR ADC works on a similar principle.

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