A design method of a multiplier based on a magnetic tunnel junction storage and calculation and the multiplier
By designing a multiplier based on magnetic tunnel junction storage and computation, and using MTJ and CMOS combined AND gate circuits for AND operation and partial product calculation, and combining CSA array and CPA for carry-retaining multiplication operation, the problems of poor computing performance and high power consumption are solved, realizing the integration of computing functions and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2023-06-27
- Publication Date
- 2026-05-19
AI Technical Summary
Existing circuits based on magnetic tunneling memory integration face difficulties in integrating computing functions into magnetic tunneling memory cells, resulting in poor computing performance and high power consumption.
Design a multiplier based on magnetic tunnel junction multiplication. By building a combined MTJ and CMOS AND gate circuit, performing AND operations using the combined MTJ and CMOS AND gate circuit, building an AND gate array to perform partial product calculations, and introducing a CSA array and CPA to perform carry-retaining multiplication operations, the computational functions are integrated.
By effectively integrating computing functions into the magnetic tunnel memory unit, the problems of poor computing performance and high power consumption are solved, and the frequent memory access operations on the multiplicand are reduced.
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Figure CN116880797B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic technology, and in particular to a design method for an in-memory multiplier. Background Technology
[0002] As technology advances, Moore's Law has encountered bottlenecks. Device leakage power consumption increases exponentially with the advancement of process nodes, accounting for an increasingly larger proportion of the chip's total power consumption. Furthermore, because processors and memory in computer architectures employ different process routes, the traditional von Neumann architecture faces problems such as the "memory wall" and the "power wall," which severely limit processor performance improvements.
[0003] To address these issues, process designers are constantly seeking new solutions. Magnetic tunnel junctions (MTJs) are non-volatile, offer higher integration density than traditional CMOS devices, and require only a fraction of the energy needed to move electron charge to change electron spin.
[0004] In 1996, Slonczewski and Berger independently predicted the existence of the spin-transfer-torque (STT) in spin valves. Subsequently, the STT effect was gradually applied in devices such as hard drives and memory. STT-MRAM, which uses STT current to write data and tunnel magnetoresistance to read data, was also developed in 2007. Applying magnetic tunnel junctions to the processor field, and utilizing their non-volatile storage, can achieve in-memory computing, thereby revolutionizing traditional computer architecture.
[0005] However, circuits based on magnetic tunnel memory are still in the research stage and face challenges such as how to integrate computing functions into magnetic tunnel memory cells, as well as poor computing performance and high power consumption. Summary of the Invention
[0006] To address the challenges of integrating computational functions into magnetic tunnel memory units in existing magnetic tunnel memory-based circuits, as well as the issues of poor computational performance and high power consumption, this invention provides a design method and multiplier based on magnetic tunnel memory-based multipliers. This method effectively integrates computational functions into magnetic tunnel memory units and solves the problems of poor computer computational performance and high power consumption.
[0007] To achieve the objectives of this invention, the following technical solution is adopted:
[0008] A method for designing a multiplier based on magnetic tunneling and memory integration includes the following steps:
[0009] S1: Construct an AND gate circuit combining MTJ and CMOS, and perform AND operations using the MTJ and CMOS combined AND gate circuit;
[0010] S2: Construct an AND gate array using the MTJ and CMOS combined AND gate circuit, and perform partial product calculation of the multiplier based on the AND operation result of each MTJ and CMOS combined AND gate circuit in the AND gate array;
[0011] S3: Introduce a CSA array and CPA to form a carry-retaining multiplier. Use the carry-retaining multiplier to receive the partial product calculation results of the multipliers in the AND gate array, and perform carry-retaining multiplication operations based on the partial product calculation results of the multipliers.
[0012] Wherein, MTJ represents magnetic tunnel junction, CMOS represents complementary metal-oxide semiconductor, CSA represents carry-hold adder, and CPA represents ripple carry adder.
[0013] According to the above technical solution, the AND operation is performed using the combined MTJ and CMOS AND gate circuit; further, an AND gate array is constructed using the combined MTJ and CMOS AND gate circuit, and partial product calculation of the multiplier is performed based on the AND operation result of each MTJ and CMOS combined AND gate circuit in the AND gate array; a CSA array and CPA are introduced to form a carry-retaining multiplier, which receives the partial product calculation result of the multipliers in the AND gate array, and performs carry-retaining multiplication operation based on the partial product calculation result of the multipliers. The multiplier design method based on magnetic tunnel junction storage and computation provided by this invention can effectively integrate computing functions into the magnetic tunnel memory unit and solve the problems of poor computer computing performance and high power consumption.
[0014] The MTJ and CMOS combined AND gate circuit includes: output nodes AND and NAND, clock signal node CLK, a sensitive amplifier, a logic network unit, and an evaluation transistor unit. The sensitive amplifier includes two symmetrical transistor units: a first transistor unit and a second transistor unit. Each transistor unit includes two opposing transistors. The first transistor unit includes transistors P1 and P2, and the second transistor unit includes transistors P3 and P4. The source of transistor P1 is connected to the source of transistors P2, P3, and P4. The gate of transistor P1 and the gate of transistor P4 are connected to the clock signal node CLK. The drains of transistors P1 and P2 are both connected to the output node NAND. The drains of transistors P3 and P4 are both connected to the output node AND. The gate of transistor P2 is also connected to the drain of transistor P3. It also includes two transistors in opposite directions: the fifth transistor N1 and the sixth transistor N2. The source of the fifth transistor N1 is connected to the output node NAND, the drain of transistor P1 and the drain of transistor P2. The source of the sixth transistor N2 is connected to the output node AND, the drain of transistor P3 and the drain of transistor P4.
[0015] The logic network unit includes transistors N4, N5, N6, MTJ1, and MTJ2. The gate of transistor N4 is connected to the external signal input port A. The source of transistor N4 is connected to the drain of transistor N1. The drain of transistor N4 is connected to the source of MTJ1. Transistors N5 and N6 form two opposing structures. The sources of transistors N5 and N6 are connected to the drain of transistor N2. The gate of transistor N5 is connected to the external signal input port -A. The gate of transistor N6 is connected to the external signal input port A. The drains of transistors N5 and N6 are both connected to the source of MTJ2. The drain of MTJ1 is connected to the external signal input port BL. The drain of MTJ2 is connected to the external signal input port BLB.
[0016] The evaluation transistor unit includes evaluation transistor N3. The source of evaluation transistor N3 is connected to the gate of magnetic tunnel junction MTJ1 and the gate of magnetic tunnel junction MTJ2. The gate of evaluation transistor N3 is connected to the clock signal node CLK. The drain of evaluation transistor N3 is connected to the ground terminal.
[0017] According to the above technical solution, the MTJ is non-volatile, and the CMOS device has high integration. The energy required to change the electron spin is only a small fraction of the energy required to move the electron charge. Furthermore, by combining the MTJ and CMOS with an AND gate circuit, the computing function can be better integrated into the magnetic tunnel memory unit. The designed MTJ and CMOS combined AND gate circuit is used for AND operation. An AND gate array is built using the MTJ and CMOS combined AND gate circuit. Based on the AND operation result of the MTJ and CMOS combined AND gate circuit, partial product calculation of the multiplier can be performed, which can better solve the problems of poor computing performance and high power consumption.
[0018] Furthermore, the specific process of constructing the MTJ and CMOS combined AND gate circuit in step S1, and performing AND operations using the MTJ and CMOS combined AND gate circuit, is as follows:
[0019] S11: Based on the aforementioned sensitive amplifier and evaluation transistor unit, a pre-charge unit is formed;
[0020] S12. Based on the value of the clock signal node CLK, the pre-charge unit is used to control the MTJ and CMOS combined AND gate circuit to perform pre-charge;
[0021] S13: Based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, and in conjunction with the pre-charge unit and the logic network unit, control the MTJ and CMOS combined AND gate circuit to perform AND operation.
[0022] The specific process of pre-charging the MTJ and CMOS combined AND gate circuit according to the value of the clock signal node CLK in step S12 is as follows:
[0023] When the clock signal node CLK = 0, transistors P1, P4, N1 and N2 in the precharge unit are turned on, while transistors P2, P3 and N3 are turned off. The precharge unit controls the MTJ and CMOS combined AND gate circuit to perform precharge to reach the power supply voltage VDD.
[0024] The specific process of controlling the MTJ and CMOS combined AND gate circuit to perform AND operation based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, combined with the pre-charge unit and the logic network unit, as described in step S13 is as follows:
[0025] When the MTJ and CMOS combined AND gate circuit is precharged to the power supply voltage VDD, the clock signal node CLK=1, the evaluation transistor N3 is turned on, the transistors P1 and P4 are turned off, the output nodes AND and NAND are discharged through the evaluation transistor N3 and the logic network unit, the output nodes AND or NAND are discharged to GND, the magnetic tunnel junction MTJ1 is in an antiparallel state, and the magnetic tunnel junction MTJ2 is in a parallel state.
[0026] When transistors P2 and N2 are turned on, and transistors P3 and N1 are turned off, the output node AND continues to discharge to GND, the output node NAND stops discharging, the output node AND = 0, and the output node NAND = 1.
[0027] According to the above technical solution, a pre-charge unit is formed by utilizing the sensitive amplifier and evaluation transistor unit in the MTJ and CMOS combined AND gate circuit. Based on the value of the clock signal node CLK, the pre-charge unit controls the MTJ and CMOS combined AND gate circuit to perform pre-charge. Based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, the pre-charge unit and logic network unit are combined to control the MTJ and CMOS combined AND gate circuit to perform AND operation. By utilizing the mutual cooperation of the various components in the MTJ and CMOS combined AND gate circuit, the AND operation result required for the partial product calculation of the multiplier can be obtained more effectively.
[0028] Furthermore, the specific process of constructing an AND gate array using the MTJ and CMOS combined AND gate circuit described in step S2 is as follows:
[0029] The MTJ and CMOS are combined and packaged into an AND gate circuit, and multiple AND cells are connected to form an AND gate array. The process satisfies:
[0030] The input signals of the AND unit include: clock signal CLK, multiplier A, and signals BL and BLB; the output signal includes: AND.
[0031] Transistors M1 and M2 and a write enable terminal EN are introduced. The ports of multiple signals BL are connected to the drains of multiple transistors M1, the ports of multiple signals BLB are connected to the drains of multiple transistors M2, the ports of multiple write enable terminals EN are connected to the gates of multiple transistors M1 and M2, the sources of multiple transistors M1 are connected to the signal BL terminals of multiple next AND cells in the same column, and the sources of multiple transistors M2 are connected to the signal BLB terminals of multiple next AND cells in the same column, forming an AND gate array of multiple AND cells connected together.
[0032] The specific process of calculating the partial product of the multiplier based on the AND operation result using an AND gate array, as described in step S2, is as follows:
[0033] Using the MTJ and CMOS combined structure, the value of the multiplicand B of the multiplier is written into the MTJ for storage. The clock signal node CLK is set to 0, and all AND cells in the AND gate array are precharged to the power supply voltage VDD. Then the clock signal node CLK is set to 1, and all AND cells in the AND gate array are used for AND operation.
[0034] Based on the AND operation result, the AND gate array is used to perform a partial product calculation on the multiplier A and the multiplicand B, and the partial product calculation result is transmitted to the CSA array.
[0035] The specific process of writing the value of the multiplicand B of the multiplier into the MTJ for storage using the combined MTJ and CMOS structure is as follows:
[0036] Set clock signal node CLK = 1, and store the multiplicand B according to the states of magnetic tunnel junctions MTJ1 and MTJ2. The process satisfies:
[0037] With signals BL=1 and BLB=0, magnetic tunnel junction MTJ1 is in a parallel state, magnetic tunnel junction MTJ2 is in an antiparallel state, and the multiplicand B is stored in MTJ.
[0038] According to the above technical solution, by encapsulating the MTJ and CMOS combined AND gate circuit into an AND unit, connecting the electrodes of each component in the multiple AND units, introducing transistors M1 and M2 and write enable EN, and using multiple signals BL and BLB to connect with transistors M1 and M2, an AND gate array composed of multiple AND units is formed. At the same time, using the MTJ and CMOS combined structure, the value of the multiplicand B required for the partial product calculation of the multiplier is written into the MTJ for storage, which can avoid frequent memory access operations on the multiplicand. The AND gate array is used to perform the partial product calculation of the multiplier based on the AND operation result of the MTJ and CMOS combined AND gate circuit, and the partial product calculation result of the multiplier is transmitted to the CSA array through the AND gate array.
[0039] Further, in step S3, the specific process of using the CSA array to receive the partial product calculation results of the multipliers in the AND gate array, and performing carry-preserving multiplication operations using the CSA array and CPA based on the partial product calculation results of the multipliers is as follows:
[0040] The CSA array receives the partial product calculation results of the multipliers in the AND gate array. Based on the partial product calculation results of the multipliers, the FA and HA units in the CSA array are used to perform carry-retaining addition. Based on the carry-retaining addition result, the CPA is used to perform ripple carry addition to generate the final multiplier calculation result.
[0041] In this context, FA represents a full adder, and HA represents a half adder.
[0042] According to the above technical solution, the partial product calculation result of the multiplier transmitted by the AND gate array is received by the CSA, and the partial product calculation result of the multiplier is further carried-retaining addition operation is performed by the CSA array. The carry-retaining addition operation result is then transmitted to the CPA for ripple carry addition operation, thereby generating the final multiplier calculation result. This effectively solves the problems of poor computer computing performance and high power consumption.
[0043] A multiplier designed based on a magnetic tunneling multiplier design method includes:
[0044] MTJ and CMOS are combined with AND gate circuits to perform AND operations;
[0045] An AND gate array formed by multiple MTJ and CMOS combined AND gate circuits is used for partial product calculation of the multiplier;
[0046] The carry-retaining multiplier circuit is used to perform carry-retaining multiplication on the partial product calculation result of the multiplier to produce the final multiplication result.
[0047] According to the above technical solution, the AND operation is performed using MTJ and CMOS AND gate circuits, and multiple MTJ and CMOS combined AND gate circuits are used to form an AND gate array. Based on the AND operation result of the MTJ and MCOS combined AND gate circuit, the partial product calculation of the multiplier is performed. Furthermore, through the carry-retaining multiplication circuit, the carry-retaining multiplication operation is performed on the partial product calculation result of the multiplier to produce the final multiplier calculation result. This effectively integrates the computing function into the magnetic tunnel memory unit and solves the problems of poor computing performance and high power consumption of computers.
[0048] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0049] This invention proposes a multiplier design method and multiplier based on magnetic tunneling memory integration. It involves constructing an MTJ / CMOS combined AND gate circuit and performing AND operations using this circuit. Further, it utilizes the MTJ / CMOS combined AND gate circuit to construct an AND gate array, and performs partial product calculations based on the AND operation results of each MTJ / CMOS combined AND gate circuit within the array. A CSA array and CPA are introduced to form a carry-retaining multiplier, which receives the partial product calculation results from the multipliers in the AND gate array and performs carry-retaining multiplication based on these results. This invention provides a multiplier design method based on magnetic tunneling memory integration, effectively integrating computational functions into a magnetic tunneling memory unit, solving the problem of frequent memory access to the multiplicand, and addressing the issues of poor computer performance and high power consumption. Attached Figure Description
[0050] Figure 1 A flowchart illustrating a multiplier design method based on magnetic tunneling and memory integration, provided for embodiments of this application;
[0051] Figure 2 The circuit diagram of the combination of MTJ and CMOS provided in the embodiments of this application;
[0052] Figure 3 This is an AND gate array diagram formed by multiple AND cells provided in the embodiments of this application;
[0053] Figure 4 The functional architecture diagram of CSA array and CPA provided in the embodiments of this application;
[0054] Figure 5 The overall structural framework diagram of the multiplier designed based on the magnetic tunneling and storage-computation integrated multiplier design method provided in the embodiments of this application is shown. Detailed Implementation
[0055] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0056] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element present. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0057] Example 1:
[0058] This embodiment proposes a multiplier design method based on magnetic tunneling and memory integration. See [link to relevant documentation]. Figure 1 This includes the following steps:
[0059] S1: Construct an AND gate circuit combining MTJ and CMOS, and perform AND operations using the MTJ and CMOS combined AND gate circuit;
[0060] S2: Construct an AND gate array using the MTJ and CMOS combined AND gate circuit, and perform partial product calculation of the multiplier based on the AND operation result of each MTJ and CMOS combined AND gate circuit in the AND gate array;
[0061] S3: Introduce a CSA array and CPA to form a carry-retaining multiplier. Use the carry-retaining multiplier to receive the partial product calculation results of the multipliers in the AND gate array, and perform carry-retaining multiplication operations based on the partial product calculation results of the multipliers.
[0062] Wherein, MTJ represents magnetic tunnel junction, CMOS represents complementary metal-oxide semiconductor, CSA represents carry-hold adder, and CPA represents ripple carry adder.
[0063] See Figure 2In this embodiment, the constructed MTJ and CMOS combined AND gate circuit includes: output nodes AND and NAND, clock signal node CLK, a sensitive amplifier, a logic network unit, and an evaluation transistor unit. The sensitive amplifier includes two symmetrical transistor units: a first transistor unit and a second transistor unit. Each transistor unit includes two opposing transistors. The first transistor unit includes transistor P1 and transistor P2, and the second transistor unit includes transistor P3 and transistor P4. The source of transistor P1 is connected to the source of transistor P2, the source of transistor P3, and the source of transistor P4. The gates of transistors P1 and P4 are connected to the clock signal node CLK. The drains of transistors P1 and P2 are both connected to the output node NAND. The drains of transistors P3 and P4 are both connected to the output node AND. The gate of transistor P2 is also connected to the drain of transistor P3. The system also includes two transistors in opposite directions: a fifth transistor N1 and a sixth transistor N2. The source of the fifth transistor N1 is connected to the output node NAND, the drain of transistor P1, and the drain of transistor P2. The source of the sixth transistor N2 is connected to the output node AND, the drain of transistor P3, and the drain of transistor P4.
[0064] The logic network unit includes transistors N4, N5, N6, MTJ1, and MTJ2. The gate of transistor N4 is connected to the external signal input port A. The source of transistor N4 is connected to the drain of transistor N1. The drain of transistor N4 is connected to the source of MTJ1. Transistors N5 and N6 form two opposing structures. The sources of transistors N5 and N6 are connected to the drain of transistor N2. The gate of transistor N5 is connected to the external signal input port -A. The gate of transistor N6 is connected to the external signal input port A. The drains of transistors N5 and N6 are both connected to the source of MTJ2. The drain of MTJ1 is connected to the external signal input port BL. The drain of MTJ2 is connected to the external signal input port BLB.
[0065] The evaluation transistor unit includes evaluation transistor N3. The source of evaluation transistor N3 is connected to the gate of magnetic tunnel junction MTJ1 and the gate of magnetic tunnel junction MTJ2. The gate of evaluation transistor N3 is connected to the clock signal node CLK. The drain of evaluation transistor N3 is connected to the ground terminal.
[0066] Understandably, the MTJ and CMOS combined AND gate circuit proposed in this invention is designed because the MTJ is non-volatile and the CMOS device has high integration. The energy required to change the electron spin is only a small fraction of the energy required to move the electron charge. Furthermore, the MTJ and CMOS combined AND gate circuit can better integrate computing functions into the magnetic tunnel memory cell. The designed MTJ and CMOS combined AND gate circuit is used for AND operations. An AND gate array is built using the MTJ and CMOS combined AND gate circuit. Based on the AND operation results of the MTJ and CMOS combined AND gate circuit, partial product calculation of the multiplier can be performed, which can better solve the problems of poor computing performance and high power consumption.
[0067] Example 2:
[0068] In this embodiment, the implementation method for designing a multiplier using the MTJ and CMOS combined AND gate circuit designed in Embodiment 1 is as follows:
[0069] The specific process of constructing the MTJ and CMOS combined AND gate circuit in step S1, and performing AND operations using the MTJ and CMOS combined AND gate circuit, is as follows:
[0070] S11: Based on the aforementioned sensitive amplifier and evaluation transistor unit, a pre-charge unit is formed;
[0071] S12. Based on the value of the clock signal node CLK, the pre-charge unit controls the MTJ and CMOS combined AND gate circuit to perform pre-charge, specifically as follows:
[0072] When the clock signal node CLK = 0, transistors P1, P4, N1 and N2 in the precharge unit are turned on, while transistors P2, P3 and N3 are turned off. The precharge unit controls the MTJ and CMOS combined AND gate circuit to perform precharge to reach the power supply voltage VDD.
[0073] S13: Based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, and in conjunction with the pre-charge unit and the logic network unit, control the MTJ and CMOS combined AND gate circuit to perform an AND operation. The specific process is as follows:
[0074] When the MTJ and CMOS combined AND gate circuit is precharged to the power supply voltage VDD, the clock signal node CLK=1, the evaluation transistor N3 is turned on, the transistors P1 and P4 are turned off, the output nodes AND and NAND are discharged through the evaluation transistor N3 and the logic network unit, the output nodes AND or NAND are discharged to GND, the magnetic tunnel junction MTJ1 is in an antiparallel state, and the magnetic tunnel junction MTJ2 is in a parallel state.
[0075] When transistors P2 and N2 are turned on, and transistors P3 and N1 are turned off, the output node AND continues to discharge to GND, the output node NAND stops discharging, the output node AND = 0, and the output node NAND = 1.
[0076] For example, the operation of the MTJ and CMOS combined AND gate circuit can be explained in the following two stages.
[0077] (i) During the precharge phase, the clock signal node CLK is set to "0". In the precharge unit, transistors P1, P4, N1, and N2 are turned on, while transistors P2, P3, and evaluation transistor N3 are turned off. Output nodes NAND(OUT) and AND(OUT) are precharged to VDD or logic "1".
[0078] (ii) During the calculation phase, the clock signal node CLK becomes "1", evaluation transistor N3 is turned on, and transistors P1 and P4 are turned off. Output nodes AND and NAND discharge through evaluation transistor N3 and the logic network cell. In the logic network cell, transistors N4 and N6 are turned on, while transistor N5 is turned off. Therefore, both output nodes NAND and AND have a path to discharge to GND. However, the output discharge process will depend on the resistance provided by the left branch (LB) and the right branch (RB). Since magnetic tunnel junction MTJ1 is in an antiparallel (AP) state and magnetic tunnel junction MTJ2 is in a parallel (P) state, the resistance of magnetic tunnel junction MTJ1 (RMTJ1) is higher than the resistance of magnetic tunnel junction MTJ2 (RMTJ2), i.e., RMTJ1 > RMTJ2.
[0079] Therefore, even if the left branch (LB) and right branch (RB) begin discharging to GND simultaneously, the discharge rate of output node NAND is slower than that of output node AND. Because output node AND discharges faster, it crosses the threshold voltage of transistor P2, turning it on. Consequently, the gate terminal of transistor P3 is pre-charged to VDD, thus turning it off. Simultaneously, the gates of output node NAND and transistor N2 are pre-charged to VDD, allowing output node AND to continue discharging to GND. When output node AND crosses the threshold voltage of transistor N1, N1 is turned off. Therefore, the discharge path from output node NAND to GND stops discharging. However, transistor N2 remains fully on, facilitating the discharge of output node AND to GND. Therefore, output nodes AND = '0' and NAND = '1' can be achieved simultaneously.
[0080] Understandably, a pre-charge unit is formed by utilizing the sensitive amplifier and evaluation transistor unit in the MTJ and CMOS combined AND gate circuit. Based on the value of the clock signal node CLK, the pre-charge unit controls the MTJ and CMOS combined AND gate circuit to perform pre-charge. Based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, combined with the pre-charge unit and logic network unit, the MTJ and CMOS combined AND gate circuit is controlled to perform AND operation. By utilizing the mutual cooperation of the various components in the MTJ and CMOS combined AND gate circuit, the AND operation result required for the partial product calculation of the multiplier can be obtained more effectively.
[0081] See Figure 3 The specific process of constructing an AND gate array using the MTJ and CMOS combination AND gate circuit described in step S2 is as follows:
[0082] The MTJ and CMOS are combined and packaged into an AND gate circuit, and multiple AND cells are connected to form an AND gate array. The process satisfies:
[0083] The input signals of the AND unit include: clock signal CLK, multiplier A, and signals BL and BLB; the output signal includes: AND.
[0084] Transistors M1 and M2 and a write enable terminal EN are introduced. The ports of multiple signals BL are connected to the drains of multiple transistors M1, the ports of multiple signals BLB are connected to the drains of multiple transistors M2, the ports of multiple write enable terminals EN are connected to the gates of multiple transistors M1 and M2, the sources of multiple transistors M1 are connected to the signal BL terminals of multiple next AND cells in the same column, and the sources of multiple transistors M2 are connected to the signal BLB terminals of multiple next AND cells in the same column, forming an AND gate array of multiple AND cells connected together.
[0085] The specific process of calculating the partial product of the multiplier based on the AND operation result using an AND gate array, as described in step S2, is as follows:
[0086] Using the MTJ and CMOS combined structure, the value of the multiplicand B of the multiplier is written into the MTJ for storage. The clock signal node CLK is set to 0, and all AND cells in the AND gate array are precharged to the power supply voltage VDD. Then the clock signal node CLK is set to 1, and all AND cells in the AND gate array are used for AND operation.
[0087] Based on the AND operation result, the AND gate array is used to perform a partial product calculation on the multiplier A and the multiplicand B, and the partial product calculation result is transmitted to the CSA array.
[0088] The specific process of writing the value of the multiplicand B of the multiplier into the MTJ for storage using the combined MTJ and CMOS structure is as follows:
[0089] Set clock signal node CLK = 1, and store the multiplicand B according to the states of magnetic tunnel junctions MTJ1 and MTJ2. The process satisfies:
[0090] When signals BL=1 and BLB=0, magnetic tunnel junction MTJ1 is in a parallel state, magnetic tunnel junction MTJ2 is in an antiparallel state, and the multiplicand B is stored in MTJ.
[0091] For example, see Figure 3 ,Will Figure 2 The MTJ and CMOS combination is packaged into a single AND gate unit. Multiple ADN units are connected to form an AND gate array, the process of which is as follows:
[0092] Figure 3 The AND unit shown provides input signals CLK, A, BL, and BLB, and an output signal AND. Multiple copies of this AND unit can be linked together to form... Figure 3The array is shown. Its specific connection relationship is illustrated using the first column of the array as an example, with signal BL... <0> Connect the drain of transistor M1, signal BLB <0> Connect the drain of transistor M2, signal EN <0> The gates of transistors M1 and M2 are connected. Transistor M1 is connected to the BL terminal of this AND cell, and the source of transistor M2 is connected to the BLB terminal of this AND cell. Input signal A <7> To A <0> Connect the A ports of the AND units in each row. For the outputs of the AND units, taking the first column as an example, from top to bottom, connect the AND ports of the AND gates to CSA arrays X7Y0, X6Y0, X5Y0, X4Y0, X3Y0, X2Y0, X1Y0, and X0Y0 respectively. Taking the first row as an example, from left to right, connect the AND ports of the AND gates to CSA arrays X7Y0, X7Y1, X7Y2, X7Y3, X7Y4, X7Y5, X7Y6, and X7Y7 respectively.
[0093] The partial product calculation process of the AND gate array with respect to the multiplier is as follows:
[0094] See Figure 3 Here, we take an 8x8 AND gate array multiplier as an example to obtain the partial product of all 64 multipliers. This array has 8 rows and 8 columns, containing 64 AND units. Multiplier A <7> A <6> To A <0> The 8-bit input data A of the multiplier is transmitted through signal BL. <7> BL <6> To BL <0> The 8-bit multiplicand B of the multiplier can be stored in MTJ. Before multiplication, the multiplicand B needs to be written to MTJ. The write operation is as follows: set CLK to 1 and control the write enable EN. <7> EN <6> To EN <0> A write operation can be performed on any one bit of the 8-bit data B (the second method of writing is as follows: assuming the multiplicand B = 1 is to be written into MTJ, let signal BL = 1 and signal BLB = 0. At this time, the state of magnetic tunnel junction MTJ2 will become antiparallel (AP), and the state of magnetic tunnel junction MTJ1 will become parallel (P). The state of magnetic tunnel junction MTJ1 is opposite to that of magnetic tunnel junction MTJ2 to store the data 1). When EN... <0> When = 1, it means that the 0th bit of B, i.e., B, can be modified. <0> Perform a write operation. After the write operation is complete, enable all write operations (EN). <7> EN <6> To EN <0> Set to 0.
[0095] After the write operation is complete, the partial product calculation of the multipliers can be performed. Similar to the calculation process of AND operation between a single MTJ and CMOS combined AND gate circuit, the clock signal node CLK is set to 0, and the AND gate array is in the pre-charge phase. The output nodes of all AND gate units will be pre-charged to the power supply voltage VDD. At this time, the clock signal node CLK = 1, and the calculation phase begins. All AND gate units output the calculated results, and the calculated partial product results of the 64 multipliers are sent to the CSA array for accumulation.
[0096] It can be understood that by encapsulating the MTJ and CMOS combination gate circuit into an AND cell, connecting the electrodes of each component in multiple AND cells, introducing transistors M1 and M2 and write enable EN, and using multiple signals BL and BLB to connect with transistors M1 and M2, an AND gate array composed of multiple AND cells is formed. At the same time, by using the MTJ and CMOS combination structure, the value of the multiplicand B required for the partial product calculation of the multiplier is written into the MTJ for storage, which can avoid frequent memory access operations on the multiplicand. The partial product calculation of the multiplier is performed based on the AND operation result of the MTJ and CMOS combination gate circuit using the AND gate array, and the partial product calculation result of the multiplier is transmitted to the CSA array through the AND gate array.
[0097] See Figure 4 The specific process of receiving the partial product calculation result of the multipliers in the AND gate array using the CSA array in step S3, and performing carry-preserving multiplication operation using the CSA array and CPA based on the partial product calculation result of the multipliers, is as follows:
[0098] The CSA array receives the partial product calculation results of the multipliers in the AND gate array. Based on the partial product calculation results of the multipliers, the FA and HA units in the CSA array are used to perform carry-retaining addition. Based on the carry-retaining addition result, the CPA is used to perform ripple carry addition to generate the final multiplier calculation result.
[0099] In this context, FA represents a full adder, and HA represents a half adder.
[0100] For example, a carry-preserving multiplier consists of a CSA array and a CPA. The basic units of the carry-preserving array are FA and HA. FA consists of three inputs (multiplier A, multiplicand B, and CI) and two outputs (S and Co), where CI is the carry input, S is the sum output, and Co is the carry output. HA has only two inputs (multiplier A and multiplicand B) and two outputs (S and Co). Each stage of the CSA array generates a sum and a carry output, which serve as the input for the next stage. Finally, the result calculated by the CSA array is sent to the CPA to produce the final multiplication result.
[0101] Understandably, by receiving the partial product calculation result of the multiplier transmitted by the AND gate array through the CSA, performing further carry-preserving addition operation on the partial product calculation result of the multiplier using the CSA array, and transmitting the carry-preserving addition operation result to the CPA for ripple carry addition operation, the final multiplier calculation result is generated, which effectively solves the problems of poor computer computing performance and high power consumption.
[0102] This embodiment proposes a multiplier design method and multiplier based on magnetic tunneling memory integration. It constructs an MTJ / CMOS combined AND gate circuit and performs AND operations using this circuit. Further, it constructs an AND gate array using the MTJ / CMOS combined AND gate circuit, and performs partial product calculations based on the AND operation results of each MTJ / CMOS combined AND gate circuit within the array. A CSA array and CPA are introduced to form a carry-retaining multiplier. This carry-retaining multiplier receives the partial product calculation results from the multipliers in the AND gate array and performs carry-retaining multiplication operations based on these results. This invention provides a multiplier design method based on magnetic tunneling memory integration, effectively integrating computational functions into a magnetic tunneling memory unit, solving the problem of frequent memory access operations on the multiplicand, and addressing the issues of poor computer performance and high power consumption.
[0103] Example 3:
[0104] A multiplier designed based on a magnetic tunneling-based multiplier design method, see [link to relevant documentation]. Figure 5 ,include:
[0105] MTJ and CMOS are combined with AND gate circuits to perform AND operations;
[0106] An AND gate array formed by multiple MTJ and CMOS combined AND gate circuits is used for partial product calculation of the multiplier;
[0107] The carry-retaining multiplier circuit is used to perform carry-retaining multiplication on the partial product calculation result of the multiplier to produce the final multiplication result.
[0108] Understandably, by using MTJ and CMOS AND gates to perform AND operations, and by forming an AND gate array using multiple MTJ and CMOS combined AND gates, the partial product calculation of the multiplier is performed based on the AND operation result of the MTJ and MCOS combined AND gate. Furthermore, through a carry-retaining multiplication circuit, the carry-retaining multiplication operation is performed on the partial product calculation result of the multiplier to produce the final multiplication result. This effectively integrates the computing function into the magnetic tunnel memory unit and solves the problems of poor computing performance and high power consumption in computers.
[0109] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent or equivalent procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method for designing a multiplier based on magnetic tunneling and memory integration, characterized in that, Includes the following steps: S1: Construct an MTJ and CMOS combined AND gate circuit, and perform AND operations using the MTJ and CMOS combined AND gate circuit; the MTJ and CMOS combined AND gate circuit includes: output nodes AND and NAND, clock signal node CLK, sensitive amplifier, logic network unit, and evaluation transistor unit. The sensitive amplifier includes two symmetrical transistor units: a first transistor unit and a second transistor unit. Each transistor unit includes two opposing transistors. The first transistor unit includes transistor P1 and transistor P2, and the second transistor unit includes transistor P3 and transistor P4. The source of transistor P1 is connected to the source of transistor P2, and the source of transistor P3 is connected to the source of transistor P4. The source of transistor P1 and the source of transistor P4 are both connected. The gate of transistor P1 and the gate of transistor P4 are connected to the clock signal node CLK. The drain of transistor P1 and the drain of transistor P2 are both connected to the output node NAND. The drain of transistor P3 and the drain of transistor P4 are both connected to the output node AND. The gate of transistor P2 is also connected to the drain of transistor P3. It also includes two transistors in opposite directions: a fifth transistor N1 and a sixth transistor N2. The source of the fifth transistor N1 is connected to the output node NAND, the drain of transistor P1 and the drain of transistor P2. The source of the sixth transistor N2 is connected to the output node AND, the drain of transistor P3 and the drain of transistor P4. The logic network unit includes transistors N4, N5, N6, MTJ1, and MTJ2. The gate of transistor N4 is connected to the external signal input port A. The source of transistor N4 is connected to the drain of transistor N1. The drain of transistor N4 is connected to the source of MTJ1. Transistors N5 and N6 form two opposing structures. The sources of transistors N5 and N6 are connected to the drain of transistor N2. The gate of transistor N5 is connected to the external signal input port -A. The gate of transistor N6 is connected to the external signal input port A. The drains of transistors N5 and N6 are both connected to the source of MTJ2. The drain of MTJ1 is connected to the external signal input port BL. The drain of MTJ2 is connected to the external signal input port BLB. The evaluation transistor unit includes evaluation transistor N3. The source of evaluation transistor N3 is connected to the gate of magnetic tunnel junction MTJ1 and the gate of magnetic tunnel junction MTJ2. The gate of evaluation transistor N3 is connected to the clock signal node CLK. The drain of evaluation transistor N3 is connected to the ground terminal. S2: Construct an AND gate array using the MTJ and CMOS combined AND gate circuit, and perform partial product calculation of the multiplier based on the AND operation result of each MTJ and CMOS combined AND gate circuit in the AND gate array; S3: Introduce a CSA array and CPA to form a carry-retaining multiplier. Use the carry-retaining multiplier to receive the partial product calculation results of the multipliers in the AND gate array, and perform carry-retaining multiplication operations based on the partial product calculation results of the multipliers. Wherein, MTJ represents magnetic tunnel junction, CMOS represents complementary metal-oxide semiconductor, CSA represents carry-hold adder, and CPA represents ripple carry adder.
2. The multiplier design method based on magnetic tunneling and memory integration according to claim 1, characterized in that, The specific process of constructing the MTJ and CMOS combined AND gate circuit in step S1, and performing AND operations using the MTJ and CMOS combined AND gate circuit, is as follows: S11: Based on the aforementioned sensitive amplifier and evaluation transistor unit, a pre-charge unit is formed; S12. Based on the value of the clock signal node CLK, the pre-charge unit is used to control the MTJ and CMOS combined AND gate circuit to perform pre-charge; S13: Based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, and in conjunction with the pre-charge unit and the logic network unit, control the MTJ and CMOS combined AND gate circuit to perform AND operation.
3. The multiplier design method based on magnetic tunneling and memory integration according to claim 2, characterized in that, The specific process of pre-charging the MTJ and CMOS combined AND gate circuit according to the value of the clock signal node CLK in step S12 is as follows: When the clock signal node CLK=0, transistors P1, P4, N1 and N2 in the precharge unit are turned on, while transistors P2, evaluation transistors P3 and N3 are turned off. The precharge unit controls the MTJ and CMOS combined AND gate circuit to perform precharge to reach the power supply voltage VDD.
4. The multiplier design method based on magnetic tunneling and memory integration according to claim 3, characterized in that, The specific process of controlling the MTJ and CMOS combined AND gate circuit to perform AND operation based on the pre-charge state of the MTJ and CMOS combined AND gate circuit, combined with the pre-charge unit and the logic network unit, as described in step S13 is as follows: When the MTJ and CMOS combined AND gate circuit is precharged to the power supply voltage VDD, the clock signal node CLK=1, the evaluation transistor N3 is turned on, the transistors P1 and P4 are turned off, the output nodes AND and NAND are discharged through the evaluation transistor N3 and the logic network unit, the output nodes AND or NAND are discharged to GND, the magnetic tunnel junction MTJ1 is in an anti-parallel state, and the magnetic tunnel junction MTJ2 is in a parallel state. When transistors P2 and N2 are turned on, and transistors P3 and N1 are turned off, the output node AND continues to discharge to GND, the output node NAND stops discharging, the output node AND=0, and the output node NAND=1.
5. The multiplier design method based on magnetic tunneling and memory integration according to claim 4, characterized in that, The specific process of building an AND gate array using the MTJ and CMOS combination AND gate circuit described in step S2 is as follows: The MTJ and CMOS are combined and packaged into an AND gate circuit, and multiple AND cells are connected to form an AND gate array. The process satisfies: The input signals of the AND unit include: clock signal CLK, multiplier A, and signals BL and BLB; the output signal includes: AND. Transistors M1 and M2 and a write enable terminal EN are introduced. The ports of multiple signals BL and BLB are connected to the drains of multiple transistors M1 and M2 respectively. The ports of multiple write enable terminals EN are connected to the gates of multiple transistors M1 and M2. The sources of multiple transistors M1 are connected to the BL terminal of multiple next AND cells in the same column. The sources of multiple transistors M2 are connected to the BLB terminal of multiple next AND cells in the same column, forming an AND gate array of multiple AND cells connected together.
6. The multiplier design method based on magnetic tunneling and memory integration according to claim 5, characterized in that, The specific process of calculating the partial product of the multiplier based on the AND operation result using an AND gate array, as described in step S2, is as follows: Using the MTJ and CMOS combined structure, the value of the multiplicand B of the multiplier is written into the MTJ for storage. The clock signal node CLK is set to 0, and all AND cells in the AND gate array are precharged to the power supply voltage VDD. Then the clock signal node CLK is set to 1, and all AND cells in the AND gate array are used for AND operation. Based on the AND operation result, the AND gate array is used to perform a partial product calculation on multiplier A and multiplicand B, and the partial product calculation result is transmitted to the CSA array.
7. The multiplier design method based on magnetic tunneling and memory integration according to claim 6, characterized in that, The specific process of writing the value of the multiplicand B of the multiplier into the MTJ for storage using the combined MTJ and CMOS structure is as follows: Set clock signal node CLK=1, and store the multiplicand B according to the states of magnetic tunnel junctions MTJ1 and MTJ2. The process satisfies: When signals BL=1 and BLB=0, magnetic tunnel junction MTJ1 is in a parallel state, magnetic tunnel junction MTJ2 is in an antiparallel state, and the multiplicand B is stored in MTJ.
8. The multiplier design method based on magnetic tunneling and memory integration according to claim 7, characterized in that, The specific process of receiving the partial product calculation results of the multipliers in the AND gate array using the CSA array in step S3, and performing carry-preserving multiplication operation using the CSA array and CPA based on the partial product calculation results of the multipliers, is as follows: The CSA array is used to receive partial product calculation results of the multipliers in the AND gate array; Based on the partial product calculation result of the multiplier, carry-preserving addition operation is performed using the FA and HA cells in the CSA array; Based on the carry-preserving addition result, CPA is used to perform ripple carry addition to generate the final multiplier calculation result; In this context, FA represents a full adder, and HA represents a half adder.
9. A multiplier designed based on the multiplier design method according to any one of claims 1-8, characterized in that, include: MTJ and CMOS are combined with AND gate circuits to perform AND operations; An AND gate array formed by multiple MTJ and CMOS combined AND gate circuits is used for partial product calculation of the multiplier; The carry-retaining multiplier circuit is used to perform carry-retaining multiplication operations using the partial product calculation results of the multiplier, and produce the final multiplication result.