Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising a target layer, a plurality of lower electrodes and a top support structure, the plurality of lower electrodes being independently arranged on the target layer, the lower electrode comprising a first electrode part and a second electrode part arranged on the first electrode part, the second electrode part extending to a space between adjacent lower electrodes; the top support structure comprising a first support part arranged between the second electrode parts and a second support part arranged above the second electrode parts, the top support structure and the second electrode part being snap-connected. The snap-connection of the top support structure and the second electrode part improves the support force of the top support structure on the top of the lower electrode, thereby improving the structural stability of the lower electrode, reducing the risk of tilting, collapsing and deforming of the lower electrode, and improving the product yield and product quality of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As the integration density of Dynamic Random Access Memory (DRAM) increases, the size of memory nodes and plate area continue to decrease, but the demand for DRAM's charge storage capacity is increasing. To meet the charge storage capacity requirements of DRAM, the height of capacitors can only be continuously increased. However, the increased capacitor height leads to a decrease in the structural stability of the capacitors, increasing the risk of capacitor tipping over.

[0003] To reduce the risk of capacitors tipping over, a support layer is usually used to support the middle and top areas of the capacitor. However, current support layers, especially the top support layer, are not very effective at supporting capacitors. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem that the support layer in the existing technology provides poor support for the capacitor.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor structure comprising:

[0006] Target layer;

[0007] Multiple lower electrodes are independently disposed on the target layer. Each lower electrode includes a first electrode portion and a second electrode portion disposed on the first electrode portion. The second electrode portion extends into the space between adjacent lower electrodes.

[0008] A top support structure, comprising a first support portion disposed between the second electrode portions and a second support portion disposed above the second electrode portions, wherein the top support structure and the second electrode portions are snap-fitted together.

[0009] In one embodiment, the second electrode portion includes a connecting portion and a protrusion. The connecting portion is disposed on the top surface of the first electrode portion, and the protrusion is disposed at one end of the connecting portion away from the first electrode portion. The connecting portion includes a first arc surface, and the protrusion extends from the first arc surface into the space between adjacent lower electrodes. The protrusion includes a second arc surface disposed between adjacent lower electrodes.

[0010] The first support portion of the top support structure includes a first portion disposed between the connecting portions and a second portion disposed between the protrusions, wherein the size of the first portion is larger than the size of the second portion.

[0011] In one embodiment, the projection of the first arc surface onto the target layer falls within the projection of the top edge of the first electrode portion onto the target layer;

[0012] The first arc surface and the second arc surface are parallel to each other along the radial direction of the lower electrode.

[0013] In one embodiment, the protrusion includes a third arc surface connected to the second arc surface;

[0014] For two adjacent lower electrodes, the second arc surfaces of the protrusions are arranged opposite each other, and the distance between the second arc surfaces is less than the distance between the first electrode posts; or, the third arc surfaces of the protrusions are arranged opposite each other, and the distance between the third arc surfaces is greater than the distance between the first electrode posts.

[0015] In one embodiment, the connecting portion further includes a fourth arc surface connected to the first arc surface, and the fourth arc surface and the third arc surface are located on the same arc surface.

[0016] Secondly, the present invention provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0017] Provide the target layer;

[0018] A stacked structure is formed on the target layer;

[0019] An initial electrode is formed in the stacked structure. The initial electrode includes a first pillar disposed on the target layer and a second pillar connected to the first pillar. The radial dimension of the second pillar is larger than the radial dimension of the first pillar.

[0020] A portion of the stacked structure is removed to form a first trench between the initial electrodes, the first trench exposing the sidewalls of the second pillar and a portion of the sidewalls at the top of the first pillar;

[0021] A top support material layer is formed, which fills the first trench and covers the top surface of the second column;

[0022] The top support material layer is graphically visualized, and the top support material layer and part of the initial electrode are etched to the target height. The etched and retained initial electrode forms the lower electrode, and the etched and retained top support material layer forms the top support structure.

[0023] The lower electrode includes a first electrode portion located below the target height and a second electrode portion located above the target height. The top support structure includes a first support portion disposed between the second electrode portions and a second support portion disposed above the second electrode portions. The top support structure and the second electrode portions are snap-fitted together.

[0024] In one embodiment, forming an initial electrode in the stacked structure includes:

[0025] A capacitor hole is formed, which penetrates the stacked structure. Along the direction from the target layer to the stacked structure, the capacitor hole includes a first hole and a second hole connected in sequence, and the size of the second hole is larger than the diameter of the first hole.

[0026] The initial electrode is formed in the capacitor hole.

[0027] In one embodiment, forming a capacitor hole includes:

[0028] An initial hole is formed, which penetrates the stacked structure and exposes the target layer;

[0029] A portion of the top structure of the stacked structure is removed along the radial direction of the initial hole to increase the size of the top of the initial hole, thereby forming the capacitor hole.

[0030] In one embodiment, before removing a portion of the top structure of the stacked structure along the radial direction of the initial hole, the process includes:

[0031] A protective layer is formed, which covers the bottom wall of the initial hole and a portion of the sidewall of the initial hole, and exposes a portion of the top sidewall of the initial hole.

[0032] In one embodiment, the target height is lower than the bottom surface of the top support material layer.

[0033] The semiconductor structure and its fabrication method of the present invention have the following beneficial effects:

[0034] The semiconductor structure of the present invention improves the structure and shape of the second electrode portion at the top of the lower electrode, and at the same time improves the structure of the top support structure, increases the thickness of the top support structure, increases the contact area between the top support structure and the lower electrode, and improves the support capacity of the top support structure for the lower electrode, thereby improving the stability of the semiconductor structure and reducing the risk of the semiconductor structure tipping over, collapsing, or deforming.

[0035] The semiconductor structure fabrication method of the present invention includes an initial electrode formed in a stacked structure comprising a first pillar and a second pillar disposed on the first pillar, wherein the size of the second pillar is larger than the size of the first pillar. Then, a top support material layer is formed to cover the second pillar, thereby optimizing the morphology and structure of the second electrode portion at the top of the formed lower electrode. At the same time, the structure of the top support structure is optimized. The projection of the top support structure on a plane perpendicular to the top surface of the target layer is a structure similar to an "I". This increases the contact area between the top support structure and the lower electrode, improves the support effect of the top support structure on the lower electrode, thereby improving the stability of the semiconductor structure and reducing the risk of tilting, collapse, and deformation of the semiconductor structure. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a top view of a semiconductor structure provided in an example embodiment.

[0038] Figure 2 This is a cross-sectional view along line AA of a semiconductor structure provided in an example embodiment.

[0039] Figure 3 for Figure 2 A magnified view of a portion of point A in the middle.

[0040] Figure 4 This is a schematic diagram of the structure of the second electrode section provided in an example embodiment.

[0041] Figure 5 This is a cross-sectional view along line AA of a semiconductor structure provided in an example embodiment.

[0042] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure provided in an example embodiment.

[0043] Figure 7 This is a schematic diagram of a stacked structure formed on a target layer, provided in an example embodiment.

[0044] Figure 8 This is a schematic diagram of the initial hole after it has been formed, provided in an example embodiment.

[0045] Figure 9 This is a schematic diagram of the protective material layer after it has been formed, as provided in an example embodiment.

[0046] Figure 10 This is a schematic diagram of the protective layer after it has been formed, provided in an example embodiment.

[0047] Figure 11 This is a schematic diagram of the capacitor hole after it has been formed, provided in an example embodiment.

[0048] Figure 12 This is a schematic diagram showing the initial capacitance after it has been formed, as provided in an example embodiment.

[0049] Figure 13 This is a schematic diagram of the formation of the first trench provided in an example embodiment.

[0050] Figure 14 This is a schematic diagram of the top support material layer after it has been formed, as provided in an example embodiment.

[0051] Figure 15 This is a schematic diagram of the top support structure after it has been formed, as provided in an example embodiment.

[0052] Explanation of reference numerals in the attached figures:

[0053] 10. Target layer; 11. Substrate; 12. Dielectric material layer; 110. Bottom support layer; 120. Intermediate support layer; 20. Lower electrode; 21. First electrode portion; 22. Second electrode portion; 30. Top support structure; 30a. First patterned hole; 31. First support portion; 311. First part; 312. Second part; 32. Second support portion; 40. Connecting part; 41. First arc surface; 42. Fourth arc surface; 50. Protrusion; 51. Second arc surface; 52. Third arc surface; 60. High-K dielectric layer; 70. Upper electrode;

[0054] 200. Laminated structure; 210. Supporting material layer; 211. First supporting material layer; 212. Second supporting material layer; 213. Third supporting material layer; 220. Sacrificial layer; 221. First sacrificial layer; 222. Second sacrificial layer; 223. Third sacrificial layer; 300. Capacitor via; 301. First via; 302. Second via; 310. Initial via; 400. Protective layer; 410. Protective material layer; 500. Initial electrode; 510. First pillar; 520. Second pillar; 610. First trench; 700. Top supporting material layer;

[0055] H0, initial height; H1, first height; H2, second height; H3, third height; L1, first width; L2, second width; L3, third width; L4, fourth width. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0062] In related technologies, capacitors are typically formed in the manufacturing process of DRAM memory using the following method: A stacked structure is formed on a target layer, the stacked structure including a support material layer and a sacrificial layer alternately covering the target layer. The stacked structure is etched to form capacitor vias that penetrate the stacked structure and expose a portion of the top surface of the target layer. Conductive material is filled into the capacitor vias to form a lower electrode. Then, a portion of the stacked structure is etched back to expose a portion of the top peripheral surface of the lower electrode. Next, a top support material layer is deposited to form a top support structure that covers the exposed surface of the top of the lower electrode and fills the portion of the stacked structure that was removed. The top support material layer is patterned to form a top support structure that covers a portion of the sidewalls and the top surface of the lower electrode.

[0063] In the aforementioned capacitor manufacturing process, due to the large aspect ratio of the capacitor holes, during the deposition process to fill the holes and form the lower electrode, it is easy for the conductive material to fail to completely fill the holes, resulting in air gaps in the lower electrode. Furthermore, controlling the deposition parameters cannot completely eliminate these air gaps. These air gaps reduce the structural stability of the lower electrode, necessitating control of the etch-back depth of the stacked structure. If the height difference between the etch-back stacked structure and the lower electrode is large, the resulting top support layer will be correspondingly thicker. This means the lower electrode bears a significant weight from the top support layer, and under the pressure of the top support layer, part of the lower electrode may sink into the air gaps, causing deformation. Furthermore, during the subsequent formation of the high-k dielectric layer, the high-k dielectric layer may fill the air gaps, causing it to disappear, severely impacting the capacitor's yield and quality. However, if the height difference between the etch-back stacked structure and the lower electrode is small, the resulting top support layer will be thin, failing to provide ideal support and increasing the risk of the capacitor tipping over, collapsing, or deforming.

[0064] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to... Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the semiconductor structure includes a target layer 10, a plurality of lower electrodes 20, and a top support structure 30. The plurality of lower electrodes 20 are independently disposed on the target layer 10. Each lower electrode 20 includes a first electrode portion 21 and a second electrode portion 22 disposed on the first electrode portion 21, with the second electrode portion 22 extending into the space between adjacent lower electrodes 20. The top support structure 30 includes a first support portion 31 disposed between the second electrode portions 22 and a second support portion 32 disposed above the second electrode portions 22. The top support structure 30 and the second electrode portions 22 are snap-fitted together.

[0065] In this embodiment, the snap-fit ​​connection between the top support structure 30 and the second electrode portion 22 in the semiconductor structure increases the support force of the top support structure 30 on the top of the lower electrode 20, thereby improving the structural stability of the lower electrode 20, reducing the risk of the lower electrode 20 tipping over, collapsing, or deforming, and improving the product yield and product quality of the semiconductor structure.

[0066] Reference Figure 2 The target layer 10 can be a substrate, which can be a semiconductor substrate. Alternatively, the target layer 10 can be a material layer formed on a semiconductor substrate, and one or more stacked semiconductor device layers can be disposed between the target layer 10 and the substrate. For example, the target layer 10 can be a metal layer disposed on the substrate, and the material of the metal layer can include tungsten, titanium, etc.

[0067] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the second electrode portion 22 includes a connecting portion 40 and a protrusion 50. The connecting portion 40 is disposed on the top surface of the first electrode portion 21, and the protrusion 50 is disposed at the end of the connecting portion 40 away from the first electrode portion 21. The connecting portion 40 includes a first arc surface 41, and the protrusion 50 extends from the first arc surface 41 into the space between adjacent lower electrodes 20. The protrusion 50 includes a second arc surface 51 disposed between adjacent lower electrodes 50. For example, the protrusion 50 may extend from the first arc surface 41 of the connecting portion 40 in the radial direction of the lower electrode 20. Thus, the distance between the second arc surfaces 51 of the protrusions 50 of some adjacent lower electrodes 20 is smaller than the distance between the first arc surfaces 41 of the connecting portions 40 of adjacent lower electrodes 20. The first support portion 31 of the top support structure 30 includes a first portion 311 disposed between the connecting portions 40 and a second portion 312 disposed between the protrusions 50. The size of the first portion 311 is larger than the size of the second portion 312.

[0068] The first portion 311 of the first support portion 31 fills the space between the connecting portions 40, at least covering a portion of the first arc surface 41 of the connecting portions 40 and filling a portion of the area between the first arc surfaces 41. It is understood that, to improve the support effect of the top support structure 30, the first portion 311 covers the portion of the first arc surface 41 of the connecting portion 40 near the protrusion 50. The second portion 312 of the first support portion 31 covers the second arc surface 51 of the protrusion 50 and fills the space between the second arc surfaces 51. The second support portion 32 is connected to the second portion 312 of the first support portion 31 and covers the top surface of the protrusion 50. Along the radial direction of the lower electrode 20, the size of the first portion 311 of the first support portion 31 is larger than the size of the second portion 312 of the first support portion 31, and the size of the second support portion 32 is larger than the size of the second portion 312 of the first support portion 31. The projection of the top support structure 30 onto a plane perpendicular to the top surface of the target layer 10 is a structure resembling an "I". The material of the top support structure 30 may include carbon-doped silicon nitride.

[0069] In this embodiment of the semiconductor structure, the second electrode portion 22 of the lower electrode 20 includes two parts: a connecting portion 40 and a protruding portion 50. The top support structure 30 is configured in an "I"-shaped structure according to the shape of the second electrode portion 22, which increases the thickness of the top support structure 30 and the contact area between the top support structure 30 and the lower electrode 20, thereby improving the support effect of the top support structure 30 on the lower electrode 20, thus improving the stability of the semiconductor structure and reducing the risk of the semiconductor structure tipping over, collapsing, or deforming.

[0070] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the first part 311 of the first support 31 has a first height H1, which is 3nm to 20nm. For example, the first height H1 can be 3nm, 5nm, 7nm, 9nm, 12nm, 15nm, 18nm or 20nm, etc.

[0071] The second part 312 of the first support 31 has a second height H2, which is 2nm to 30nm. For example, the second height H2 can be 2nm, 5nm, 9nm, 15nm, 18nm, 23nm, 28nm or 30nm, etc.

[0072] The second support part 32 has a third height H3, where (H1+H2) / 2 < H3 < 5(H1+H2).

[0073] This embodiment further increases the support force of the top support structure 30 on the lower electrode 20 by configuring the thickness of the first part 311, the second part 312, and the second support 32 of the first support part 31, thereby improving the stability and anti-tipping ability of the semiconductor structure.

[0074] In some embodiments, refer to Figure 1 , Figure 4 As shown, the projection of the first arc surface 41 onto the target layer 10 falls within the projection of the top edge of the first electrode portion 21 onto the target layer 10; the first arc surface 41 and the second arc surface 51 are parallel along the radial direction of the lower electrode 20. That is, the second arc surface 51 extends from the edge of the peripheral surface of the first electrode portion 21 toward the protrusion 50 in a direction away from the first electrode portion 21; in other words, the second arc surface 51 and the peripheral surface of the first electrode portion 21 are located on the same curved surface.

[0075] In some embodiments, refer to Figure 1 , Figure 2 As shown, the protrusion 50 includes a third arc surface 52 connected to the second arc surface 51. For two adjacent lower electrodes 20, the second arc surfaces 51 of the protrusion 50 are arranged opposite each other, and the distance between the second arc surfaces 51 is less than the distance between the first electrode posts 21; or, the third arc surfaces 52 of the protrusion 50 are arranged opposite each other, and the distance between the third arc surfaces 52 is greater than the distance between the first electrode posts 21.

[0076] Reference Figure 2 , Figure 3 Along the radial direction of the lower electrode 20, the distance between adjacent first electrode posts 21 is the first width L1, which is 10nm to 20nm. For example, the first width L1 can be 10nm, 12nm, 15nm, 18nm or 20nm.

[0077] For the two lower electrodes 20 disposed opposite to each other on the second arc surfaces 51 of the protrusions 50, the distance between the first arc surfaces 41 of the connecting portion 40 is a first width L1, and the distance between the second arc surfaces 51 of the protrusions 50 is a second width L2. The first width L1 is greater than the second width L2, and L2:L1 = 0.4-0.85:1. In this embodiment, L2:L1 = 0.4-0.8:1, and the second width L2 > 5nm, thereby avoiding the problem of short-circuiting and conducting between adjacent protrusions 50 due to the small spacing between the second arc surfaces 51, and ensuring that the semiconductor structure has good electrical performance.

[0078] In some embodiments, refer to Figure 1 , Figure 2 , Figure 4The connecting portion 40 also includes a fourth arc surface 42 connected to the first arc surface 41, and the fourth arc surface 42 and the third arc surface 52 are located on the same arc surface. For the two lower electrodes 20 disposed opposite to the third arc surface 52 of the protrusion 50, the distance between the fourth arc surface 42 (or the third arc surface 52) is a third width L3, which is greater than the first width L1. The second electrode portion 22 is disposed on the first electrode portion 21, and part of the top surface of the first electrode portion 21 is covered by the second electrode portion 22, while another part of the top surface of the first electrode portion 21 is not covered by the second electrode portion 22.

[0079] In some embodiments, refer to Figure 2 , Figure 5 As shown, the semiconductor structure also includes a bottom support layer 110, which covers the sidewall of the first electrode post 21 near the bottom region of the target layer 10 and the top surface of the target layer 10.

[0080] In some embodiments, refer to Figure 2 , Figure 5 As shown, the semiconductor structure also includes at least one intermediate support layer 110, at least one intermediate support layer 120 is disposed between the top support structure 30 and the bottom support layer 110, and at least one intermediate support layer 110 covers part of the sidewall of the first electrode post 21.

[0081] Reference Figure 2 , Figure 5 As shown, the semiconductor structure in this embodiment can be a capacitor. The semiconductor structure also includes a high-k dielectric layer 60 and an upper electrode 70. The high-k dielectric layer 60 covers the exposed surfaces of the first electrode post 21 and the second electrode post 22. The upper electrode 70 covers the high-k dielectric layer 60 and fills the unfilled areas between the lower electrodes 20. The top support structure 30 provides a good manufacturing process for the capacitor in this embodiment, preventing the capacitor area from tilting, collapsing, or deforming, thus improving the structural stability of the capacitor.

[0082] The semiconductor structure of this embodiment can be applied to memory chips, which can be used in Dynamic Random Access Memory (DRAM). However, it can also be applied to Static Random-Access Memory (SRAM), flash EPROM, ferroelectric Random-Access Memory (FRAM), magnetic Random-Access Memory (MRAM), phase-change Random-Access Memory (PRAM), etc.

[0083] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 6 As shown, Figure 6 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. The method for fabricating the semiconductor structure includes the following steps:

[0084] Step S110: Provide the target layer.

[0085] Reference Figure 7 As shown, the target layer 10 can be a substrate, which can be a semiconductor substrate. The substrate material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials with semiconductor properties, such as gallium arsenide and other III-V compounds.

[0086] Alternatively, the target layer 10 can be a material layer formed on the substrate. For example, the target layer 10 can be a material layer used to form semiconductor devices, such as a dielectric material layer or a metal layer. For example, the target layer 10 can be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited to these. One or more stacked semiconductor device layers can be disposed between the target layer 10 and the substrate, wherein each semiconductor device layer can form multiple semiconductor devices and multiple metal interconnect structures. The semiconductor devices can include at least one of metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, resistors, inductors, diodes, and optical devices.

[0087] In this embodiment, the target layer 10 is a metal layer disposed on the substrate 11. The material of the target layer 10 may include tungsten or titanium. A dielectric material layer 12 is also disposed between the target layer 10 and the substrate 11. For example, the material of the dielectric material layer 12 may include tantalum.

[0088] Step S120: Form a stacked structure on the target layer.

[0089] Reference Figure 7 As shown, the stacked structure 200 includes a support material layer 210 and a sacrificial layer 220 alternately disposed on the target layer 10. The specific number and stack height of the support material layer 210 and sacrificial layer 220 in the stacked structure 200 are set according to the height of the lower electrode 20 to be formed. In this embodiment, along the direction away from the target layer 10, the stacked structure 200 includes a first support material layer 211, a first sacrificial layer 221, a second support material layer 212, a second sacrificial layer 222, a third support material layer 213, and a third sacrificial layer 223 disposed sequentially.

[0090] The materials of the first sacrificial layer 221, the second sacrificial layer 222, and the third sacrificial layer 223 include silicon oxide or BPSG (Boro-phospho-silicate glass). The materials of the first sacrificial layer 221, the second sacrificial layer 222, and the third sacrificial layer 223 may be doped with boron or phosphorus. The materials of the first support material layer 211, the second support material layer 212, and the third support material layer 213 include any one or any combination of two or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0091] Step S130: An initial electrode is formed in the stacked structure. The initial electrode includes a first pillar disposed on the target layer and a second pillar connected to the first pillar. The radial dimension of the second pillar is larger than the radial dimension of the first pillar.

[0092] In this embodiment, forming the initial electrode in the stacked structure includes the following steps:

[0093] Step S131: Form a capacitor hole. The capacitor hole penetrates the stacked structure and extends along the direction from the target layer to the stacked structure. The capacitor hole includes a first hole and a second hole connected in sequence. The size of the second hole is larger than the diameter of the first hole.

[0094] Step S1311: Form an initial hole that penetrates the stacked structure and exposes the target layer.

[0095] Reference Figure 8 As shown, the stacked structure 200 is etched layer by layer from the top surface of the stacked structure 200 toward the target layer 10 to form an initial hole 310 that penetrates the stacked structure 200.

[0096] After the initial aperture 310 is formed, the initial aperture 310 has a fourth width L4 along the radial direction of the initial aperture 310. The fourth width L4 is 12nm to 35nm, for example, the fourth width L4 can be 12nm, 15nm, 20nm, 23nm, 26nm, 30nm, 33nm or 35nm. The retained stacked structure 200 between two adjacent initial apertures 310 has a first width L1, the first width L1 is 10nm to 20nm, for example, the first width L1 can be 10nm, 12nm, 15nm, 18nm or 20nm.

[0097] Step S1312: Form a protective layer that covers the bottom wall of the initial hole and part of the sidewall of the initial hole, and exposes part of the top sidewall of the initial hole.

[0098] The protective layer can be formed using the following methods:

[0099] First, refer to Figure 9As shown, an atomic layer deposition (ALD) process can be used to deposit a protective material layer 410, which covers the bottom wall and sidewalls of the initial hole 310 and the top surface of the third sacrificial layer 223.

[0100] Then, refer to Figure 10 As shown, the protective material layer 410 is etched from the opening of the initial hole 310 toward the target layer 10. The etching removes the protective material layer 410 covering the top surface of the third sacrificial layer 223 and part of the protective material layer 410 covering the top sidewall of the initial hole 310, exposing the top sidewall of the initial hole 310, that is, exposing part of the top structure of the third sacrificial layer 223. The etched and retained protective material layer 410 forms the protective layer 400.

[0101] The exposed portion at the top of the third sacrificial layer 223 has an initial height H0, which is 5nm to 30nm. For example, the initial height H0 can be 5nm, 10nm, 15nm, 20nm, 25nm or 30nm.

[0102] Step S1313: Remove part of the top structure of the stacked structure along the radial direction of the initial hole to increase the size of the top of the initial hole and form a capacitor hole.

[0103] Reference Figure 10 , Figure 11 As shown, the initial hole 310 is flushed with an etching solution to remove part of the third sacrificial layer 223 exposed by the protective layer 400, thereby increasing the aperture of the top of the initial hole 310 to form a capacitor hole 300. The capacitor hole 300 includes a first hole 301 and a second hole 302 connected together. The second hole 302 is located on top of the first hole 301, and the size of the second hole 302 is larger than the aperture of the first hole 301.

[0104] After the capacitor aperture 300 is formed, the third sacrificial layer 223 located between adjacent second apertures 302 has a second width L2, the first width L1 is greater than the second width L2, L2:L1 = 0.4-0.85:1, in this embodiment, L2:L1 = 0.4-0.8:1, and the second width L2 > 5 nm. The second aperture 302 of the capacitor aperture 300 has a second height H2, 40% H0 < H2 < H0. Hydrofluoric acid solution can be used as the etching solution.

[0105] Step S132: Form an initial electrode in the capacitor hole.

[0106] Reference Figure 11 , Figure 12As shown, any one of the following deposition processes can be selected: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering to deposit an electrode material layer. The electrode material layer fills the capacitor hole 300 and covers the top surface of the third sacrificial layer 223.

[0107] The electrode material layer is etched until the top surface of the third sacrificial layer 223 is exposed. The electrode material layer and the protective layer 400 located in the capacitor hole 300 together form the initial electrode 500. The initial electrode 500 includes a first pillar 510 located in the first hole 301 and a second pillar 520 located in the second hole 302. Along the radial direction of the initial electrode 500, the size of the second pillar 520 is larger than the size of the first pillar 510.

[0108] Because the second hole 302 at the top of the capacitor hole 300 has a large size, the influence of the aspect ratio of the capacitor hole 300 on the filling effect is reduced, so that the electrode material layer can fill the capacitor hole 300. The electrode material layer in the capacitor hole 300 has no air gaps. Therefore, the initial electrode 500 formed in this embodiment can fill the capacitor hole 300. The initial electrode 500 has no air gaps, and the structure of the subsequently formed lower electrode 20 is more stable and robust, while improving the charge storage capacity of the semiconductor structure.

[0109] The material of the initial electrode 500 may include at least one of a metal, a metal nitride, or a metal silicide. For example, the material of the initial electrode 500 may include at least one of a high-melting-point metal, such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo). Alternatively, the material of the initial electrode 500 may also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride. Alternatively, the material of the initial electrode 500 may include a noble metal from at least one of platinum (Pt), ruthenium (Ru), and iridium (Ir). Alternatively, the material of the initial electrode 500 may include at least one of the above noble metal oxides, such as platinum oxide (PtO), ruthenium dioxide (RuO2) and / or iridium dioxide (IrO2). For example, the material of the initial electrode 500 may include at least one of SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), and LSCO ((La,Sr)CoO3).

[0110] Step S140: Remove part of the stacked structure to form a first trench between the initial electrodes, the first trench exposing the sidewall of the second pillar and part of the sidewall of the top of the first pillar.

[0111] Reference Figure 13 As shown, etching exposes part of the third sacrificial layer 223 by the initial electrode 500, forming a first trench 610 between adjacent initial electrodes 500. The first trench 610 exposes part of the sidewall of the second pillar 520 and part of the top sidewall of the first pillar 510. That is, the bottom wall of the first trench 610 is located below the bottom wall of the second pillar 520.

[0112] In this embodiment, the height difference between the bottom wall of the first trench 610 and the bottom wall of the second column 520 is the first height H1, which is 3nm to 20nm. For example, the first height H1 can be 3nm, 5nm, 7nm, 9nm, 12nm, 15nm, 18nm or 20nm, etc.

[0113] Step S150: Form a top support material layer, which fills the first groove and covers the top surface of the second column.

[0114] Reference Figure 14 As shown, any one of the following deposition processes can be selected: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering to deposit the top support material layer 700. The top support material layer 700 covers part of the top sidewall of the first pillar 510, the sidewall of the second pillar 520, the top surface of the second pillar 520, and fills the first trench 610.

[0115] In this embodiment, the thickness of the deposited top support material layer 700 is 1.5(H1+H2) to 5(H1+H2), so that the thickness of the top support material layer 700 covering the top surface of the second column 520 after the top support material layer 700 fills the first groove 610 is sufficiently thick, so that the subsequently formed top support structure 30 has good support force.

[0116] Step S160: Graphicalize the top support material layer, etch the top support material layer and part of the initial electrode to the target height, the etched and retained initial electrode forms the lower electrode, and the etched and retained top support material layer forms the top support structure.

[0117] Reference Figure 15As shown, a mask layer (not shown) is formed on the top surface of the top support structure 30. A mask pattern for forming the first patterned hole 30a is defined on the mask layer. The top support material layer 700 and the initial electrode 500 are etched to a target height based on the mask layer. The target height is lower than the bottom surface of the top support material layer 700, so as to transfer the mask pattern into the top support material layer 700 to form the first patterned hole 30a. The etched and retained top support material layer 700 forms the top support structure 30, and the etched and retained initial electrode 500 forms the lower electrode 20.

[0118] Reference Figure 15 , combined Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the lower electrode 20 includes a first electrode portion 21 located below the target height and a second electrode portion 22 located above the target height. The top support structure 30 includes a first support portion 31 disposed between the second electrode portions 22 and a second support portion 32 disposed above the second electrode portions 22. The top support structure 30 and the second electrode portions 22 are snap-fitted together.

[0119] The semiconductor structure fabrication method of this embodiment includes an initial electrode formed in a stacked structure comprising a first pillar and a second pillar disposed on the first pillar, wherein the size of the second pillar is larger than the size of the first pillar. Then, a top support material layer is formed to cover the second pillar, thereby optimizing the morphology and structure of the second electrode portion at the top of the formed lower electrode. At the same time, the structure of the top support structure is optimized. The projection of the top support structure on a plane perpendicular to the top surface of the target layer is a structure similar to an "I". This increases the contact area between the top support structure and the lower electrode, improves the support effect of the top support structure on the lower electrode, thereby improving the stability of the semiconductor structure and reducing the risk of the semiconductor structure tipping over, collapsing, or deforming.

[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Target layer; Multiple lower electrodes are independently disposed on the target layer. Each lower electrode includes a first electrode portion and a second electrode portion disposed on the first electrode portion. The second electrode portion extends into the space between adjacent lower electrodes. A top support structure, comprising a first support portion disposed between the second electrode portions and a second support portion disposed above the second electrode portions, wherein the top support structure and the second electrode portions are snap-fitted together.

2. The semiconductor structure according to claim 1, characterized in that, The second electrode portion includes a connecting portion and a protrusion. The connecting portion is disposed on the top surface of the first electrode portion, and the protrusion is disposed at the end of the connecting portion away from the first electrode portion. The connecting portion includes a first arc surface, and the protrusion extends from the first arc surface into the space between adjacent lower electrodes. The protrusion includes a second arc surface disposed between adjacent lower electrodes. The first support portion of the top support structure includes a first portion disposed between the connecting portions and a second portion disposed between the protrusions, wherein the size of the first portion is larger than the size of the second portion.

3. The semiconductor structure according to claim 2, characterized in that, The projection of the first arc surface onto the target layer falls within the projection of the top edge of the first electrode portion onto the target layer. The first arc surface and the second arc surface are parallel to each other along the radial direction of the lower electrode.

4. The semiconductor structure according to claim 2, characterized in that, The protrusion includes a third arc surface connected to the second arc surface; For two adjacent lower electrodes, the second arc surfaces of the protrusions are arranged opposite each other, and the distance between the second arc surfaces is less than the distance between the first electrode posts; or, the third arc surfaces of the protrusions are arranged opposite each other, and the distance between the third arc surfaces is greater than the distance between the first electrode posts.

5. The semiconductor structure according to claim 4, characterized in that, The connecting part further includes a fourth arc surface connected to the first arc surface, and the fourth arc surface and the third arc surface are located on the same arc surface.

6. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes the following steps: Provide the target layer; A stacked structure is formed on the target layer; An initial electrode is formed in the stacked structure. The initial electrode includes a first pillar disposed on the target layer and a second pillar connected to the first pillar. The radial dimension of the second pillar is larger than the radial dimension of the first pillar. A portion of the stacked structure is removed to form a first trench between the initial electrodes, the first trench exposing the sidewalls of the second pillar and a portion of the sidewalls at the top of the first pillar; A top support material layer is formed, which fills the first trench and covers the top surface of the second column; The top support material layer is graphically visualized, and the top support material layer and part of the initial electrode are etched to the target height. The etched and retained initial electrode forms the lower electrode, and the etched and retained top support material layer forms the top support structure. The lower electrode includes a first electrode portion located below the target height and a second electrode portion located above the target height. The top support structure includes a first support portion disposed between the second electrode portions and a second support portion disposed above the second electrode portions. The top support structure and the second electrode portions are snap-fitted together.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, Forming an initial electrode in the stacked structure includes: A capacitor hole is formed, which penetrates the stacked structure. Along the direction from the target layer to the stacked structure, the capacitor hole includes a first hole and a second hole connected in sequence, and the size of the second hole is larger than the diameter of the first hole. The initial electrode is formed in the capacitor hole.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, Forming a capacitor hole includes: An initial hole is formed, which penetrates the stacked structure and exposes the target layer; A portion of the top structure of the stacked structure is removed along the radial direction of the initial hole to increase the size of the top of the initial hole, thereby forming the capacitor hole.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Before removing a portion of the top structure of the stacked structure along the radial direction of the initial hole, the process includes: A protective layer is formed, which covers the bottom wall of the initial hole and a portion of the sidewall of the initial hole, and exposes a portion of the top sidewall of the initial hole.

10. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The target height is lower than the bottom surface of the top support material layer.

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