Polishing methods for semiconductor process compositions and substrates

Abstract

This invention relates to a composition for semiconductor processing and a polishing method for a substrate. The composition for semiconductor processing includes: polishing particles, surface-modified with an aminosilane compound; a copper corrosion inhibitor comprising an azole compound; a copper surface protectant comprising a compound having betaine and salicyl groups or derivatives thereof; and a surfactant containing fluorine in its molecule; the surface of the surface-modified polishing particles having aminosilane groups. According to this embodiment, the polishing process can be performed more efficiently, especially when applied to polishing substrates with through electrodes, minimizing defects such as pits, corrosion, and protrusions. Furthermore, when polishing surfaces with multiple different films exposed externally, a flat polishing result can be achieved without thickness variations between the individual films.

Description

Technical Field

[0001] This embodiment relates to a composition applicable to semiconductor manufacturing and processing processes, and to a composition applicable to polishing processes for semiconductor substrates. Background Technology

[0002] Chemical mechanical polishing (CMP) is a process used in semiconductor manufacturing to planarize the surface of a wafer using a polishing pad and a paste composition. CMP involves polishing the wafer by simultaneously subjecting it to a mixed rotational and linear orbital motion using a paste composition containing a polishing agent after the polishing pad and wafer are brought into contact.

[0003] The slurry composition used in CMP processes mainly consists of polishing particles with physical effects and compounds with chemical effects, such as etchants. Therefore, the slurry composition selectively etches exposed portions of the wafer surface through physical and chemical actions to perform a more optimized and extensive planarization process.

[0004] In copper wiring polishing, it is very important to control the polishing speed for different types of film.

[0005] When polishing copper wiring, the material to be polished includes not only the copper wiring itself, but also the barrier film and the insulating film (passivation layer). Therefore, the polishing performance varies depending on the polishing speed applied to the copper and the difference in polishing speed applied to the two different film materials.

[0006] As relevant prior art, there are Korean Patent Publication No. 10-2006-0059216 and Korean Patent No. 10-2261822, etc. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The purpose of this embodiment is to provide a semiconductor process composition and a method for manufacturing semiconductor devices that can perform polishing processes more efficiently and achieve a flat polished surface without thickness deviations between the various films when polishing a surface with multiple different films exposed to the outside.

[0009] means for solving problems

[0010] To achieve the above objectives, the semiconductor process composition according to this embodiment includes: polishing particles, surface-modified with an aminosilane compound; a copper corrosion inhibitor, comprising an azole compound; a copper surface protectant, comprising a compound having a betaine group and a salicyl group or a derivative thereof; and a surfactant containing fluorine in its molecule.

[0011] The surface of the surface-modified polishing particles may have aminosilyl groups.

[0012] The weight ratio of the azole compound to the copper surface protectant can be from 1:0.2 to 1:4.

[0013] The weight ratio of the azole compound to the surfactant can be from 1:0.001 to 1:0.2.

[0014] Based on 100 parts by weight of the polishing particles, the content of the azole compound can be from 0.02 parts by weight to 2 parts by weight.

[0015] The weight ratio of the aminosilane compound to the azole compound can be from 1:0.1 to 1:0.28.

[0016] The semiconductor process composition may include more than 1% by weight and less than 17% by weight of the polishing particles.

[0017] The semiconductor process composition can be a slurry for polishing surfaces that partially comprise each of copper, silicon nitride, and silicon oxide.

[0018] For the surface of a circular via with a diameter of 5 μm polished using the semiconductor process composition, the maximum roughness measured using an atomic force microscope (AFM) can be within 220 nm.

[0019] To achieve the above objectives, the semiconductor process composition according to this embodiment includes: polishing particles, surface-modified with an aminosilane compound; a copper corrosion inhibitor, comprising an azole compound; a copper surface protectant, comprising a compound having a betaine group and a salicyl group or a derivative thereof; and a surfactant containing fluorine in its molecule.

[0020] The copper corrosion inhibition index (Er) of the composition for semiconductor processing according to the following formula 1 can be from 8 to 15.

[0021] Form 1:

[0022]

[0023] In the first formula, indexC is the value according to the second formula below, Cab is the content (by weight%) of polishing particles contained in the entire semiconductor process composition, and Ps is the content (by weight) of aminosilane compounds in 100 parts by weight of the polishing particles.

[0024] Form 2:

[0025] IndexC=C1×6+C2×5-C3-C4×10

[0026] In the second formula, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition, C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition, C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition, and C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition.

[0027] The semiconductor process composition may further include a silicon nitride polishing enhancer, wherein the index C may be a value according to the following formula 2-1.

[0028] Formula 2-1:

[0029] IndexC=C1×6+C2×5-C3-C4×10-C5×2

[0030] In the second-1 formula, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition; C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition; C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition; C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition; and C5 is the content (by weight) of the silicon nitride polishing enhancer contained in 100 parts by weight of the entire semiconductor process composition.

[0031] For the surface of a 5 μm diameter circular copper via polished with the semiconductor process composition described above, the surface area difference percentage measured using AFM can be less than 2.5%.

[0032] To achieve the above objective, the substrate polishing method according to this embodiment includes: a preparation step of preparing a flat plate on which a polishing pad is mounted and a carrier for accommodating the substrate; and a polishing step of rotating at least one of the flat plate and the carrier to planarize the surface of the substrate by means of the polishing surface of the polishing pad, thereby manufacturing a polished substrate.

[0033] Polishing is performed in the presence of a semiconductor process composition, which is the semiconductor process composition described above.

[0034] The surface of the substrate after the polishing step may partially comprise each of copper, silicon nitride, and silicon oxide.

[0035] For a circular copper via with a diameter of 5 μm on the surface of a substrate that has undergone the polishing step, the absolute value of the skewness measured using AFM can be within 1.

[0036] In the polishing method of the substrate, the SiO / SiN selection ratio, which is the ratio of silicon oxide polishing rate to silicon nitride polishing rate, can be 3 or higher.

[0037] In the polishing method of the substrate, the SiO / Cu selection ratio, which is the ratio of silicon oxide polishing rate to copper polishing rate, can be 0.9 or higher.

[0038] The effects of the invention

[0039] The semiconductor process composition and the polishing method for semiconductor substrates described in this embodiment can be used to perform polishing processes more efficiently. In particular, when applying the polishing process to substrates with through-hole electrodes, defects such as depressions, corrosion, and protrusions can be minimized. Furthermore, when polishing surfaces with multiple different films exposed on the outside, a flat polished surface can be achieved without thickness variations between the individual films.

[0040] According to the semiconductor process composition and substrate polishing method of this embodiment, when polishing a surface that simultaneously exposes copper and at least one material selected from silicon oxide and silicon nitride, the polishing rate is relatively high, and a flat polished surface can be achieved without thickness deviation between the various materials. Attached Figure Description

[0041] Figure 1 This is a cross-sectional illustration of a substrate including through-electrodes, planarized using a semiconductor process composition.

[0042] Figure 2 A conceptual diagram illustrating the recess using a cross-section of a substrate.

[0043] Figure 3A conceptual diagram illustrating metal corrosion using a cross-section of a substrate.

[0044] Figure 4 The images shown are AFM photographs of the sample surfaces prepared in the examples. e1 shows the sample of Example 1, e3 shows the sample of Example 3, ce1 shows the sample of Comparative Example 1, and ce2 shows the sample of Comparative Example 2.

[0045] Explanation of reference numerals in the attached figures

[0046] 100: Substrate

[0047] 11: Insulating film

[0048] 13: Barrier membrane

[0049] 15: Conductive film

[0050] 20: Wafer

[0051] D: Depression Detailed Implementation

[0052] The embodiments will be described in detail below to enable those skilled in the art to readily implement them. However, the present invention can be implemented in many different ways and is not limited to the embodiments described in this specification.

[0053] In this specification, when a component is described as "including" another component, it means, unless otherwise stated to the contrary, that other components are also included, rather than excluded.

[0054] In this specification, when describing a component as "connected" to another component, it includes not only the case of "direct connection" but also the case of "connection with other components in between".

[0055] In this specification, "B is located on A" means that B is located on A in direct contact with A or in the presence of other layers in between, and should not be interpreted as B being located on the surface of A in contact with A.

[0056] In this specification, the term "combination of..." included in the Markush-type description refers to a mixture or combination of one or more elements selected from the group of elements constituted by the Markush-type description, thereby implying that the invention includes one or more elements selected from the group of said elements.

[0057] In this specification, the term “A and / or B” means “A, B, or A and B”.

[0058] In this specification, unless otherwise specified, terms such as “first,” “second,” or “A,” “B,” etc., are used to distinguish them from each other.

[0059] Unless otherwise specified, the use of the singular in this specification is to be interpreted as including the meaning of singular or plural as the context suggests.

[0060] The semiconductor process composition according to this embodiment includes: polishing particles, surface-modified with an aminosilane compound; a copper corrosion inhibitor, comprising an azole compound; a copper surface protectant, comprising a compound having a betaine group and a salicyl group or a derivative thereof; and a surfactant containing fluorine in its molecule.

[0061] The surface of the surface-modified polishing particles has aminosilyl groups.

[0062] The following will provide a more detailed description of this embodiment.

[0063] Polishing particles

[0064] Polishing particles mainly serve a physical etching function, but can also achieve a planarization effect through mechanical friction with the surface of the object to be polished.

[0065] Polishing particles may include inorganic particles, organic particles, or organic / inorganic composite particles.

[0066] The inorganic particles may include inorganic particles surface-modified with organic matter. That is, inorganic particles should be understood to include the concept of containing trace amounts of organic components. Here, "trace amounts" refers to a content of approximately 0.03 parts by weight or less per 100 parts by weight of polishing particles. The organic / inorganic composite particles include particles containing 50 parts by weight to 200 parts by weight of organic components per 100 parts by weight of inorganic components.

[0067] For example, the inorganic particles may include a metal oxide particle selected from the group consisting of silicon dioxide (SiO2), cerium oxide (CeO2), aluminum oxide (Al2O3), zirconia (ZrO2), and combinations thereof.

[0068] The polishing particles may be in a colloidal state. For example, the polishing particles may include colloidal inorganic particles.

[0069] The polishing particles can be metal oxide particles with a surface that exposes functional groups.

[0070] The surface may include functional groups with amine groups at the ends.

[0071] By surface modification of the polishing particles with silane compounds, functional groups containing amine groups at the ends can be introduced into the surface of the polishing particles.

[0072] The silane compound can be, by way of example, an aminosilane, a ureosilane, or a combination thereof, and can be an aminosilane. By way of example, the aminosilane can be selected from 3-aminopropyltriethoxysilane, bis[(3-triethoxysilyl)propyl]amine, 3-aminopropyltrimethoxysilane, bis[(3-trimethoxysilyl)propyl]amine, 3-aminopropylmethyldiethoxysilane, 3-aminopropylmethyldimethoxysilane, N-[3-(trimethoxysilyl)propyl]ethylenediamine, N-bis[3-(trimethoxysilyl)propyl]- 1,2-Ethylenediamine, N-[3-(triethoxysilyl)propyl]ethylenediamine, diethylenetriaminopropyltrimethoxysilane, diethylenetriaminopropylmethyldimethoxysilane, diethylaminomethyltriethoxysilane, diethylaminopropyltrimethoxysilane, diethylaminopropyltriethoxysilane, diethylaminopropyltriethoxysilane, dimethylaminopropyltrimethoxysilane, N-[3-(trimethoxysilyl)propyl]butylamine, and combinations thereof. The ureosilane may be selected from the group consisting of 3-ureotrimethoxysilane, 3-ureotriethoxysilane, and combinations thereof.

[0073] Based on 100 parts by weight of the metal oxide particles, the content of the silane compound can be from 0.05 parts by weight to 10 parts by weight. Based on 100 parts by weight of the metal oxide particles, the content of the silane compound can be from 0.1 parts by weight to 5 parts by weight. Based on 100 parts by weight of the metal oxide particles, the content of the silane compound can be from 0.1 parts by weight to 3 parts by weight. In this case, the surface of the metal oxide particles can be sufficiently modified as intended, and the polishing speed and quality of the polishing particles can be maintained at the desired level by applying the silane compound together with other components.

[0074] Based on 1 part by weight of the azole compound described below, the content of the aminosilane compound can be from 0.01 parts by weight to 70 parts by weight, or from 0.01 parts by weight to 30 parts by weight. Based on 1 part by weight of the azole compound described below, the content of the aminosilane compound is preferably from 0.1 parts by weight to 0.28 parts by weight. In this case, it is advantageous to obtain excellent etching results while using minimal surface treatment agents.

[0075] The diameter (D) of the polishing particles 50 The diameter (D) of the polishing particles can range from 10 nm to 120 nm. 50 The diameter (D) of the polishing particles can range from 15 nm to 90 nm. 50The diameter can be from 20 nm to 60 nm. When the polishing particles exceed 120 nm, the possibility of defects such as scratches occurring on the substrate to be polished increases. When the diameter of the polishing particles is less than 10 nm, the particle dispersion may deteriorate, or the occurrence of defects may increase. When the diameter is between 20 nm and 60 nm, excellent physical properties can be obtained when used as a composition for semiconductor processes with substrates having fine wiring widths.

[0076] The diameters mentioned above are based on Malvern's Nano-ZS instrument, which measures particle size using dynamic light scattering (DLS).

[0077] The zeta potential of the polishing particles can be +1mV to +80mV, +2mV to +50mV, or +20mV to +40mV. When inorganic or organic particles themselves do not have a zeta potential within the aforementioned range, surface modification treatment can be applied to produce particles with the aforementioned zeta potential.

[0078] The method for determining the zeta potential of the polishing particles is not particularly limited; however, for example, it can be performed using a zeta potential measuring device (Malvern, Zeta-sizer Nano ZS) after adding approximately 1 mL of the polishing particles to the measuring cell.

[0079] The polishing particles can have a zeta potential within the range by modifying the surface of the colloidal silica particles with aminosilane.

[0080] Based on the total amount of the semiconductor process composition, the content of the polishing particles can be 1% by weight or more, 3% by weight or more, or 4% by weight or more. Based on the total amount of the semiconductor process composition, the content of the polishing particles can be 8% by weight or less, or 7% by weight or less.

[0081] When a semiconductor process composition includes polishing particles within the stated content range, a more efficient polishing process can be performed.

[0082] Copper corrosion inhibitor

[0083] Copper corrosion inhibitors include azole compounds.

[0084] For example, azole compounds may include one selected from the group consisting of benzotriazole (BTA), 5-methyl-1H-benzotriazole (5-MBTA), 3-amino-1,2,4-triazole (3-Amino-1,2,4-Triazole), 5-phenyl-1H-tetrazole (5-Phenyl-1H-Tetrazole), 3-amino-5-methyl-4H-1,2,4-triazole (3-Amino-5-Methyl-4H-1,2,4-Triazole), 5-aminotetrazole (5-Aminotetrazole (ATZ), 1,2,4-triazole (1,2,4-Triazole), tolytriazole, and combinations thereof.

[0085] Azole compounds may include one selected from the group consisting of 5-aminotetrazole (ATZ), 5-methyl-1H-benzotriazole (5-MBTA), and combinations thereof.

[0086] Zazole compounds can act on the copper surface during the polishing process to prevent copper corrosion.

[0087] Based on 100 parts by weight of the polishing particles, the content of the azole compound may be from 0.02 parts by weight to 2.00 parts by weight, from 0.03 parts by weight to 1.5 parts by weight, or from 0.5 parts by weight to 1.5 parts by weight.

[0088] When the content of the azole compound is within the specified range, the semiconductor composition can achieve a corrosion protection effect on copper surfaces, especially providing a strong corrosion protection effect on relatively wide surfaces such as through-hole surfaces.

[0089] Copper surface protectant

[0090] Copper surface protectants can be compounds or their derivatives containing betaine and salicyl groups.

[0091] Copper surface protectants may include betaine salicylate.

[0092] Copper surface protectants may include one selected from betaine hydrochloride, betaine perchloric acid, betaine aldehyde chloride, and combinations thereof; and / or salicylic acid.

[0093] The copper surface protectant effectively protects the copper surface during the polishing process, thereby greatly suppressing the formation of polishing-induced depressions in the through-hole surfaces of copper with relatively soft properties that are widely exposed.

[0094] Based on 100 parts by weight of the polishing particles, the copper surface protectant may contain 0.1 to 1.5 parts by weight or 0.13 to 0.42 parts by weight.

[0095] Copper surface protectants can be separated into ions in aqueous solutions, and the content and / or content ratio of copper surface protectants can be confirmed by removing pure water as a solvent.

[0096] In the semiconductor process composition, the weight ratio of the azole compound to the copper surface protectant can be 1:0.2 to 1:4, 1:0.2 to 1:2.5, 1:0.4 to 1:2.0, 1:0.4 to 1:1.0, or 1:0.4 to 1:0.6.

[0097] The azole compounds and the copper surface protectant have strong and relatively weak copper surface corrosion inhibition effects, respectively, and control the excessive corrosion or pitting of the copper surface. Therefore, even when polishing at a fast polishing speed, excellent polishing quality can be achieved.

[0098] surfactants

[0099] Compositions for semiconductor processing include surfactants containing fluorine in their molecules.

[0100] For example, as surfactants containing fluorine in their molecules, BNO-BS-BOH from BNOCHEM, FS-30, FS-31, FS-34, ET-3015, ET-3150, ET-3050 and Capstone FS-3100 from Chemours can be used alone or in combination.

[0101] Fluorinated surfactants can effectively prevent excessive adsorption of polishing particles onto the surface of the object to be polished. In addition, they can make or maintain the surface of the planarized material, such as silicon oxide film, in a state conducive to polishing.

[0102] Based on 100 parts by weight of the polishing particles, the content of the fluorinated surfactant in the semiconductor process composition can be from 0.003 parts by weight to 0.05 parts by weight, or from 0.005 parts by weight to 0.03 parts by weight, or from 0.007 parts by weight to 0.02 parts by weight. When the content of the fluorinated surfactant is within the range described above, it is possible to reduce defects caused by excessive adsorption of polishing particles onto the surface of the workpiece.

[0103] In the semiconductor process composition, the weight ratio of the azole compound to the fluorinated surfactant can be 1:0.001 to 1:0.2, 1:0.013 to 1:1.5, or 1:0.015 to 1:0.05. When the aforementioned content ratio is applied, defects caused by surface adsorption of particles generated during polishing can be suppressed, while substantially suppressing the formation of adhesive foreign matter due to the interaction of the surfactant with other components.

[0104] Silicon nitride polishing enhancer

[0105] Compositions for semiconductor processing may also include silicon nitride polishing enhancers.

[0106] Silicon nitride polishing enhancers may include phosphoric acid compounds. These phosphoric acid compounds can help adjust the polishing properties of barrier films such as silicon nitride films.

[0107] Phosphoric acid compounds may be, for example, selected from the group consisting of phosphomolybdic acid or its salts, nitrilotris (methylenephosphonic acid) or its salts, phosphorus trichloride or its salts, pyrophosphate or its salts, and combinations thereof. The salts may be sodium salts, potassium salts, etc.

[0108] The phosphate compounds may include triazine (methylenephosphonic acid) and / or potassium pyrophosphate.

[0109] Based on 100 parts by weight of the polishing particles, the content of the phosphate compound in the semiconductor process composition may be from 0 parts by weight to 0.005 parts by weight, from 0 parts by weight to 0.004 parts by weight, or from 0 parts by weight to 0.003 parts by weight.

[0110] Based on 100 parts by weight of the polishing particles, the content of the phosphate compound in the semiconductor process composition may be less than 0.001 parts by weight, or the semiconductor process composition may substantially exclude the phosphate compound.

[0111] Based on 1 part by weight of the azole compound, the content of the phosphate compound in the semiconductor process composition may be from 0 to 0.05 parts by weight, from 0 to 0.01 parts by weight, or from 0 to 0.003 parts by weight.

[0112] When phosphoric acid compounds are further applied to the semiconductor process composition, it can help to adjust the polishing performance of barrier films such as silicon nitride films.

[0113] Other additives

[0114] Compositions used in semiconductor processes may include organic acids as additives.

[0115] The organic acid can be mainly used as a chelating agent. Specifically, copper ions and the hydroxyl groups of the organic acid can bond to each other to capture copper ions and improve polishing efficiency.

[0116] For example, the organic acid may include, selected from acetic acid, formic acid, benzoic acid, nicotinic acid, picolinic acid, alanine, phenylalanine, valine, leucine, isoleucine, arginine, aspartic acid, citric acid, adipic acid, succinic acid, oxalic acid, glycine, glutamic acid, glutaric acid, and phthalic acid. One of the following groups: acid), histidine, threonine, serine, cysteine, methionine, asparagine, tyrosine, diiodotyrosine, tryptophan, proline, oxyproline, ethylenediaminetetraacetic acid (EDTA), nitrotriacetic acid (NTA), iminodiacetic acid (IDA), and combinations thereof.

[0117] Compositions for semiconductor processes may include citric acid as the organic acid.

[0118] In the semiconductor process composition of this embodiment, in addition to the aforementioned constituent components, an acid component may be added to prepare and maintain a solution within a suitable pH range. The acid component, together with a pH adjuster, can be used in the semiconductor process composition.

[0119] As the acid component, one or more of the following can be used: hydrochloric acid (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), nitric acid (HNO3). As the pH adjuster, one or more of the following can be used: ammonium hydroxide (NH4OH), potassium hydroxide (KOH), sodium hydroxide (NaOH).

[0120] The acid components and pH adjusters can be applied in appropriate amounts according to the desired pH.

[0121] Compositions for semiconductor processes may also include nonionic polymers.

[0122] The nonionic polymer can be at least one selected from the group consisting of polyethylene glycol, polypropylene glycol, polyvinylpyrrolidone, polyethylene oxide, polypropylene oxide, polyalkyl oxide, polyethylene oxide, polyethylene oxide-propylene oxide copolymer, cellulose, methylcellulose, methyl hydroxyethylcellulose, methyl hydroxypropylcellulose, hydroxyethylcellulose, carboxymethylcellulose, carboxymethyl hydroxyethylcellulose, sulfoethylcellulose, and carboxymethyl sulfoethylcellulose.

[0123] Nonionic polymers can have a weight-average molecular weight of less than 25,000 g / mol. When the weight-average molecular weight of the nonionic polymer is less than 25,000 g / mol, the nonionic polymer can exhibit excellent solubility and dispersibility. Nonionic polymers can have a weight-average molecular weight of 1,000 g / mol or more but less than 25,000 g / mol. When nonionic polymers within the above range are used, the compositions for semiconductor processes can exhibit superior solubility and dispersion stability, and are also beneficial for polishing performance.

[0124] Compositions for semiconductor processes may include additional chelating agent compounds, either alone or in combination with the aforementioned organic acids. The chelating agent adsorbs metals or metal ions for easy removal.

[0125] For example, a chelating agent may include two or more carboxyl or alcohol groups in its molecule. Two or more chelating agents containing two or more carboxyl or alcohol groups in their molecule may be used as chelating agents. Specifically, the chelating agent may include one selected from the group consisting of ethylenediaminetetraacetic acid, glycine, carboxylic acid chelating agents, and combinations thereof. The carboxylic acid chelating agent refers to a compound containing at least one or two carboxyl groups in its molecule.

[0126] Compositions used in semiconductor processes also include solvents.

[0127] Compositions used in semiconductor processes can be aqueous dispersions.

[0128] Aqueous dispersions refer to solutions with pure water as the main solvent, and also include those that contain liquid organic matter or organic solvents.

[0129] Compositions for semiconductor processes

[0130] Polishing compositions for semiconductor processes can be acidic solutions.

[0131] Specifically, the pH of the polishing composition for semiconductor processes can be from 2 to 5. The pH of the polishing composition for semiconductor processes can be from 2 to 4.5, or from 2 to 4. When the acidic environment of the composition is maintained within the specified range, polishing speed and quality can be maintained at a certain level while preventing excessive corrosion of the metal components or polishing equipment.

[0132] Because copper is relatively soft, while silicon oxide and silicon nitride are relatively hard, it is not easy to quickly and evenly polish them to expose their surfaces.

[0133] The semiconductor process composition can be used as a slurry for polishing surfaces that partially comprise each of copper, silicon nitride, and silicon oxide, thereby achieving excellent polishing results.

[0134] Even when the semiconductor process composition is polished at a relatively high polishing speed, defects such as corrosion or pitting can be avoided in soft-textured areas such as copper.

[0135] Specifically, the semiconductor process composition is advantageous for substrate polishing processes, including those for semiconductor wafers with through-electrodes.

[0136] Figure 1 This is a conceptual diagram illustrating, in cross-section, a substrate planarized (including through-electrodes) using a semiconductor process. Figure 2 A conceptual diagram illustrating the recess using a cross-section of the substrate. Figure 3 A conceptual diagram illustrating metal corrosion using a cross-section of a substrate. (Refer to...) Figures 1 to 3 To explain in more detail.

[0137] The substrate 100, including the through electrode, includes a wafer 20, an insulating film material such as SiO2 used as an insulating film 11, a barrier film material such as SiN used as a barrier film 13 used to block the movement of metal ions, and a conductive film material such as copper used as a conductive film 15 used to transmit electrical signals due to its conductivity.

[0138] During substrate planarization, surfaces with two or three different film materials simultaneously exposed are planarized. Because different film materials have different properties (strength, oxidation level, etc.), it is not easy to planarize them simultaneously and quickly.

[0139] Semiconductor substrates are becoming increasingly refined and complex; for example, interconnects are becoming finer and through-electrodes are being used more frequently. This necessitates more efficient process technology and more stringent planarization processes. Through-electrodes have a wider exposed area compared to fine lines and are made of a softer metal than metal oxides or metal nitrides, thus making them more prone to creating recesses (D-type). Figure 2 ) or metal corrosion (refer to Figure 3 Defects such as )

[0140] When excessive pitting or corrosion occurs in the through-electrode portion, incomplete electrical connections are created in the vertical direction, making it difficult to transmit sufficient electrical signals, thus leading to fatal defects in the semiconductor.

[0141] The semiconductor process composition of this embodiment substantially suppresses erosion of conductive films such as copper while applying an effective polishing process.

[0142] The polishing conditions are as follows: slurry flow rate: 300 ml / min, carrier speed: 120 rpm, plate speed: 117 rpm, pressure: 3.0 psi down pressure, polishing equipment: CTS 300 mm CMP equipment, using SKC Solmics HD-500 polishing pads.

[0143] For the surface of a 5 μm diameter circular via polished with the semiconductor process composition described above, the Rmax roughness measured using AFM can be below 220 nm, 200 nm, 180 nm, or 160 nm. The Rmax roughness can be above 100 nm. Rmax represents the maximum height roughness and is a different variable from Ra, which represents the average roughness along the centerline. Rmax is the sum of the maximum peak height and the maximum valley depth within the measurement range. The aforementioned Rmax roughness value implies a substantial reduction in the occurrence of erosion, etc.

[0144] For a circular via with a diameter of 5 μm polished using the semiconductor process composition, the surface area difference percentage (SAD) measured using AFM can be less than 2.5%, or less than 2.3%, 2.2%, 2%, or 1.8%. The SAD percentage can be greater than 1%. The SAD can also be represented by Sdr, which is the difference between the actual surface area and the projected surface area. The SAD can be used as one of the indicators of surface complexity, expressed as a percentage, and is called the surface area difference percentage. Having such a low SAD means that the surface complexity is significantly low, i.e., it has a flatter surface.

[0145] For the surface of a circular via with a diameter of 5 μm polished using the semiconductor process composition, the absolute value of the skewness measured using AFM can be less than 1, less than 0.96, less than 0.8, or less than 0.6. The absolute value of the skewness can be greater than 0.2. When the absolute value of the skewness is small, it indicates that the asymmetry of the surface is relatively small. Considering the surface of a polished circular via, a surface with this skewness characteristic can have a flatter profile.

[0146] For the surface of a circular via with a diameter of 5 μm polished using the semiconductor process composition, the Z range of the surface measured using AFM can be less than 220 nm, less than 200 nm, less than 180 nm, or less than 160 nm. The Z range can also be greater than 100 nm. The Z range is one of the variables obtained through AFM measurement. Having the above-mentioned Z range indicates a flatter surface.

[0147] The aforementioned variables, such as roughness, can be calculated by measuring the surface profile using an AFM device, and can be measured using a Park Systems XE-150 device according to the manufacturer's guidelines.

[0148] The copper corrosion inhibition index (Er, without unit) of the composition for semiconductor processing according to the first formula below can be from 8 to 15.

[0149] Form 1:

[0150]

[0151] In Equation 1, indexC is a value according to Equation 2 or Equation 2-1 below, and has no unit.

[0152] In Formula 1, Cab is the content (by weight%) of polishing particles in the entire semiconductor process composition, and Ps is the content (by weight) of aminosilane compounds in 100 parts by weight of the polishing particles.

[0153] Form 2:

[0154] IndexC=C1×6+C2×5-C3-C4×10

[0155] In Formula 2, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition, C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition, C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition, and C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition.

[0156] Formula 2-1:

[0157] IndexC=C1×6+C2×5-C3-C4×10-C5×2

[0158] In the second-1 formula, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition; C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition; C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition; C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition; and C5 is the content (by weight) of the silicon nitride polishing enhancer contained in 100 parts by weight of the entire semiconductor process composition.

[0159] The copper corrosion inhibition index (Er, unitless) can be 8 to 15, 8 to 14, or 8 to 13. Semiconductor process compositions having the above-mentioned copper corrosion inhibition index achieve excellent copper polishing rate, silicon nitride polishing rate, and silicon oxide polishing rate values ​​at a certain level or higher, while simultaneously suppressing copper corrosion on the surface of the polished object.

[0160] Semiconductor process compositions can perform effective polishing processes while controlling the degree of dents and etches within appropriate levels.

[0161] When polishing substrate surfaces with different film textures, the semiconductor process composition can have a polishing speed ratio for each film texture within the following range.

[0162] Polishing can be performed using a semiconductor process composition, such that the SiO / SiN selectivity ratio, which is the ratio of silicon oxide polishing rate to silicon nitride polishing rate, is 3 or higher. The SiO / SiN selectivity ratio can be from 3 to 10, or from 3 to 7.

[0163] Polishing can be performed using a semiconductor process composition, such that the SiO / Cu selectivity ratio, which is the ratio of silicon oxide polishing rate to copper polishing rate, can be 0.9 or higher. The SiO / Cu selectivity ratio can be from 0.9 to 2, or from 0.9 to 1.5.

[0164] When a semiconductor process composition capable of polishing with the above-described polishing selectivity is used to polish the surface of a workpiece containing copper, silicon oxide, and silicon nitride, effective planarization can be provided.

[0165] The copper polishing rate of the composition for semiconductor processing can be from about 2,000 angstroms / min to about 4,600 angstroms / min, from about 2,100 angstroms / min to about 4,000 angstroms / min, from about 2,200 angstroms / min to about 3,800 angstroms / min, or from about 2,200 angstroms / min to about 3,000 angstroms / min.

[0166] The silicon nitride polishing rate of the composition for semiconductor processing can be from 300 Å / min to 2700 Å / min, from 400 Å / min to about 2500 Å / min, or from about 500 Å / min to about 1500 Å / min.

[0167] The silicon oxide polishing rate of the composition for semiconductor processing can be from 2,300 Å / min to 4,400 Å / min, from 2,500 Å / min to about 4,000 Å / min, or from about 3,000 Å / min to about 3,700 Å / min.

[0168] By using the semiconductor process composition applicable to this embodiment, substrate surfaces having three different types of film can be effectively etched while substantially suppressing the formation of depressions.

[0169] The polishing rate or polishing ratio is based on the measurement under the above polishing conditions.

[0170] Semiconductor process compositions with the above-mentioned characteristics enable efficient polishing processes and suppress the formation of conductive film depressions, making them suitable for polishing substrates with through electrodes and the like.

[0171] The semiconductor process composition of this embodiment can be prepared by mixing polishing particles and each component in a solvent such as pure water, and may include a process of stirring in a conventional manner to ensure smooth dispersion of the particles. When surface-modified polishing particles are used, a method can be applied that first surface-modifies the polishing particles and then disperses them.

[0172] The applicability of the semiconductor process composition of this embodiment can be demonstrated by applying pressure and rotation while injecting the semiconductor process composition after mounting the workpiece and polishing pad in the substrate polishing apparatus, and the above-described features are explained based on measurements under the polishing conditions. However, the use of the semiconductor process composition is not limited to the polishing conditions described above.

[0173] substrate polishing method

[0174] The substrate polishing method according to this embodiment includes: a preparation step of preparing a flat plate on which a polishing pad is mounted and a carrier for containing a workpiece to be polished; and a polishing step of rotating at least one of the flat plate and the carrier to polish the surface of the workpiece by means of the polishing surface of the polishing pad.

[0175] Polishing is performed in the presence of a semiconductor process composition, which is the semiconductor process composition described above.

[0176] The substrate surface after the polishing step may partially comprise each of copper, silicon nitride, and silicon oxide, and may be a substrate with copper through-electrodes.

[0177] Specific details regarding semiconductor process compositions, selectivity, polishing rate, recesses, etching, etc., are repeated above and will therefore be omitted.

[0178] The following will provide a more detailed description through specific embodiments. These embodiments are merely examples to aid in understanding the invention, and the scope of the invention is not limited thereto.

[0179] 1. Preparation of compositions for semiconductor processes

[0180] Semiconductor process compositions with a pH of 2 or higher and less than 4.0 are prepared according to the compositions shown in Table 1 below.

[0181] Colloidal silica was used as the polishing particles, specifically colloidal silica prepared by the condensation reaction of tetraethyl orthosilicate (TEOS) dispersed in an ethanol solution. 3-aminopropyltriethoxysilane was used as the surface treatment agent, and surface-modified colloidal silica with a diameter of approximately 45 nm was used as the polishing particles.

[0182] 5-Aminotetrazole was used as a copper corrosion inhibitor, betaine salicylate as a copper surface protectant, and a nonionic surfactant (capstone FS-3100) containing 3 to 8 carbon atoms and a fluorine functional group was used as the surfactant. Silicon nitride polishing enhancer was added or not added according to the preparation example. As a silicon nitride polishing enhancer, nitrilotrimethylmethylenephosphonic acid was used. A residual amount of ultrapure water was used to ensure that the total amount of the semiconductor process composition was 100 parts by weight. Acetic acid and KOH solution were used as pH adjusters. Ultrapure water was used as the solvent. The pH of the semiconductor process composition was measured using a hydrogen ion concentration (pH) measuring device (Horiba, Laqua) while stirring at 200 rpm at room temperature (20°C to 25°C) to confirm that it was within the above range.

[0183] Table 1

[0184]

[0185] * indicates the content based on 100 parts by weight of the composition, and the content in parentheses indicates the content calculated based on azole compounds as copper corrosion inhibitors.

[0186] 2. Physical property evaluation of compositions used in semiconductor processes

[0187] (1) Polishing evaluation

[0188] Polishing evaluations were performed using copper wafers with a thickness of approximately 20,000 angstroms, silicon nitride film wafers with a thickness of approximately 12,000 angstroms, and silicon oxide film wafers with a thickness of approximately 20,000 angstroms, respectively.

[0189] For each wafer, polishing was performed for 60 seconds in a conventional manner under the conditions of 3.0 psi pressure, 120 rpm carrier speed, 117 rpm plate speed and 300 ml / min slurry flow rate, with the polishing pad of SKC Solmics HD-500 model installed in a CMP apparatus (CTS 300mm CMP equipment).

[0190] The thickness of each wafer after the polishing process is measured, and the polishing rate (polishing speed; angstroms / minute) of the corresponding slurry composition for copper film, silicon oxide film and silicon nitride film is calculated respectively.

[0191] (2) Measurement of copper via corrosion

[0192] A test patterned wafer with copper vias of 5 μm in diameter and surface-trimmed with SiN was polished under the same conditions as in the polishing evaluation described in (1), and then cleaned. Cleaning was performed for 60 seconds using a self-made cleaning chemical solution at a brush speed of 500 rpm and a chemical solution spraying speed of 2000 cc / min.

[0193] In the patterned wafer that has completed the cleaning process, the surface roughness value is obtained by performing through-hole surface analysis at each location of the wafer, namely the center, middle and edge, using BRUKER's Dimension ICON equipment, which is a dedicated 300mm AFM device.

[0194] The scanning size was approximately 5.0 μm, the scanning speed was 0.3 Hz, and the probe tip was a BRUKER OLTESPA-R3 model (rectangular, tip radius of curvature: 7 nm, maximum: 10 nm). Other more specific measurement conditions are shown in Table 3 below along with the surface analysis results.

[0195] (3) Evaluation of Copper Erosion Inhibition Index (Er)

[0196] The value is evaluated according to the first equation below.

[0197] Form 1:

[0198]

[0199] In the first formula, indexC is the value according to the second formula or the second-first formula below, Cab is the content (by weight%) of polishing particles contained in the entire semiconductor process composition, and Ps is the content (by weight) of aminosilane compounds in 100 parts by weight of the polishing particles. When silicon nitride polishing enhancer is included, the indexC value according to the second formula applies; when silicon nitride polishing enhancer is not included, the indexC value according to the second-first formula applies.

[0200] Form 2:

[0201] IndexC=C1×6+C2×5-C3-C4×10

[0202] In the second formula, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition, C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition, C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition, and C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition.

[0203] Formula 2-1:

[0204] IndexC=C1×6+C2×5-C3-C4×10-C5×2

[0205] In the second-1 formula, C1 is the content (by weight) of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition; C2 is the content (by weight) of the azole compound contained in 100 parts by weight of the entire semiconductor process composition; C3 is the content (by weight) of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition; C4 is the content (by weight) of the surfactant contained in 100 parts by weight of the entire semiconductor process composition; and C5 is the content (by weight) of the silicon nitride polishing enhancer contained in 100 parts by weight of the entire semiconductor process composition.

[0206] [Table 2]

[0207]

[0208]

[0209] [Table 3]

[0210]

[0211] Refer to Tables 1 to 3 and Figure 4 Copper corrosion was clearly observed in the comparative examples. Copper corrosion was clearly observed in Comparative Examples 1, 3, and 4, especially at the edges in Comparative Examples 2 and 4. Figure 4 Examples 1 and 3 and Comparative Examples 1 and 2 are shown. In addition, a decrease in polishing efficiency was confirmed for silicon oxide in Comparative Examples 2 and 4, and a decrease in polishing efficiency for silicon nitride was confirmed in Comparative Example 1.

[0212] In the embodiments, virtually no copper erosion occurred, particularly in terms of surface roughness Rmax, showing a significant difference from the comparative example. On the other hand, in terms of Ra, the embodiments showed no significant difference from the comparative example. In particular, in Embodiment 3, a silicon nitride film polishing enhancer was not substantially used, thus exhibiting a slightly lower silicon nitride film polishing rate compared to Embodiments 1 and 2, but the copper polishing rate was relatively excellent, demonstrating the superior effect of virtually no copper erosion. The copper exposed in the vias has a wider surface area compared to the copper forming the lines, and the depressions or erosion of this copper surface greatly affect the degree of current or resistance generation in the through-electrode. Therefore, the semiconductor process composition of this embodiment is considered useful for surface polishing of substrates with through-electrodes.

[0213] The preferred embodiments of the present invention have been described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art based on the basic concepts of the present invention as defined in the appended claims are also within the scope of the present invention.

Claims

1. A composition for semiconductor processing, wherein, include: Polishing particles are surface-modified with aminosilane compounds. Copper corrosion inhibitors, including azole compounds, Copper surface protectants, comprising compounds or derivatives thereof having betaine and salicyl groups, and Surfactants contain fluorine in their molecules; The copper corrosion inhibition index Er of the composition for semiconductor processing, according to formula 1 below, is 8 to 15. Form 1: In the first formula, indexC is the value according to the second formula below, Cab is the content of polishing particles in the entire semiconductor process composition, Ps is the content of aminosilane compounds in 100 parts by weight of the polishing particles, and the unit of Cab is % by weight, and the unit of Ps is parts by weight. Form 2: In the second equation, C1 represents the content of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition; C2 represents the content of the azole compound contained in 100 parts by weight of the entire semiconductor process composition; C3 represents the content of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition; and C4 represents the content of the surfactant contained in 100 parts by weight of the entire semiconductor process composition. The units for C1, C2, C3, and C4 are parts by weight.

2. The composition for semiconductor processing according to claim 1, wherein, The semiconductor process composition further includes a silicon nitride polishing enhancer. The index C is the value according to the following equation 2-1. Formula 2-1: In the above formula 2-1, C1 represents the content of the aminosilane compound in the polishing particles contained in 100 parts by weight of the entire semiconductor process composition; C2 represents the content of the azole compound contained in 100 parts by weight of the entire semiconductor process composition; C3 represents the content of the copper surface protectant contained in 100 parts by weight of the entire semiconductor process composition; C4 represents the content of the surfactant contained in 100 parts by weight of the entire semiconductor process composition; and C5 represents the content of the silicon nitride polishing enhancer contained in 100 parts by weight of the entire semiconductor process composition. The units for C1, C2, C3, C4, and C5 are parts by weight.

3. The composition for semiconductor processing according to claim 1, wherein, For the surface of a 5 μm diameter circular copper via polished with the semiconductor process composition, the percentage of surface area difference measured using atomic force microscopy is less than 2.5%.

4. A method for polishing a substrate, wherein, include: Preparation steps include preparing a flat plate with a polishing pad and a carrier to hold the substrate. The polishing step involves rotating at least one of the flat plate and the carrier to planarize the surface of the substrate by means of the polishing surface of the polishing pad, thereby producing a polished substrate. Polishing is performed in the presence of a semiconductor processing composition. The semiconductor process composition is the semiconductor process composition according to claim 1. The surface of the substrate after the polishing step comprises, in part, each of copper, silicon nitride, and silicon oxide.

5. The substrate polishing method according to claim 4, wherein, For a circular copper via with a diameter of 5 μm on the surface of the substrate after the polishing step, the absolute value of the skewness measured using an atomic force microscope is less than 1.

6. The substrate polishing method according to claim 4, wherein, The SiO / SiN ratio, which is the ratio of silicon oxide polishing rate to silicon nitride polishing rate, is selected to be 3 or higher.

7. The substrate polishing method according to claim 4, wherein, The SiO / Cu selection ratio, which is the ratio of silicon oxide polishing rate to copper polishing rate, is 0.9 or higher.

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