Low power current integrating dac slew rate stabilization auxiliary circuit

Abstract

This application relates to low power current integrating DAC slew settling assist circuit. A slew generator includes an operational amplifier having an output to generate a slew signal. An integrating current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor and a reset switch are coupled between the first input and the output of the operational amplifier. The reset switch is turned on to reset the slew generator. A slew event is configured to be generated in the slew signal at the output of the operational amplifier in response to the reset switch being turned off. An assist current source is coupled between the output of the operational amplifier and ground. The assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response to the reset switch being turned off.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to ramp generators in image sensors. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, etc. in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing. The technology for manufacturing image sensors has been advancing at a high rate. For example, the demand for higher resolution and lower power consumption has facilitated further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge after absorbing the image light. The pixel-generated image charge is measurable as an analog output image signal on a column bitline that varies with the incident image light. In other words, the amount of generated image charge is proportional to the intensity of the image light, which is read out as an analog signal from the column bitline and converted to a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] An analog-to-digital converter (ADC) is typically used in a CMOS image sensor (CIS) to convert charge to a digital representation of charge by the image sensor. The ADC generates the digital representation of charge based on a comparison of the image charge signal to a reference voltage signal. The reference voltage signal can conventionally be a ramp signal provided by a ramp generator, and the comparison can conventionally be performed by a comparator that provides an output that can be used with a counter to generate the digital representation of the image charge.

[0005] It should be appreciated that the ramp settling time or delay of the ramp signal generated by the ramp generator and received by the comparator can limit the maximum frame rate of the image sensor. Thus, reducing the ramp settling time of the ramp signal received by the comparator can improve the maximum frame rate and thus the performance of the image sensor. SUMMARY

[0006] In one aspect, the present application provides a ramp generator comprising: an operational amplifier having a first input, a second input, and an output to generate a ramp signal; an integrating current source coupled to the first input of the operational amplifier; a reference voltage coupled to the second input of the operational amplifier; a feedback capacitor coupled between the first input and the output of the operational amplifier; a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off; and an auxiliary current source coupled between the output of the operational amplifier and ground, wherein the auxiliary current source is configured to conduct an auxiliary current from the output of the operational amplifier to ground in response to the reset switch turning off.

[0007] In another aspect, the present application provides an imaging system comprising: a pixel array that receives image light and generates, in response, an image charge voltage signal; and readout circuitry coupled to receive the image charge voltage signal from the pixel array and provide, in response, a digital representation of the image charge voltage signal, the readout circuitry including a comparator to receive the image charge voltage signal, compare the image charge voltage signal to a ramp signal from a ramp generator, and provide, in response, the digital representation of the image charge voltage signal, wherein the ramp generator comprises: an operational amplifier having a first input, a second input, and an output to generate the ramp signal; an integrating current source coupled to the first input of the operational amplifier; a reference voltage coupled to the second input of the operational amplifier; a feedback capacitor coupled between the first input and the output of the operational amplifier; a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off; and an auxiliary current source coupled between the output of the operational amplifier and ground, wherein the auxiliary current source is configured to conduct an auxiliary current from the output of the operational amplifier to ground in response to the reset switch turning off. BRIEF DESCRIPTION OF DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present application are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views.

[0009] Figure 1An example of an imaging system including a readout circuit having a ramp generator with a low power ramp stabilization assist circuit is illustrated in accordance with the teachings of the present disclosure.

[0010] Figure 2 A circuit model of an example current integrating ramp generator without a low power ramp stabilization assist circuit is illustrated.

[0011] Figure 3 A timing diagram illustrating a non-ideal ramp signal generated by an example current integrating ramp generator without a low power ramp stabilization assist circuit compared to an ideal ramp signal.

[0012] Figure 4 An example of a schematic diagram of a current integrating ramp generator with a low power ramp stabilization assist circuit in accordance with the teachings of the present disclosure is illustrated.

[0013] Figure 5 A timing diagram illustrating a signal including a ramp signal generated by an example current integrating ramp generator with a low power ramp stabilization assist circuit in accordance with the teachings of the present disclosure is illustrated.

[0014] Corresponding reference numbers indicate corresponding components throughout the several views of the drawings. It will be understood that the elements of the figures are merely for simplicity and clarity of illustration and are not necessarily drawn to scale. For example, some of the elements in the figures can be exaggerated in size or proportions to help enhance understanding of the various embodiments of the present disclosure. Also, common but well-understood elements that are useful in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Examples directed to imaging systems including readout circuits having current integrating ramp generators with low power ramp stabilization assist circuits are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects.

[0016] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present technology. Thus, the appearance of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0017] Spatially relative terms, such as "under", "below", "lower", "above", "upper", "top", "bottom", "bottom", "left", "right", "center", "intermediate", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over or rotated, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that, when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more intervening elements can also be present.

[0018] Throughout this specification, several technical terms are used. Such terms are to be understood in their ordinary context. Unless otherwise defined, or if it is clear from the context, the terms are to be interpreted as follows. It is noted that element names and symbols can be used interchangeably herein (e.g., Si and silicon); however, both have the same meaning.

[0019] As will be discussed, various examples of imaging systems are described that include readout circuits having current integrating ramp generators with low power ramp stabilization assist circuits. In various examples, the ramp generator is a current integrating ramp generator that includes an operational amplifier configured as an integrator with a feedback capacitor coupled between an input and an output of the operational amplifier. An integrating current source is also coupled to the input of the operational amplifier. In an example, the low power ramp stabilization assist circuit includes an assist current source coupled between an output of the current integrating ramp generator and ground. In an example, the low power ramp stabilization assist circuit provides an assist current from the output of the ramp generator to ground that is turned on during a ramp event or ramp phase of an output ramp signal of the ramp generator. For purposes of this disclosure, it is understood that a ramp event of an output ramp signal is the time during which the ramp signal continuously decreases. In another example, it is understood that a ramp event of an output ramp signal can also be considered the time during which the ramp signal continuously increases. An output capacitor coupled to the output of the ramp generator is discharged by the assist current, thus reducing the ramp stabilization time of the ramp signal caused by loading the output of the ramp generator, thus improving the maximum frame rate and image sensor performance according to the teachings of the present disclosure.

[0020] To illustrate, Figure 1An example of an imaging system 100 including a readout circuit containing a current integrating ramp generator with a low power ramp stabilization assist circuit according to the teachings of this disclosure is shown. As shown in the illustrated example, the imaging system 100 includes a pixel array 102, a control circuit 110, a readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, a place, an object, etc. that can then be used to present an image of the person, place, object, etc.

[0021] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photo generate image charge in response to incident light. Image charge generated in each photodiode is transferred to a floating diffusion included in each pixel circuit 104, converted to an image signal, and then read out from each pixel circuit 104 by the readout circuit 106 through a column bit line 112. In various examples, the readout circuit 106 can read out one row of image data at a time along the (illustrated) readout column bit line 112 or can read out image data using a variety of other techniques (not illustrated), such as all pixel circuits 104 read out serially or synchronous full parallel read out.

[0022] In various examples, the readout circuit 106 can include amplification circuitry, an analog-to-digital converter (ADC), or other. In the depicted example, the ADC 118 includes a comparator circuit 116 coupled to receive image signals from the pixel array 102 through the column bit line 112. In one example, the comparator circuit 116 can include a plurality of comparators coupled to receive image signals through the bit line 112. In the example, each of the comparators included in the comparator circuit 116 is also coupled to receive a ramp signal 140 from a ramp generator 114 as shown. In the example, each comparator included in the comparator circuit 116 can be used to determine a digital representation of an image signal using a counter based on a comparison of the ramp signal 140 to the image signal voltage level received through the bit line 112. As will be discussed in further detail below, in various examples, the ramp generator 114 is a current integrating ramp generator. In various examples, a ramp stabilization time or delay of the ramp signal 140 generated by the ramp generator 114 and received by the comparator circuit 116 is reduced by a low power stabilization assist circuit to increase a maximum frame rate and thus improve performance of the imaging system 100 according to the teachings of this disclosure.

[0023] In an example, digital image data values generated by the ADC 118 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or others).

[0024] In one example, the control circuit 104 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 104 can generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for enabling all pixel circuits 104 within the pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during successive acquisition windows. In another example, image acquisition is synchronized with an illumination effect, such as a flash.

[0025] In one example, the imaging system 100 can be included in a digital camera, a cell phone, a laptop computer, etc. Additionally, the imaging system 100 can be coupled to other pieces of hardware, such as a processor (general purpose or other purpose), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination device / flash, an electrical input (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other pieces of hardware can communicate instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0026] Figure 2 A schematic diagram showing an example of a current integration ramp generator without a low-power ramp stabilization assist circuit is shown. As shown, the current integration ramp generator includes an operational amplifier 224. A first input (e.g., inverting input) of the operational amplifier 224 is coupled to an integration current source 230 to receive an integration current I INT 232. A second input (e.g., non-inverting input) of the operational amplifier 224 is coupled to receive a reference voltage V REF 234. In the depicted example, a switch and capacitor 236 can be coupled to the non-inverting input of the operational amplifier 224 to sample and hold the reference voltage V REF 224 at the non-inverting input of the operational amplifier 224. In the depicted example, a feedback capacitor C F 226 is coupled to the output of the operational amplifier 224 and the inverting input of the operational amplifier 224. A reset switch 228 is also coupled between the output of the operational amplifier 224 and the inverting input of the operational amplifier 224. Figure 2 The depicted example shows an output capacitor C OUT238 is coupled between the output of the operational amplifier 224 and ground. As will be discussed, the current I C 242 represents the current drawn from the output capacitor C OUT 238 as it discharges and the current I IN 240 represents the current drawn by the output of the operational amplifier 224 due to the discharge of the output capacitor C OUT 238.

[0027] Figure 3 is a timing diagram illustrating a non-ideal ramp signal generated by an example current integration ramp generator without a low-power ramp stabilization assist circuit compared to an ideal ramp signal. It will be appreciated that, Figure 3 the signals illustrated in the timing diagram of Figure 2 depicted in the current integration ramp generator of RAMP 320, the input current I IN 340, and the capacitor current I C 342.

[0028] As shown in the example depicted in Figure 3 , the ramp voltage signal V RAMP 320 is initialized to a voltage V CVDN at time TO prior to a ramp event. At time Tl, the ramp event begins, shown by the ramp signal RAMP 344 transitioning to a high level (e.g., “1”) and the reset signal RESET 328 transitioning to a low level (e.g., “0”). In the example, the transition of the reset signal RESET 328 to a low level (e.g., “0”) turns off the reset switch 228 shown in the example of Figure 2 . As such, the ramp event begins at the ramp voltage signal V RAMP 320 at time Tl, and as shown, the voltage ramps down. Ideally, the ramp voltage signal V RAMP 320 should have a sharp corner at time Tl and begin ramping down in a linear fashion as indicated for the ideal ramp signal 384. However, a current integration ramp generator without a low-power ramp stabilization assist circuit according to the teachings of the present disclosure has a non-ideal ramp signal 386 as shown due to the discharge of the output capacitor C OUT 238.

[0029] In particular, at time Tl, when the ramp event or ramp phase begins in the ramp voltage signal V RAMP 320, the integration current I INT232 after feedback capacitor C F 226 and the slope change voltage signal V RAMP The slope begins to drop from 320. At this point, the output capacitor C... OUT 238 needs to be discharged. Therefore, the output of operational amplifier 224 needs to be adjusted to change the ramp voltage signal V. RAMP 320 absorbs input current I IN 340, the input current I IN 340 corresponds to the output capacitor C OUT 238 discharge current I C 342. Specifically, due to the limited bandwidth of operational amplifier 224, the ramp-up voltage signal V RAMP 320 and input current I IN 340 regains stability according to the following equation:

[0030]

[0031]

[0032] Where g m It is the effective transconductance of operational amplifier 224.

[0033] Figure 4 An example of a schematic diagram of a current integration ramp generator with a low-power ramp stabilization auxiliary circuit according to the teachings of the present invention is shown. It should be understood that... Figure 4 The current integral ramp generator with low-power ramp stabilization auxiliary circuit shown in the figure can be used as... Figure 1 The example of the slant generator 114 described herein, and the similarly named and numbered elements described above, are similarly coupled and function in the following text.

[0034] like Figure 4 As shown, the current integrating ramp generator includes an operational amplifier 424. A first input (e.g., an inverting input) of the operational amplifier 424 is coupled to the integrating current source 430 to receive the integrating current I. INT 432. The second input (e.g., the non-inverting input) of operational amplifier 424 is coupled to receive a reference voltage V. REF 434. In the depicted example, switch and capacitor 436 may be coupled to the non-inverting input of operational amplifier 424 to sample and hold the reference voltage V at the non-inverting input of operational amplifier 424. REF 424. In the example described, the feedback capacitor C F 426 is coupled between the output of operational amplifier 424 and the inverting input of operational amplifier 424. Reset switch 428 is also coupled between the output of operational amplifier 424 and the inverting input of operational amplifier 424.Figure 4 The example depicted in FIG. 4A shows the output capacitor C OUT 438 coupled between the output of the operational amplifier 424 and ground. As shown in the depicted example, the auxiliary current source 440 is coupled between the output of the operational amplifier 424 and ground. In the example, the ramping switch 444 is coupled to the auxiliary current source 440 such that the ramping switch 444 and the auxiliary current source 440 are coupled between the output of the operational amplifier 424 and ground.

[0035] In operation, the auxiliary current source 440 is configured to conduct an auxiliary current I ASSIST 446 from the output of the operational amplifier 424 to ground in response to the reset switch 428 being turned off, which corresponds to a ramping event occurring in the ramping voltage V RAMP 420. In the depicted example, the ramping switch 444 is also turned on during the ramping event occurring in the ramping voltage V RAMP 420 in order to conduct the auxiliary current I ASSIST 446 from the output of the operational amplifier 424 to ground during the ramping event. The current I C 442 represents the discharge current from the output capacitor C OUT 438 and the current I IN 440 represents the current absorbed by the output of the operational amplifier 424 due to the discharge of the output capacitor C OUT 438 without the auxiliary current source 440.

[0036] In particular, the auxiliary current I ASSIST 446 is configured to have approximately equal magnitude to the discharge current I RAMP 442 of the output capacitor C OUT 438 during the ramping event in the ramping voltage V C 420. Thus, according to the teachings of the present disclosure, the input current I IN 440 that would otherwise need to be absorbed by the output of the operational amplifier 424 remains approximately zero and the operational amplifier 424 does not need to be re-stabilized. As a result, according to the teachings of the present disclosure, the ramping voltage V RAMP 420 approaches a more ideal ramping signal to a much greater extent with substantially no stabilization time delay and with a sharper corner at the beginning of the ramping event.

[0037] Figure 5 is a timing diagram illustrating signals including a ramping signal generated by an example current integrating ramp generator having a low power ramping stabilization auxiliary circuit according to the teachings of the present disclosure. It should be appreciated that, Figure 5 the signals illustrated in the timing diagram of Figure 4The example depicted in the current integrator ramp generator, and similarly named and numbered elements described above are similarly coupled and function below. In particular, the depicted example shows a ramp signal RAMP 544, a reset signal RESET 528, a ramp voltage signal V RAMP 520, an input current I IN 540, a capacitor current I C 542, an auxiliary current I ASSIST 546, and a power line current I AVDD 548.

[0038] As Figure 5 shown in the example depicted in the current integrator ramp generator, the ramp voltage signal V RAMP 520 is initialized to a voltage V CVDN 0 prior to a ramp event. At time T1, the ramp event begins, shown by the ramp signal RAMP 544 transitioning to a high level (e.g., "1") and the reset signal RESET 528 transitioning to a low level (e.g., "0"). In the example, the ramp signal RAMP 544 transitioning to a high level (e.g., "1") turns on the ramp switch 444 and the reset signal RESET 528 transitioning to a low level (e.g., "0") turns off the reset switch 428. Figure 4 The reset switch 428 shown in the example depicted in the current integrator ramp generator. Thus, the ramp event begins with the ramp voltage signal V RAMP 520 at time T1, and as shown, the voltage ramps down. As will be discussed, the auxiliary current I ASSIST 546 is configured to be substantially equal to the capacitor current I C 542 so that the output capacitor C OUT 438 discharges. As a result, the ramp voltage signal V RAMP 520 has a sharp corner at time T1 and begins to ramp down in a linear fashion with substantially no settling delay as indicated for the ideal ramp signal 584. It will be appreciated that without the auxiliary current source 440 providing the auxiliary current I ASSIST 546, an unideal ramp signal 586 occurs due to the output capacitor C OUT 438 discharging.

[0039] In particular, at time T1, when the ramp event or ramp phase begins in the ramp voltage signal V RAMP 520, the integral current I INT 532 passes through the feedback capacitor C F 526 and the ramp voltage signal V RAMP 520 begins to ramp down. At this time, the output capacitor C OUT 438 needs to discharge the capacitor current I C542discharge. With the auxiliary current source 440 providing an auxiliary current I C 542of approximately zero, which achieves the ideal ramp signal 584 as shown at time Tl. Thus, it should be appreciated that the auxiliary current I ASSIST 4446absorbed by the output I IN 540remains approximately zero, which achieves the ideal ramp signal 584 as shown at time Tl. Thus, it should be appreciated that the auxiliary current I ASSIST 546, the input current I IN 540and the ramp voltage signal V RAMP 520:

[0040]

[0041] I IN (t) = 0, (4)

[0042]

[0043] In operation, it should be further appreciated that the additional power consumption due to the auxiliary current 546 is conserved by turning off the ramp switch 444 during the non-ramp event (e.g., at time TO) or prior to the ramp event at time Tl. Moreover, as Figure 5 shown, it should be appreciated that the supply line current I AVDD 548remains substantially constant or unchanged during the non-ramp event (e.g., at time TO) as well as during the ramp event (e.g., at time Tl ) since the auxiliary current source is coupled between the output of the operational amplifier 424 and ground, rather than between the supply line (e.g., AVDD) and the output of the operational amplifier 424.

[0044] The above description of the illustrated examples of the application (including what is described in the abstract) is not intended to be exhaustive or to limit the application to the precise forms disclosed. While specific examples of the application are described herein for illustrative purposes, various modifications are possible within the scope of the application, as those skilled in the relevant art will recognize.

[0045] These modifications can be made in light of the above detailed description of the application. The terms used in the following claims should not be construed to limit the application to the specific examples disclosed in the specification. Rather, the scope of the application is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures. It is intended to cover and embrace all alternatives, modifications and equivalents included within the scope of the following claims.

Claims

1. A ramp generator comprising: an operational amplifier having a first input, a second input, and an output to generate a ramp signal; an integration current source coupled to the first input of the operational amplifier; a reference voltage coupled to the second input of the operational amplifier; a feedback capacitor coupled between the first input and the output of the operational amplifier; a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off; and an auxiliary current source coupled between the output of the operational amplifier and ground, wherein the auxiliary current source is configured to conduct an auxiliary current from the output of the operational amplifier to ground in response to the reset switch turning off, and wherein the feedback capacitor is coupled between the auxiliary current source and the first input of the operational amplifier.

2. The ramp generator of claim 1, further comprising a reference capacitor coupled between the second input of the operational amplifier and ground.

3. The ramp generator of claim 1, further comprising an output capacitor coupled between the output of the operational amplifier and ground.

4. The ramp generator of claim 3, wherein the auxiliary current is approximately equal to an integration current conducted by the integration current source multiplied by a ratio of a capacitance of the output capacitor to a capacitance of the feedback capacitor.

5. The ramp generator of claim 3, wherein the auxiliary current conducted by the auxiliary current source is approximately equal to a discharge current from the output capacitor during the ramp event configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off.

6. The ramp generator of claim 1, wherein the auxiliary current is zero when the reset switch is configured to turn on to reset the ramp generator.

7. The ramp generator of claim 6, further comprising an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to turn off when the reset switch is configured to turn on, wherein the auxiliary current switch is configured to turn on when the reset switch is configured to turn off.

8. The ramp generator of claim 1, wherein the reset switch is coupled between the auxiliary current source and the first input of the operational amplifier.

9. The ramp generator of claim 1, wherein the reset switch and the feedback capacitor are arranged in parallel with each other between the auxiliary current source and the first input of the operational amplifier.

10. The ramp generator of claim 1, wherein the reset switch and the feedback capacitor are arranged in parallel with each other between the integration current source and the auxiliary current source.

11. An imaging system comprising: a pixel array that receives image light and produces, in response, image charge voltage signals; and readout circuitry coupled to receive the image charge voltage signals from the pixel array and provide, in response, digital representations of the image charge voltage signals, the readout circuitry including a comparator to receive the image charge voltage signals, compare the image charge voltage signals to a ramp signal from a ramp generator, and provide, in response, the digital representations of the image charge voltage signals, wherein the ramp generator comprises: an operational amplifier having a first input, a second input, and an output to produce the ramp signal; an integration current source coupled to the first input of the operational amplifier; a reference voltage coupled to the second input of the operational amplifier; a feedback capacitor coupled between the first input and the output of the operational amplifier; a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off; and an auxiliary current source coupled between the output of the operational amplifier and ground, wherein the auxiliary current source is configured to conduct an auxiliary current from the output of the operational amplifier to ground in response to the reset switch turning off, and wherein the feedback capacitor is coupled between the auxiliary current source and the first input of the operational amplifier.

12. The imaging system of claim 11, wherein the ramp generator additionally comprises a reference capacitor coupled between the second input of the operational amplifier and ground.

13. The imaging system of claim 11, wherein the ramp generator additionally comprises an output capacitor coupled between the output of the operational amplifier and ground.

14. The imaging system of claim 13, wherein the auxiliary current is approximately equal to an integration current conducted by the integration current source multiplied by a ratio of a capacitance of the output capacitor to a capacitance of the feedback capacitor.

15. The imaging system of claim 13, wherein the auxiliary current conducted by the auxiliary current source is approximately equal to a discharge current from the output capacitor during the ramp event configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch turning off.

16. The imaging system of claim 11, wherein the auxiliary current is zero when the reset switch is configured to turn on to reset the ramp generator.

17. The imaging system of claim 16, wherein the ramp generator additionally comprises an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to turn off when the reset switch is configured to turn on, wherein the auxiliary current switch is configured to turn on when the reset switch is configured to turn off.

18. The imaging system of claim 11, wherein the reset switch is coupled between the auxiliary current source and the first input of the operational amplifier.

19. The imaging system of claim 11, wherein the reset switch and the feedback capacitor are arranged in parallel with each other between the auxiliary current source and the first input of the operational amplifier.

20. The imaging system of claim 11, wherein the reset switch and the feedback capacitor are arranged in parallel with each other between the integration current source and the auxiliary current source.

Images