A real-time fault diagnosis and protection method for EMIF parallel bus
By dividing the address domain on the EMIF parallel bus and sending life signals for real-time fault diagnosis, the problem of communication failure between the DSP and FPGA was solved, real-time protection of the EMIF parallel bus was realized, and the safety of the traction converter system was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-11
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, EMIF parallel bus communication faults between DSP and FPGA cannot be diagnosed and protected in real time, leading to the risk of traction converter failure and affecting system safety.
By dividing the control word address field and status word address field on the EMIF parallel bus, and using the address bus, data bus and control bus between the DSP and FPGA to send and receive life signals, real-time fault diagnosis is performed, and protective measures are taken when a fault is diagnosed, such as disconnecting electrical connections or blocking control signals.
It enables timely diagnosis and protection against EMIF parallel bus communication faults, ensuring the safety of the traction converter system and preventing system damage caused by communication failures.
Smart Images
Figure CN116931474B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of traction converter control technology, and in particular to a real-time fault diagnosis and protection method for EMIF parallel bus. Background Technology
[0002] DSPs excel at high-speed data processing, computation, and control, while FPGAs excel at parallel processing, logic processing, and high-speed real-time communication. These combined strengths have led to the widespread application of the DSP+FPGA control architecture in traction converter control. Typically, EMIF parallel bus communication technology is used between the DSP and FPGA, with the DSP acting as the master controller and the FPGA serving as external memory. In existing EMIF parallel bus communication technology, a problem with either the DSP or FPGA, or a problem with the parallel bus signal between the DSP and FPGA, can cause traction converter failure or even burnout. For example, if the DSP program pointer runs out of control, the FPGA cannot communicate normally with the DSP via the parallel bus. If the FPGA does not implement logic protection measures, it may lead to a risk of the traction converter exploding, causing significant economic and social harm. Similarly, if the FPGA is reset due to strong electromagnetic interference, and the DSP does not implement control protection measures, this could also cause a major traction converter failure.
[0003] Currently, a search of existing technologies only yielded methods for parallel bus communication between DSPs and FPGAs. No effective real-time diagnostic and protection methods were found for faults occurring between the two or any part of the parallel bus. Since a fault in the parallel bus between the DSP and FPGA has a fatal impact on the traction converter, it is urgent to research and propose corresponding diagnostic and protection methods. Summary of the Invention
[0004] To address one of the problems existing in the prior art, this invention provides a real-time fault diagnosis and protection method for EMIF parallel buses.
[0005] This invention provides a real-time fault diagnosis and protection method for an EMIF parallel bus. One end of the EMIF parallel bus is connected to a DSP, and the other end is connected to an FPGA. The FPGA is connected to a traction converter power circuit. The EMIF parallel bus includes an address bus, a data bus, and a control bus. The method includes:
[0006] The memory area in the FPGA is divided into the control word address field and the status word address field based on the address width of the address bus and the data width of the data bus.
[0007] The DSP sends a DSP write life signal to the FPGA via the address bus, data bus and control bus. The FPGA reads the DSP write life signal and writes it into the first preset address in the control word address field to form the FPGA write life signal. The FPGA read life signal is generated based on the FPGA write life signal written in the first preset address. The FPGA read life signal is stored in the second preset address in the status word address field.
[0008] The DSP reads the FPGA read life signal from the second preset address in the status word address field via the address bus, data bus, and control bus to form the DSP read life signal;
[0009] Real-time fault diagnosis is performed based on the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP, and first-class protection measures are taken when a fault is diagnosed.
[0010] Furthermore, the FPGA generates the FPGA read life signal based on the FPGA write life signal written in the first preset address by inverting the bits of the FPGA write life signal written in the first preset address and using it as the FPGA read life signal.
[0011] Furthermore, the method of sending a DSP write life signal to the FPGA via the address bus, data bus, and control bus includes: when the timing period reaches the preset control cycle, determining whether the value of the DSP write life signal is less than a first preset threshold. If so, the value of the DSP write life signal is incremented by 1 and then sent to the FPGA via the address bus, data bus, and control bus. If not, the value of the DSP write life signal is cleared to zero and then sent to the FPGA via the address bus, data bus, and control bus.
[0012] Furthermore, real-time fault diagnosis based on the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP includes: determining whether the read DSP read life signal is equal to the bitwise inversion of the corresponding sent DSP write life signal. If yes, it is diagnosed as no fault and the fault flag on the DSP is cleared. If no, it is diagnosed as a fault and the fault flag on the DSP is set.
[0013] Furthermore, the first type of protection measure taken when a fault is diagnosed is to disconnect the traction converter power circuit from the power supply and / or load.
[0014] Furthermore, the method also includes: using the FPGA to perform real-time fault diagnosis based on the FPGA write life signal in the first preset address, and taking second-class protection measures when a fault is diagnosed.
[0015] Furthermore, real-time fault diagnosis using the FPGA based on the FPGA write life signal within the first preset address includes:
[0016] Determine the relationship between the FPGA write life signal currently written to the first preset address and the FPGA write life signal previously written to the first preset address. If the absolute value of the difference between the two signals is 1 or the sum of the two signals is equal to the first preset threshold, then the system is diagnosed as fault-free, the FPGA fault timer variable is cleared to zero, and the FPGA fault flag is cleared to zero.
[0017] If the absolute value of the difference between two signals is not equal to 1 and the sum of the two signals is not equal to the first preset threshold, the fault timing variable on the FPGA side is increased by 1 until it reaches the second preset threshold, at which point a fault is diagnosed and the fault flag on the FPGA side is set.
[0018] Furthermore, the second type of protection measure taken when a fault is diagnosed is to block the control signal of the traction converter power circuit.
[0019] Furthermore, the first preset threshold is not less than 10.
[0020] Furthermore, the second preset threshold is equal to the sum of the preset control period and the tolerance duration, wherein the ratio of the tolerance duration to the preset control period is less than 0.5.
[0021] This invention provides a real-time fault diagnosis and protection method for an EMIF parallel bus. The method utilizes a DSP to send a write life signal for fault diagnosis to an FPGA via the EMIF parallel bus. The FPGA reads the write life signal and writes it into a first preset address in the control word address field. It then generates a read life signal based on the written write life signal and stores it in a second preset address in the status word address field for the DSP to read. Thus, based on the write life signal sent by the DSP and the read life signal read, communication faults in the EMIF parallel bus can be diagnosed in real time, and corresponding protective measures can be taken. This method is based on logical judgment, is simple to operate, easy to implement, and requires no additional hardware. It can promptly diagnose communication faults in the EMIF parallel bus and ensure the safety of the traction converter system by taking appropriate protective measures. Attached Figure Description
[0022] The accompanying drawings, which form part of this specification, are provided to further illustrate embodiments of the invention and, together with the textual description, explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.
[0023] Figure 1A schematic flowchart of a real-time fault diagnosis and protection method for an EMIF parallel bus provided according to a specific embodiment of the present invention is shown.
[0024] Figure 2 A schematic diagram of the EMIF parallel bus communication hardware architecture between the DSP and FPAG provided according to a specific embodiment of the present invention is shown.
[0025] Figure 3 A schematic diagram of FPGA memory region address division according to a specific embodiment of the present invention is shown;
[0026] Figure 4 A schematic diagram of a traction converter control system according to a specific embodiment of the present invention is shown;
[0027] Figure 5 A schematic diagram of the DSP-side EMIF parallel bus communication process provided according to a specific embodiment of the present invention is shown;
[0028] Figure 6 A schematic diagram of the FPGA-side EMIF parallel bus communication process according to a specific embodiment of the present invention is shown.
[0029] Figure 7 A schematic diagram of the DSP-side EMIF communication fault diagnosis and protection process according to a specific embodiment of the present invention is shown;
[0030] Figure 8 A schematic diagram of the FPGA-side EMIF communication fault diagnosis and protection process provided according to a specific embodiment of the present invention is shown. Detailed Implementation
[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0033] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0034] like Figure 1 As shown, according to a specific embodiment of the present invention, a real-time fault diagnosis and protection method for an EMIF parallel bus is provided. One end of the EMIF parallel bus is connected to a DSP, and the other end is connected to an FPGA. The FPGA is connected to a traction converter power circuit. The EMIF parallel bus includes an address bus, a data bus, and a control bus. The method includes:
[0035] S1, the memory area in the FPGA is divided into the control word address field and the status word address field according to the address width of the address bus and the data width of the data bus;
[0036] S2, the DSP sends a DSP write life signal to the FPGA through the address bus, data bus and control bus. The FPGA reads the DSP write life signal and writes it into the first preset address in the control word address field to form an FPGA write life signal. The FPGA read life signal is generated based on the FPGA write life signal written in the first preset address. The FPGA read life signal is stored in the second preset address in the status word address field.
[0037] S3, using the DSP to read the FPGA read life signal in the second preset address of the status word address field through the address bus, data bus and control bus to form the DSP read life signal;
[0038] S4 performs real-time fault diagnosis based on the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP, and takes first-class protection measures when a fault is diagnosed.
[0039] This method provides a real-time fault diagnosis and protection approach for the EMIF parallel bus. The method utilizes a DSP to send a write life signal for fault diagnosis to an FPGA via the EMIF parallel bus. The FPGA reads the write life signal and writes it into a first preset address in the control word address field. It then generates a read life signal based on the written life signal and stores it in a second preset address in the status word address field for the DSP to read. Thus, based on the write life signal sent by the DSP and the read life signal read, communication faults in the EMIF parallel bus can be diagnosed in real time, and corresponding protective measures can be taken. This method is based on logical judgment, is simple to operate, easy to implement, and requires no additional hardware. It can promptly diagnose communication faults in the EMIF parallel bus and ensure the safety of the traction converter system by taking appropriate protective measures. Compared with existing technologies, the technical solution of this invention can solve the technical problem that existing technologies cannot perform real-time diagnosis and protection of EMIF parallel bus communication faults between the DSP and FPGA, resulting in low safety of the traction converter system.
[0040] As a specific embodiment of the present invention, such as Figure 2 As shown, the EMIF parallel bus of the DSP and FPGA includes the address bus Bus_A, the data bus Bus_D, and the control bus. The control signals on the control bus include the chip select signal DSP_CS, the write signal DSP_WE, and the read signal DSP_RD. The address bus Bus_A has an address width of 8 bits to 32 bits, and the data bus Bus_D has a data width of 8 bits to 32 bits. It is a bidirectional bus with three working states: high impedance, input, and output. When the chip select signal DSP_CS is 0, the data bus Bus_D is set to high impedance, releasing the data bus. When the DSP_CS chip select signal is 1 but the write signal DSP_WE and the read signal DSP_RD are both 0, the data bus Bus_D is also set to high impedance, releasing the data bus. When the chip select signal DSP_CS is 1, EMIF communication between the DSP and the FPGA is possible. In this case, if the write signal DSP_WE is 1, the DSP can write control words to the control word address field of the FPGA's buffer (i.e., the memory area). If the read signal DSP_RD is 1, the DSP can read the status word from the status word address field of the FPGA's data buffer (i.e., the memory area). Note that the write signal DSP_WE and the read signal DSP_RD cannot be active simultaneously; that is, neither signal can be 1 at the same time.
[0041] The control word address field and status word address field proposed in this invention do not overlap. Please refer to [reference needed]. Figure 3 In this embodiment, the FPGA memory area corresponding to the address width of the address bus Bus_A and the data width of the data bus Bus_D is divided into a control word address field Addr_CtrlWord and a status word address field Addr_StateWord. The control word address field Addr_CtrlWord is divided into N addresses (Addr0 to Addr(N-1)) based on the type N of the control word, used to write N types of control words CtrlWord0 to CtrlWord(N-1) respectively. The status word address field Addr_StateWord is divided into N addresses (AddrN to Addr(2N-1)) for the N types of status words generated corresponding to the N types of control words, used to write N types of status words StateWord0 to StateWord(N-1) respectively. Addr0 is the starting address of the control word address field, and so on. AddrN is the starting address of the status word address field, and so on. There is a one-to-one correspondence between the status words and their addresses. The specific correspondence can be set as needed. For example, the first type of status word StateWord0 is generated based on the first type of control word CtrlWord0, and both are located at the starting addresses of the two address fields. To write each type of control word to the corresponding address, the specific address of the control word address field can be determined by the address index AddrWE_Index. To read the status word corresponding to the control word, the specific address of the status word address field can be determined by the address index AddrRD_Index.
[0042] In this embodiment of the invention, the write life signal is one type of N-class control word, and the read life signal is one type of N-class status word, used for communication fault diagnosis. As a specific embodiment of the invention, sending a DSP write life signal to an FPGA via the address bus, data bus, and control bus includes: when a preset control cycle is reached at a given time, determining whether the value of the DSP write life signal is less than a first preset threshold; if so, incrementing the value of the DSP write life signal by 1 and sending it to the FPGA via the address bus, data bus, and control bus; if not, clearing the value of the DSP write life signal to zero and sending it to the FPGA via the address bus, data bus, and control bus. The first preset threshold is determined according to actual needs; for example, in this embodiment of the invention, the first preset threshold is not less than 10. Furthermore, the first and second preset addresses corresponding to the FPGA write life signal FPGALiveWE_Data and the FPGA read life signal FPGALiveRD_Data are selected as needed. As a specific embodiment of the present invention, the first preset address is selected as the starting address Addr0 of the control word address field, and the second preset address is selected as the starting address AddrN of the status word address field. That is, the FPGA writes the DSP write life signal DSPLiveWE_Data read from the data bus Bus_D to the starting address Addr0 in the control word address field to form the FPGA write life signal FPGALiveWE_Data. Then, based on the FPGA write life signal FPGALiveWE_Data written in the starting address Addr0, the FPGA read life signal FPGALiveRD_Data, i.e., the status word, is generated and stored in the starting address AddrN of the status word address field.
[0043] Furthermore, the generation relationship between the FPGA write life signal FPGALiveWE_Data and the FPGA read life signal FPGALiveRD_Data is determined as needed. In a specific embodiment of the invention, the FPGA generates the FPGA read life signal based on the FPGA write life signal written to the first preset address as follows: the FPGA inverts the bits of the FPGA write life signal written to the first preset address (the starting address Addr0 in the control word address field) and uses this as the FPGA read life signal. Based on this embodiment, if communication is normal, the FPGA read life signal FPGALiveRD_Data should be the bit-inverted result of the DSP write life signal DSPLiveWE_Data sent by the DSP. Therefore, if the two signals do not conform to this rule, it indicates a communication failure. That is, real-time fault diagnosis based on the DSP write life signal sent by the DSP and the read DSP read life signal includes: determining whether the read DSP read life signal is equal to the bit-inverted result of the corresponding sent DSP write life signal. If yes, it is diagnosed as no fault, and the DSP fault flag is cleared; if no, it is diagnosed as a fault, and the DSP fault flag is set.
[0044] Based on the above embodiments, the first type of protection measure taken when a fault is diagnosed is to disconnect the electrical connection between the traction converter power circuit and the power supply and / or load.
[0045] To better understand the real-time fault diagnosis and protection method proposed in this invention, the following is combined with... Figure 4 , Figure 5 , Figure 6 and Figure 7 The embodiments illustrate the diagnostic and protection process in detail, such as Figure 4 As shown, a typical traction converter control system consists of a DSP, FPGA, PLC, or other industrial controller. To implement the aforementioned first type of protection measures, this invention sets an input switch (knife switch) S1 between the traction converter power circuit and the power supply, and an output switch (knife switch) S2 between the traction converter power circuit and the load. The DSP and FPGA communicate via an EMIF parallel bus. To ensure real-time data refresh, the control period Actual_time, i.e., the data refresh period, is generally 100–500 μs, determined according to specific needs, for example, 100 μs. Moreover, since the DSP and FPGA directly control the high-power electronic devices in the traction converter power circuit, control deviations will lead to very serious consequences. Therefore, the reliability requirements for real-time communication between the DSP and FPGA are high. The PLC or other industrial controller can be used to control the knife switch of the power supply or load, realizing the opening and closing control of the power supply or load. This knife switch control can also be directly controlled by the DSP after electrical isolation.
[0046] Please refer to the EMIF parallel bus communication process between the DSP and FPGA. Figure 5 and Figure 6 In this embodiment, the first address of the control word address field, Addr0, is used as the first preset address, and the first address of the status word address field, AddrN, is used as the second preset address. System initialization is performed first, including clock initialization, timer interrupt initialization, peripheral initialization, and port initialization. EMIF communication and fault diagnosis between the DSP and FPGA can be completed in a timer interrupt or main loop. The FPGA is written to first and then read from, ensuring that the time intervals for updating data within the FPGA are equal. The FPGA-side program executes on the rising edge of each system clock, which is generally not less than 10MHz. When the DSP_CS chip select signal is 1, the write signal DSP_WE is 1, and the read signal DSP_RD is 0, the FPGA reads the Bus_D data bus and stores it at the local address AddrWE_Index. If the address of AddrWE_Index is Addr0, the data transmitted in the Bus_D data bus is stored in the variable FPGA write life signal FPGALiveWE_Data. Meanwhile, on the DSP side, the DSP program runs periodically. When the timing reaches the preset control period Actual_time, it checks whether the value of the DSP write life signal DSPLiveWE_Data is less than the first preset threshold Max. If so, the value of DSPLiveWE_Data is incremented by 1 and written to the starting address Addr0 of the FPGA's control word address field, forming FPGALiveWE_Data. The DSP then writes the data corresponding to the remaining control word addresses of the FPGA. If not, the value of DSPLiveWE_Data is cleared and written to the starting address Addr0 of the FPGA's control word address field, forming FPGALiveWE_Data. After completing the write operation, the DSP reads all the status words of the FPGA and then performs DSP-side EMIF fault diagnosis and processing.
[0047] The flowchart for DSP-side EMIF fault diagnosis and handling is as follows: Figure 7As shown, when the chip select signal DSP_CS is 1, and the write signal DSP_WE is 0 and the read signal DSP_RD is 1, the FPGA writes the address data of AddrRD_Index to the Bus_D data bus. If the address of AddrRD_Index is AddrN, the DSP reads the FPGA read life signal FPGALiveRD_Data in AddrN through the Bus_D data bus and assigns it to the DSP's online state vector, i.e., the DSP read life signal DSPLiveRD_Data. If DSPLiveRD_Data is equal to the bitwise inversion of the control word DSPLiveWE_Data written by the DSP, then the EMIF communication is diagnosed as normal. At this time, the DSP fault flag DSP_EMIF_ERR is cleared to zero. Otherwise, the EMIF communication is diagnosed as faulty, the DSP fault flag DSP_EMIF_ERR is set, and the input switch S1 and the output switch S2 are turned off, thereby protecting the traction converter.
[0048] The above provides a fault diagnosis and protection method for the DSP side. To further improve the EMIF communication security between the DSP and FPGA, the proposed diagnosis and protection method further includes: using the FPGA to perform real-time fault diagnosis based on the FPGA write life signal within a first preset address, and taking a second type of protection measure when a fault is diagnosed. In this way, communication faults are diagnosed and protection measures are taken from the FPGA side.
[0049] In this embodiment of the invention, real-time fault diagnosis using an FPGA based on an FPGA write life signal within a first preset address includes:
[0050] Determine the relationship between the FPGA write life signal currently written to the first preset address and the FPGA write life signal previously written to the first preset address. If the absolute value of the difference between the two signals is 1 or the sum of the two signals is equal to the first preset threshold, then the system is diagnosed as fault-free, the FPGA fault timer variable is cleared to zero, and the FPGA fault flag is cleared to zero.
[0051] If the absolute value of the difference between two signals is not equal to 1 and the sum of the two signals is not equal to the first preset threshold, the fault timing variable on the FPGA side is increased by 1 until it reaches the second preset threshold, at which point a fault is diagnosed and the fault flag on the FPGA side is set.
[0052] As a specific embodiment of the present invention, the second preset threshold is equal to the sum of the preset control period Actual_time and the tolerance duration TimeToleratence, wherein the ratio of the tolerance duration to the preset control period is less than 0.5, that is, the value of TimeToleratence / Actual_time is less than 0.5.
[0053] Furthermore, the second type of protection measure taken when a fault is diagnosed is to block the control signal of the traction converter power circuit.
[0054] The following is combined with Figure 8 The embodiment illustrates the EMIF fault diagnosis and protection process on the FPGA side. The FPGA assigns the currently read variable—DSP write life signal DSPLiveWE_Data—to FPGALiveWE_Data1, and simultaneously assigns the previous value of FPGALiveWE_Data1 to FPGALiveWE_Data2. If the absolute value of the difference between FPGALiveWE_Data1 and FPGALiveWE_Data2 is 1, or their sum equals a first preset threshold Max, that is, if the absolute value of the difference between the currently read write life signal and the previously read write life signal is 1, or their sum equals a first preset threshold Max, then a communication failure is diagnosed. Normally, the FPGA_EMIF_ERR fault bit is cleared to zero, and the fault timing variable TimeCnt_us is also cleared to zero, indicating that EMIF communication is normal. Otherwise, it is further determined whether the fault timing variable TimeCnt_us has reached the second preset threshold (Actual_time + TimeTolerance). If it has not reached the threshold, the fault timing variable TimeCnt_us is incremented by 1, and TimeCnt_us is incremented once every 1μs. If it has reached the threshold, the FPGA-side fault flag FPGA_EMIF_ERR is set, which is diagnosed as an EMIF communication fault. At the same time, the control signal of the power unit PWM, i.e. the traction converter power circuit, is blocked, thereby protecting the traction converter.
[0055] In this embodiment of the invention, Figures 5 to 8 The diagnostic and protection process example shown can be implemented through a corresponding program. In this way, real-time fault diagnosis results can be output, and the traction converter control system can be locked or powered off based on the fault diagnosis results, thereby ensuring the safety of the traction converter.
[0056] In general, the main principle of the diagnostic and protection method proposed in this invention is as follows: During the parallel bus communication between the DSP and FPGA via the EMIF, the DSP writes a changing variable to the FPGA in real time (DSP write life signal DSPLiveWE_Data). Then, the FPGA judges whether the variable conforms to the set rule. If it does, it means that the control word sent by the DSP to the FPGA is normal in real time. If it does not conform to the set rule, the FPGA diagnoses an EMIF communication fault and blocks the PWM control signal of the power unit, thereby effectively protecting the traction converter. The FPGA feeds back to the DSP in real time the variable that is bitwise inverted from the received write life signal (FPGA read life signal FPGALiveRD_Data). Then, the DSP judges whether the received status word conforms to the set logic. If it does, it means that the status word sent by the FPGA to the DSP is normal in real time. If it does not conform to the set logic, the DSP diagnoses an EMIF communication fault and shuts off the input switch S1 and the output switch S2, thereby protecting the traction converter.
[0057] In summary, this invention provides a real-time fault diagnosis and protection method for an EMIF parallel bus. This method utilizes a DSP to send a write life signal for fault diagnosis to an FPGA via the EMIF parallel bus. The FPGA reads the write life signal and writes it into a first preset address in the control word address field. It also generates a read life signal based on the written write life signal and stores it in a second preset address in the status word address field for the DSP to read. Thus, based on the write life signal sent by the DSP and the read life signal read, communication faults in the EMIF parallel bus can be diagnosed in real time, and corresponding protective measures can be taken. This method is based on logical judgment, is simple to operate, easy to implement, and requires no additional hardware. It can promptly diagnose communication faults in the EMIF parallel bus and ensure the safety of the traction converter system by taking appropriate protective measures. Compared with existing technologies, the technical solution of this invention can solve the technical problem that existing technologies cannot perform real-time diagnosis and protection of EMIF parallel bus communication faults between the DSP and FPGA, resulting in low safety of the traction converter system.
[0058] In the description of this invention, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this invention; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.
[0059] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.
[0060] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.
[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A real-time fault diagnosis and protection method for an EMIF parallel bus, characterized in that, The EMIF parallel bus is connected to a DSP at one end and an FPGA at the other end. The FPGA is connected to the traction converter power circuit. The EMIF parallel bus includes an address bus, a data bus, and a control bus. The method includes: The memory region in the FPGA is divided into a control word address field and a status word address field based on the address width of the address bus and the data width of the data bus. The DSP sends a DSP write life signal to the FPGA via the address bus, the data bus, and the control bus. The FPGA reads the DSP write life signal and writes it into a first preset address in the control word address field to form an FPGA write life signal. It also generates an FPGA read life signal based on the FPGA write life signal written into the first preset address. The FPGA read life signal is stored in a second preset address in the status word address field. Sending the DSP write life signal to the FPGA via the address bus, the data bus, and the control bus includes: when a preset control period is reached, determining whether the value of the DSP write life signal is less than a first preset threshold. If so, the value of the DSP write life signal is incremented by 1 and sent to the FPGA via the address bus, the data bus, and the control bus, and the value of the DSP write life signal is incremented by 1 and assigned to the DSP write life signal. If not, the value of the DSP write life signal is cleared to zero and sent to the FPGA via the address bus, the data bus, and the control bus. The DSP uses the address bus, the data bus, and the control bus to read the FPGA read life signal in the second preset address of the status word address field to form a DSP read life signal; Real-time fault diagnosis is performed based on the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP, and first-class protection measures are taken when a fault is diagnosed. The FPGA performs real-time fault diagnosis based on the FPGA write life signal in the first preset address and takes a second type of protection measure when a fault is diagnosed. This includes: determining the relationship between the FPGA write life signal currently written to the first preset address and the FPGA write life signal previously written to the first preset address; if the absolute value of the difference between the two signals is 1 or the sum of the two signals is equal to the first preset threshold, then the fault is diagnosed as no fault, the FPGA fault timer variable is cleared to zero, and the FPGA fault flag is cleared to zero; if the absolute value of the difference between the two signals is not equal to 1 and the sum of the two signals is not equal to the first preset threshold, then the FPGA fault timer variable is increased by 1 until it reaches the second preset threshold, at which point a fault is diagnosed, and the FPGA fault flag is set.
2. The method according to claim 1, characterized in that, The FPGA generates the FPGA read life signal based on the FPGA write life signal written in the first preset address by inverting the bits of the FPGA write life signal written in the first preset address and using it as the FPGA read life signal.
3. The method according to claim 2, characterized in that, Real-time fault diagnosis based on the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP includes: determining whether the read DSP read life signal is equal to the bitwise inverse of the corresponding sent DSP write life signal; if so, the fault is diagnosed as no fault and the fault flag on the DSP is cleared; if not, the fault is diagnosed as a fault and the fault flag on the DSP is set.
4. The method according to claim 3, characterized in that, The first type of protection measure to be taken when a fault is diagnosed is to disconnect the traction converter power circuit from the power supply and / or load.
5. The method according to claim 4, characterized in that, The second type of protection measure taken when a fault is diagnosed is to block the control signal of the traction converter power circuit.
6. The method according to claim 5, characterized in that, The first preset threshold is not less than 10.
7. The method according to claim 6, characterized in that, The second preset threshold is equal to the sum of the preset control period and the tolerance duration, wherein the ratio of the tolerance duration to the preset control period is less than 0.5.
Citation Information
Patent Citations
General control device and method for source network load storage interactive system
CN112688349A