FPGA firmware encryption method and device

Abstract

The present invention relates to an FPGA firmware encryption method and device. The FPGA firmware is stored on a FLASH chip, and includes a functional firmware for configuring the FPGA chip. The FPGA firmware encryption method includes the following steps: when the functional firmware is running, first search for an encryption completion flag of a specified address position of the FLASH chip; if the encryption completion flag can be found, then continue to compare whether the first encrypted data generated by the functional firmware is the same as the second encrypted data stored in the specified address position of the FLASH chip; if the first encrypted data is the same as the second encrypted data, the functional firmware operates normally; if the first encrypted data is different from the second encrypted data, the functional firmware exits operation. The beneficial effect of the present invention is that at least one embodiment of the invention provides a low-cost FPGA firmware encryption solution for any FPGA chip that supports multiboot (multi-image) function, not limited to high-end chips.

Description

Technical Field

[0001] The present invention relates to the technical field of data security and relates to an FPGA firmware encryption method and device. Background Art

[0002] FPGA has the characteristics of high integration and reconfiguration. Therefore, using FPGA in hardware circuits can not only reduce the area of ​​the circuit, but also update the function of the circuit by reconfiguring the FPGA, shortening the development cycle of re-making the board in the past to modify the hardware circuit and reducing the cost, greatly improving the flexibility of the entire system. Therefore, digital systems based on FPGA have achieved rapid development and have been widely used. However, the common FPGA internal circuits on the market are based on SRAM technology, and the configuration data cannot be saved after power failure. Therefore, the configuration data in the external memory must be read when the power is turned on to work normally. The configuration data is generally stored in the FLASH chip and is easy to be stolen. Because the FPGA design can be cloned, it will cause great losses to the developers and owners of the FPGA design.

[0003] In order to protect the security of FPGA configuration data, the existing encryption technology, taking Xilinx's 7 series Xilinx FPGA chip as an example, stores the encryption key in the on-chip dedicated RAM, which can be stored in BBRAM or eFUSE. The encryption key can only be programmed into the device through the JTAG port, and the incoming bitstream is decrypted during configuration. The 7 series AES encryption logic uses a 256-bit encryption key. The on-chip AES decryption logic cannot be used for any purpose other than bitstream decryption. The AES decryption logic is not available to user designs and cannot be used to decrypt data other than the configuration bitstream. This encryption method is good, but there are several problems: 1. It can only be used in mid-to-high-end 7 series and above chips, and low-end chips, such as the 6 series, cannot use this method; 2. The BBRAM method of storing encryption keys requires the board battery to be powered, and it cannot work if the battery is dead. Moreover, designing batteries on the board also increases additional costs and wastes space. 3. Use eFUSE to save the key. This burning is a one-time (OTP) process. The key cannot be changed again after burning. If the key is forgotten, the firmware cannot be upgraded later. If the parameters are not set properly, the board may be burned. 4. Regardless of the storage method, it is not suitable for batch firmware burning, because each board must be burned with a key using JTAG. It cannot be mass-produced and is only suitable for small batch sample generation and processing. Summary of the invention

[0004] At least one aspect of the present invention provides a method for encrypting FPGA firmware, wherein the FPGA firmware is stored on a FLASH chip, the FPGA firmware includes a functional firmware for configuring the FPGA chip, and the FPGA firmware encryption method includes the following steps:

[0005] When the functional firmware is running, it first searches for the encryption completion flag of the designated address bit of the FLASH chip;

[0006] If the encryption completion flag can be found, continue to compare whether the first encrypted data generated by the functional firmware is the same as the second encrypted data stored in the designated address position of the FLASH chip;

[0007] If the first encrypted data is the same as the second encrypted data, the functional firmware operates normally; if the first encrypted data is different from the second encrypted data, the functional firmware exits operation;

[0008] The first flag data and the second flag data are generated based on two source data using the same encryption algorithm, and the source data is selected from any one of a unique ID of an FPGA chip, a unique ID of a FLASH chip, and a fixed number.

[0009] At least one aspect of the present invention also provides an FPGA firmware encryption device, which includes at least one processor; and a memory storing instructions, which, when executed by at least one processor, implement the steps of the method described in the present invention.

[0010] The beneficial effect of the present invention is that at least one embodiment of the invention provides a low-cost FPGA firmware encryption solution for any FPGA chip supporting multiboot (multi-image) function, not limited to high-end chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Topological diagram of the working principle of FLASH chip and FPGA chip in some embodiments;

[0012] Figure 2 Schematic diagram of FPGA firmware encryption method of some embodiments;

[0013] FIG3 is a schematic diagram of a method for encrypting FPGA firmware in some embodiments;

[0014] Figure 4 Schematic diagram of an FPGA firmware encryption device of some embodiments;

[0015] in, Figure 2 The multiboot in FIG3 represents multi-image, and the multiboot function can be implemented by a multi-image update module. DETAILED DESCRIPTION

[0016] Various aspects of the present disclosure will now be explained with reference to the accompanying drawings. As long as the shapes, relative positions and other aspects of the components described in these aspects are not clearly defined, the scope of the present disclosure is not limited to the components shown, which are only used for illustrative purposes. In addition, although many details are set forth, it should be understood that some aspects of the present disclosure can be implemented without these details. In other cases, well-known circuits, structures and technologies are not shown in detail to avoid obscuring the understanding of the description.

[0017] Explanation of terms

[0018] RAM (Random Access Memory) refers to random access memory.

[0019] SRAM (Static Random-Access Memory) refers to static random access memory.

[0020] JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), mainly used for internal chip testing.

[0021] Firmware is the driver written into the FPGA chip.

[0022] Please refer to Figure 1 , Figure 2 As shown, some embodiments of the present invention relate to an FPGA firmware encryption method, wherein the FPGA firmware is stored on a FLASH chip 1, the FPGA firmware includes a functional firmware for configuring the FPGA chip 2, and the FPGA firmware encryption method includes the following steps:

[0023] S1: When the functional firmware is running, first search for the encryption completion flag of the designated address bit of the FLASH chip;

[0024] S2: If the encryption completion flag can be found, continue to compare whether the first encrypted data generated by the functional firmware is the same as the second encrypted data stored in the designated address position of the FLASH chip;

[0025] S3: If the first encrypted data is the same as the second encrypted data, the functional firmware operates normally; if the first encrypted data is different from the second encrypted data, the functional firmware exits operation;

[0026] The first encrypted data and the second encrypted data are generated based on two source data using the same encryption algorithm, and the source data is selected from any one of a unique ID of an FPGA chip, a unique ID of a FLASH chip, and a fixed number.

[0027] In the technical solutions of these embodiments, Figure 3-1 As shown, the unique code (or DNA ID) of the FPGA chip and the FLASH chip can be obtained, that is, the DNA ID (56bit) of the FPGA chip itself and the unique ID (64bit) data of the FLASH chip itself are obtained, such as the full range of Xilinx chips, Micron or 25 series FLASH chips of other manufacturers, and these unique codes are used for encryption. If a chip does not support the function of obtaining a unique code, a fixed number can be used instead, but there must be a chip that supports a unique code. The specific functions of the functional firmware of the present invention are not limited, for example, it can be a network card function, its normal operation means that the network port can be started, and its exit from operation means that the network port is turned off to start.

[0028] In the FPGA firmware encryption method according to some embodiments of the present invention, after step S1, if the encryption completion flag cannot be found, the following steps are continued:

[0029] The functional firmware jumps to the address of the encrypted firmware (also called encrypted firmware program) stored on the FLASH chip through the multi-image update module of the FPGA chip;

[0030] If the encrypted firmware exists, the second encrypted data is generated and stored in the specified address bit corresponding to the encryption completion flag of the FLASH chip; if the encrypted firmware does not exist, the functional firmware exits operation and outputs a prompt that loading the encrypted firmware failed.

[0031] In these embodiments, the combination Figure 3-2 As shown, if the encryption completion flag (such as AA995588) is not obtained in the previous step, it means that the functional firmware is running for the first time, then the multi-image update module (with multiboot function) jumps to the location where the encrypted firmware program is stored to run. The encrypted firmware program mainly generates an encryption completion flag (also called an encryption completion flag, such as AA995588) and the second encrypted data.

[0032] In some embodiments of the present invention, the FPGA firmware encryption method further includes, after the second encrypted data is stored in the designated address bit corresponding to the encryption completion flag of the FLASH chip:

[0033] Erasing the encrypted firmware stored on the FLASH chip.

[0034] In some embodiments of the present invention, the FPGA firmware encryption method is provided, wherein the two source data include at least one of the following:

[0035] FPGA chip unique ID, FLASH chip unique ID; FPGA chip unique ID and a fixed number; or, FLASH chip unique ID and a fixed number.

[0036] Some embodiments of the present invention relate to a method for encrypting FPGA firmware, wherein the FPGA firmware is stored on a FLASH chip, and includes:

[0037] Generate a firmware file by using the functional firmware and the encryption firmware, wherein the functional firmware is placed at the FLASH 0-bit address of the firmware file, and the encryption firmware is placed at the FLASH high-bit address of the firmware file;

[0038] Burn the firmware file into the FLASH chip.

[0039] In these embodiments, a batch production method is provided. First, the two firmwares are generated into an mcs firmware file, the functional firmware is placed at the flash address 0, and the encryption firmware is placed at the high address part of the flash, for example: 24'hE00000 (flash address, which must be consistent with the address to which multiboot in the main functional firmware jumps). Then this mcs file is batch burned to the flash chip through the burning function. Then it is soldered to the FPGA circuit board, and the encrypted firmware can be automatically run when the FPGA is powered on for the first time, and it automatically deletes itself, and stores the AA995588 flag and the encrypted data. After the second startup, the main functional firmware can run normally, while the illegally copied firmware cannot be executed normally due to the different DNAID of the FPGA chip or the flash chip ID, thereby achieving the purpose of encryption.

[0040] In the FPGA firmware encryption method involved in some embodiments of the present invention, the FLASH high-order address where the encrypted firmware is stored in the firmware file is consistent with the address of the encrypted firmware stored in the functional firmware.

[0041] Some embodiments of the present invention involve FPGA firmware encryption methods, wherein the algorithms include but are not limited to AES, DES, and custom algorithms, wherein the custom algorithms are symmetric algorithms. In an optional embodiment of the present invention, the encryption initiative is entirely in the hands of the user, as long as the data can be restored. For example, +1 can be used for encryption and -1 can be used for decryption.

[0042] The FPGA firmware encryption method according to some embodiments of the present invention comprises the following steps after generating the second encrypted data and storing it in the designated address bit corresponding to the encryption completion flag of the FLASH chip if the encrypted firmware exists:

[0043] The functional firmware reruns to search for the encryption completion flag at the designated address position of the FLASH chip.

[0044] The FPGA firmware encryption method according to some embodiments of the present invention further comprises the following steps after erasing the encrypted firmware stored on the FLASH chip:

[0045] The encrypted firmware jumps to the address of the functional firmware stored on the FLASH chip through the multi-image update module of the FPGA chip.

[0046] like Figure 4 As shown, some embodiments of the present invention involve an FPGA firmware encryption device 100, which includes at least one processor 200; and a memory 300, which stores instructions. When the instructions are executed by at least one processor, the steps of the method described in the embodiment of the present invention are implemented.

[0047] Specific implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the activities recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes described in the accompanying drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. A method for encrypting FPGA firmware, wherein the FPGA firmware is stored on a FLASH chip, and the FPGA firmware includes a functional firmware for configuring the FPGA chip, characterized in that: The FPGA firmware encryption method comprises the following steps: When the functional firmware is running, it first searches for the encryption completion flag of the designated address bit of the FLASH chip; If the encryption completion flag can be found, continue to compare whether the first encrypted data generated by the functional firmware is the same as the second encrypted data stored in the designated address position of the FLASH chip; if the first encrypted data is the same as the second encrypted data, the functional firmware operates normally; if the first encrypted data is different from the second encrypted data, the functional firmware exits operation; wherein, the first encrypted data and the second encrypted data are generated based on two source data using the same encryption algorithm, and the two source data include at least one of the following groups: FPGA chip unique ID and a fixed number; or, FLASH chip unique ID and a fixed number; If the encryption completion flag cannot be found, continue with the following steps: the functional firmware jumps to the address of the encryption firmware stored on the FLASH chip through the multi-image update module of the FPGA chip; if the encryption firmware exists, the encryption completion flag and the second encrypted data are generated, and the second encrypted data is stored in the specified address bit corresponding to the encryption completion flag of the FLASH chip, and the functional firmware re-runs to find the encryption completion flag at the specified address bit of the FLASH chip, erases the encryption firmware stored on the FLASH chip, and the encryption firmware jumps to the address of the functional firmware stored on the FLASH chip through the multi-image update module of the FPGA chip; if the encryption firmware does not exist, the functional firmware exits and outputs a prompt that loading the encryption firmware failed.

2. The FPGA firmware encryption method according to claim 1, characterized in that: The FPGA firmware is stored on the FLASH chip, including the following steps: Generate a firmware file by using the functional firmware and the encryption firmware, wherein the functional firmware is stored at the FLASH 0-bit address of the firmware file, and the encryption firmware is stored at the FLASH high-bit address of the firmware file; Burn the firmware file into the FLASH chip.

3. The FPGA firmware encryption method according to claim 2, characterized in that: The FLASH high-order address where the encryption firmware is stored in the firmware file is consistent with the address of the encryption firmware stored in the functional firmware.

4. The FPGA firmware encryption method according to claim 1, characterized in that: The encryption algorithm includes but is not limited to AES, DES, and a custom algorithm.

5. An FPGA firmware encryption device, characterized in that: The device comprises at least one processor; and a memory storing instructions, which, when executed by the at least one processor, implement the steps of the method according to any one of claims 1 to 4.

Images