Semiconductor memory device and memory system

Abstract

A semiconductor storage device and a memory system capable of suppressing peak current are provided. The semiconductor storage device of an embodiment includes a first pad, a clock generation circuit that generates a first clock, an output circuit that outputs the first clock from the first pad, a designation circuit that designates one of a plurality of time slots generated based on the first clock as a specific time slot, and a peak control circuit that causes a portion that generates a current peak to act at a timing corresponding to the specific time slot when instructed to act.

Description

[0001] [Related Application]

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-057039 (filed on March 30, 2022). This application incorporates the entire contents of this base application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices and memory systems. Background Technology

[0004] In recent years, NAND flash memory, as a semiconductor storage device, has become increasingly popular.

[0005] Such semiconductor memory devices require the suppression of peak current. Summary of the Invention

[0006] This embodiment provides a semiconductor memory device and a memory system capable of suppressing peak current.

[0007] The semiconductor memory device of the embodiment includes: a first pad; a clock generation circuit for generating a first clock; an output circuit for outputting the first clock from the first pad; a designation circuit for designating one of a plurality of time slots generated based on the first clock as a specific time slot; and a peak control circuit for, when instructed to act, causing the execution of a portion of the action that generates a current peak to be performed at a timing corresponding to the specific time slot. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a structural example of a memory system according to an implementation method.

[0009] Figure 2 This is a schematic cross-sectional view illustrating an example of the structure of a memory device in which memory chips 2 are stacked.

[0010] Figure 3 This is a block diagram illustrating a structural example of a memory system with multiple packages.

[0011] Figure 4 This is an explanatory diagram illustrating a structural example of an encapsulation.

[0012] Figure 5 This is a block diagram illustrating a structural example of the non-volatile memory in this embodiment.

[0013] Figure 6 This is a circuit diagram showing a part of the structure of the input / output circuit 22.

[0014] Figure 7 This is a circuit diagram showing a part of the structure of logic control circuit 21.

[0015] Figure 8 This is an explanatory diagram used to illustrate the generation of the peak enable signal.

[0016] Figure 9 This is an explanatory diagram used to illustrate the generation of the peak enable signal.

[0017] Figure 10 This is an explanatory diagram used to illustrate peak motion control.

[0018] Figure 11 This is an explanatory diagram used to illustrate the current generated during peak operation.

[0019] Figure 12 This is an explanatory diagram used to illustrate the current generated during peak operation.

[0020] Figure 13 This is an explanatory diagram used to illustrate peak action control in a specific memory chip 2.

[0021] Figure 14 These are explanatory diagrams illustrating other embodiments of the present invention.

[0022] Figure 15 It is a timing diagram representing the SetFeature sequence.

[0023] Figure 16 It is a timing diagram representing the SetFeature sequence. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] (First Implementation)

[0026] In this embodiment, in a multi-chip semiconductor memory device, a specific chip is used as a reader and other chips are used as followers. The operation of each chip can be controlled by the clock generated by the reader, thereby suppressing peak current.

[0027] (Structure of a memory system)

[0028] Figure 1 This is a block diagram illustrating a structural example of a memory system according to an embodiment. The memory system of this embodiment includes a memory controller 1 and one or more NAND-type non-volatile memories. Figure 1An example with four NAND-type non-volatile memory modules 2A to 2D is shown. Hereinafter, without distinguishing between the four NAND-type non-volatile memory modules 2A to 2D, they will be representatively referred to as NAND-type non-volatile memory 2. Furthermore, NAND-type non-volatile memory will be simply referred to as non-volatile memory. The memory system can be connected to a host device (not shown). The host device is, for example, a personal computer, a mobile terminal, or other electronic device. Each non-volatile memory 2 is chip-based. In the following description, the non-volatile memory 2 will also be referred to as memory chip 2. Such memory chips 2 are sometimes stacked within a memory device.

[0029] Figure 2 This is a schematic cross-sectional view illustrating an example of the structure of a memory device in which memory chips 2 are stacked. Figure 2 Showing n memory chips 21, 22, ..., 2 n An example of stacking on wiring substrate 7. In cases where it is not necessary to distinguish between n memory chips 21, 22, ..., 2... n In this case, it is called memory chip 2. Memory device 5 achieves high storage density and large storage capacity through multiple memory chips 2.

[0030] To reduce the package size (area), multiple memory chips 2 are stacked on a substrate. The stacked memory chips 2 are interconnected using bonding wires 6 or through electrodes.

[0031] For example, such as Figure 2 As shown, the upper memory chip 2 is connected via bonding line 6. n With the underlying memory chip 2 n-1 When connected, the upper-layer storage chip 2 n Compared to the lower-level memory chip 2 n-1 They are stacked at staggered intervals. Thus, the memory chip 2 is located in the lower layer. n-1 The pad 4A is not connected to the upper memory chip 2 n Covered yet exposed.

[0032] For example, the pads 4A of each memory chip 2 are connected to a common bonding line 6 and to the terminals 5 of the wiring substrate 7. In this way, multiple memory chips 2 share the wiring for the input and output of each signal. Therefore, multiple memory chips 2 cannot drive the data lines individually. Thus, among the multiple non-volatile memories (and controllers) sharing the data lines, only one chip is capable of outputting data.

[0033] (Peak current)

[0034] In Adoption Figure 2In such a multi-chip architecture, the timing of the cell operations of multiple memory chips 2 is sometimes synchronized. In this case, current peaks may occur simultaneously in each memory chip 2 along with the cell operations, resulting in a peak current exceeding expectations as a whole. Therefore, TDPPM (Time Division Peak Power Management) is sometimes used to manage the period during which each memory chip 2 can generate a current peak.

[0035] However, this management method requires all memory chips 2 to be supplied with a common clock to manage cell operation. Previously, in TDPPM, a common clock was supplied to all memory chips 2 from the controller. Therefore, this resulted in drawbacks such as the creation of terminals for clock supply, increased wiring, and increased load on the controller.

[0036] Therefore, a method was also considered to manage the peak current generation period using an internal clock generated within each memory chip 2. However, in this case, it is necessary to synchronize the internal clocks during each specified period, and reliable peak current management is not possible during long-term operation.

[0037] (Reader and Follower)

[0038] Therefore, in this embodiment, a specific memory chip (hereinafter also referred to as a reader) among all memory chips 2 generates a clock, and the clock generated by the reader is supplied to all other memory chips (hereinafter also referred to as followers) through a terminal that is connected to all memory chips 2, thereby enabling TDPPM to stably manage the peak current generation period.

[0039] exist Figure 1 In this context, non-volatile memory (memory chip) 2 is a semiconductor storage device that stores data non-volatilely. For example... Figure 1 As shown, the memory controller 1 is connected to each non-volatile memory 2 via a NAND bus. The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0040] The host interface 13 outputs requests received from the host, write data as user data, etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0041] The memory interface 15 controls, based on instructions from the processor 12, the processes of writing user data to and reading from the non-volatile memory 2.

[0042] Processor 12 provides unified control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, based on a request from the host, processor 12 instructs memory interface 15 to write user data and parity data to non-volatile memory 2. Additionally, based on a request from the host, processor 12 instructs memory interface 15 to read user data and parity data from non-volatile memory 2.

[0043] The processor 12 determines the storage area (hereinafter referred to as storage area) on the non-volatile memory 2 for the user data stored in RAM 11. The user data is stored in RAM 11 via the internal bus 16. The processor 12 determines the storage area for page data, which is written in units of pages. In this specification, the user data stored in one page of the non-volatile memory 2 is defined as unit data. The unit data is encoded and stored as codewords in the non-volatile memory 2, for example.

[0044] Furthermore, encoding is not mandatory. Memory controller 1 can also save the cell data to non-volatile memory 2 without encoding, but... Figure 1 The diagram illustrates an encoding structure as an example. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Furthermore, a codeword can be generated based on a single cell data entry, or it can be generated based on segmented data obtained by dividing the cell data. Alternatively, a codeword can be generated using multiple cell data entries.

[0045] Processor 12 determines the storage region of non-volatile memory 2 as the destination for each unit of data. It allocates physical addresses to the storage regions of non-volatile memory 2. Processor 12 manages the storage regions as the destination for the unit data using these physical addresses. Processor 12 specifies the physical address of the determined storage region and instructs memory interface 15 to write user data into non-volatile memory 2. Processor 12 manages the mapping between logical addresses (logical addresses managed by the host) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 determines the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 15 to read the user data.

[0046] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes codewords read from non-volatile memory 2.

[0047] RAM11 temporarily stores user data received from the host until it is stored in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 until it is sent to the host. RAM11 is, for example, general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0048] exist Figure 1 The diagram shows a structural example of a memory controller 1 comprising an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 may be integrated into the non-volatile memory 2.

[0049] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and provides the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0050] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 provides the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0051] The processor 12 of the memory controller 1 controls the memory interface 15 to send signals DQ<7:0> and data strobe signals DQS and / DQS to the non-volatile memory 2. The signals DQ<7:0> sent from the memory controller 1 to the non-volatile memory 2 contain instructions, addresses, and data. This data includes set feature data (SetFeature) indicating the various operating modes of the non-volatile memory 2, and write data that will be the target of write operations to the memory cell array 23 (described later). The data strobe signals DQS and / DQS are synchronization control signals that indicate read and write timings generated synchronously with data transfer.

[0052] Processor 12 controls memory interface 15, sending chip enable signal / CE, signal CLE, signal ALE, signal / WE, read enable signal RE, and / RE to non-volatile memory 2. Signal / CE is used to activate each non-volatile memory 2. The write enable signal / WE allows writing; non-volatile memory 2 uses this signal / WE to fetch instructions and addresses. That is, signal / WE can also be called the fetch signal. The instruction latch enable signal allows instruction latching, and the address latch enable signal ALE allows address latching.

[0053] Signals marked with a " / " at the beginning indicate valid / low level or NOT logic. That is, signals without a " / " at the beginning are valid at the "H" level, while signals marked with a " / " at the beginning are valid at the "L" level.

[0054] On the other hand, the non-volatile memory 2 receives various signals from the memory controller 1 through the input / output circuit 22 described later, and sends the signals DQ<7:0> and data strobe signals DQS and / DQS to the memory controller 1. Additionally, the non-volatile memory 2 sends the signal R / B to the memory controller 1. The ready / busy signal R / B indicates whether the device is in a ready state (able to accept instructions from external sources) or a busy state (unable to accept instructions from external sources).

[0055] In addition, the memory controller 1 can output a write protection signal / WP, but in this embodiment, the terminals (pads) / WP used in the transmission of the write protection signal / WP are connected to each other in each memory chip 2, so the write protection signal / WP is not received in each memory chip 2.

[0056] The four memory chips are sometimes packaged together. Figure 1One example is using a memory controller 1 to control four memory chips 2 contained in a package. Alternatively, sometimes a single memory controller 1 can control memory chips 2 contained in multiple packages.

[0057] Figure 3 This is a block diagram illustrating an example of this situation. Additionally, Figure 4 This is an explanatory diagram illustrating a structural example of an encapsulation.

[0058] like Figure 3 As shown, the memory controller 1 is connected to each package P0 to PN-1 (hereinafter referred to as package P if there is no need to distinguish these packages) via a NAND bus. All signals except the write protection signal / WP are transmitted between the memory controller 1 and each memory chip 2 within package P. Furthermore, wiring is provided between the memory controller 1 and each package P to supply the chip enable signal / CE. A power supply voltage is supplied to each package P from a predetermined power source.

[0059] In this embodiment, the terminal / WP for receiving the write protection signal / WP is used, as described above, for connecting the memory chips 2 within each package P to each other.

[0060] like Figure 4 As shown, each package P has multiple memory chips 2 (i.e., 0-3). Additionally, in Figure 4 The example shown depicts a package P consisting of four memory chips 2, but the number of memory chips 2 contained in package P is not limited. For example... Figure 4 As shown, all signals except the write protection signal / WP, as well as the various power supply wirings, are shared by the memory chips 2 within package P. That is, within package P, the group of lines supplying the shared signals ALE, CLE, DQ, DQS, / DQS, / WE, / RE, RE, etc., is also referred to as a channel. Figure 4 In the example, a channel is formed by a package P. Figure 4 In the example, only one chip enable signal / CE is supplied within package P, but there are also cases where a package P has a group driven by multiple chip enable signals / CE.

[0061] To select each memory chip 2 in a group driven by a chip enable signal / CE, the chip address is used. Figure 4 In this example, four memory chips are selected based on the chip enable signal / CE, so memory chip 2 can be identified using a 2-bit chip address. Furthermore, the memory chip 2 identified by the chip address is called a LUN. Figure 4 The example represents an instance where there are four LUNs, LUN0 to LUN3, in a package P.

[0062] (Structure of non-volatile memory)

[0063] Figure 5 This is a block diagram illustrating a structural example of the non-volatile memory of this embodiment. The non-volatile memory (memory chip) 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, an address register 26a, an instruction register 26b, a control circuit 27, a voltage generation circuit 28, an R / B signal generation circuit 30, an input / output pad group 32, and a logic control pad group 33.

[0064] The memory cell array 23 has multiple blocks (memory blocks). Each of the multiple blocks BLK has multiple memory cell transistors (memory cells). In order to control the voltage applied to the memory cell transistors, the memory cell array 23 is equipped with multiple bit lines, multiple word lines, and source lines.

[0065] The input / output pad group 32 is equipped with multiple terminals (pads) corresponding to the signals DQ<7:0 and the data strobe signals DQS and / DQS in order to transmit and receive various signals containing data with the memory controller 1.

[0066] The logic control pad group 33 has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal, address latch enable signal ALE, write enable signal / WE, and read enable signals RE and / RE in order to transmit and receive various signals with the memory controller 1.

[0067] In this embodiment, the terminal (pad) / WP corresponding to the write protection signal / WP is used for transmitting the clock CK between the reader and the follower.

[0068] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via the NAND bus. The logic control circuit 21 receives external control signals (such as chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, and read enable signals RE and / RE) from the memory controller 1 via the NAND bus. In addition, the R / B signal generation circuit 30 sends a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0069] Address register 26a holds the address. Instruction register 26b holds the instruction. Address registers 26a and 26b are, for example, constructed from SRAM.

[0070] The non-volatile memory 2 is supplied with various operating power supplies, including power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss, from an external source. The power supply voltage Vcc is a circuit power supply voltage typically provided externally as the operating power supply, for example, around 2.5V. The power supply voltage VccQ is, for example, 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a power supply voltage higher than Vcc, for example, 12V.

[0071] The control circuit 27 receives instructions from the instruction register 26b and controls the various parts of the non-volatile memory 2 according to the sequence of instructions.

[0072] The voltage generation circuit 28 is controlled by the control circuit 27. It receives a power supply voltage from the outside of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0073] The row decoder 25 receives the row address from register 26a and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Furthermore, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0074] The sense amplifier unit group 24A of sense amplifier 24 receives the column address from register 26a and decodes the column address. Based on the decoded column address, sense amplifier unit group 24A selects any bit line. Furthermore, during data readout, sense amplifier unit group 24A detects and amplifies the data read from the memory cell transistor to the bit line. Additionally, during data writeout, sense amplifier unit group 24A transmits the write data to the bit line.

[0075] The sense amplifier 24 has a data register 24B. During data reading, the data register 24B holds the data detected by the sense amplifier unit group 24A and serially transmits it to the input / output circuit 22. Conversely, during data writing, the data register 24B holds the data serially transmitted from the input / output circuit 22 and transmits it to the sense amplifier unit group 24A. The data register 24B is constructed from SRAM or the like.

[0076] The input / output circuit 22 is controlled by the logic control circuit 21, and transmits and receives signals DQ (e.g., DQ0 to DQ7) and signals DQS and / DQS via the NAND bus with the memory controller 1.

[0077] Figure 6This is a circuit diagram showing a portion of the structure of the input / output circuit 22. For example... Figure 6 As shown, the input / output circuit 22 has an input receiver 22a and an output driver 22b for each terminal of the input / output pad group 32. The input receiver 22a receives signals input through each terminal, and the output driver 22b sends signals output through each terminal.

[0078] The input / output circuit 22 is configured to receive signal DQ as data synchronously with signals DQS and / DQS when signal DQ is supplied along with signals DQS and / DQS. Furthermore, corresponding to the signal RE provided to the logic control circuit 21, the input / output circuit 22 sends data read from the memory cell array 23 as signal DQ along with signals DQS and / DQS to the memory controller 1.

[0079] The input / output circuit 22 is controlled by the logic control circuit 21, enabling signal transmission corresponding to the signal / WE and signals DQS and / DQS. The input / output circuit 22, controlled by the logic control circuit 21, outputs the received signals to the address register 26a or the instruction register 26b.

[0080] The logic control circuit 21 determines, based on the address Cadd, whether the signal transfer between itself and the non-volatile memory 2 is specified by the memory controller 1. The logic control circuit 21 controls the input / output circuit 22 in accordance with the corresponding signal, enabling it to output the instruction received as the signal DQ to the instruction register 26b. The logic control circuit 21 also controls the input / output circuit 22 in accordance with the signal ALE, enabling it to output the address received as the signal DQ to the address register 26a. Synchronously with the signal / WE, the logic control circuit 21 outputs the signals received by the input / output circuit 22 to each part, thus enabling writing.

[0081] When an instruction is provided from instruction register 26b, control circuit 27 parses the instruction and controls logic control circuit 21 based on the parsing result.

[0082] (Peak motion control)

[0083] In this embodiment, when a peak control start command is input, the control circuit 27 performs peak management based on TDPPM.

[0084] The memory cell array 23 includes a region (hereinafter referred to as the ROM region) for storing system information used to set system actions. In this embodiment, the ROM region also stores peak management information for TDPPM. TDPPM defines time slots synchronized with the clock CK (hereinafter simply referred to as time slots), and time slots whose numbers (hereinafter referred to as time slot numbers) cycle once at a predetermined number of time slots (hereinafter referred to as the total number of time slots). Peak current management (peak action control) is performed by determining the time slots that can generate peak current for each memory chip 2.

[0085] The peak management information stored in the ROM area includes information on the frequency division period for setting the clock frequency used in TDPPM control, information on the total number of time slots representing one cycle of the time slot numbering, information on the time slot allocation numbers assigned to time slots that can generate current peaks, and reader / follower information indicating whether it is a reader or a follower. Furthermore, the time slot allocation number information and the reader / follower information are set for each memory chip 2.

[0086] System information, including peak management information, is read through a boot-up read performed immediately after the memory system or memory chip 2 is started. Memory chip 2 uses the system information and peak management information read from the ROM area through the boot-up read to control the write and read operations of user data.

[0087] The control circuit 27 includes a peak control circuit 27a and a ROM register 27b. The ROM register 27b holds system information and peak management information read during power-on readout. The peak control circuit 27a controls the timing of the peak occurrence of the current flowing within the memory chip 2. That is, the peak control circuit 27a retains peak operation until a peak enable signal is received that allows the execution of a partial operation (hereinafter referred to as peak operation) involving the current peak in the operation of the memory chip 2. For example, in a read operation, a channel clearing operation is a partial operation (peak operation) that is subject to current peak control. The peak control circuit 27a performs control (peak operation control) for peak operations such as channel clearing operation, waiting for the input of the peak enable signal and executing it, thereby preventing the peak current from increasing beyond what is intended. Furthermore, the peak control circuit 27a can also execute the peak operation at a timing corresponding to the timing when the peak enable signal is input by appropriate timing adjustment.

[0088] In order to generate a peak enable signal, the control circuit 27 outputs the peak management information stored in the ROM register 27b to the logic control circuit 21.

[0089] (Structure of logic control circuits related to peak motion control)

[0090] Figure 7 This is a circuit diagram showing a portion of the structure of the logic control circuit 21. The logic control circuit 21 has an input receiver 21a for each terminal of the logic control pad group 33. The input receiver 21a receives signals input via each terminal. Additionally, the logic control circuit 21 has an output driver 21b corresponding to a terminal / WP in the logic control pad group 33. The input receiver 21a receives signals input via each terminal. Furthermore, as described later, the input receiver 21a corresponding to the terminal / WP receives a clock CK transmitted from the terminal / WP of another memory chip 2, and the output driver 21b transmits the clock CK provided to the other memory chip 2 via the terminal / WP.

[0091] like Figure 5 As shown, the logic control circuit 21, in addition to the circuit section for controlling the input / output circuit 22, also includes a control unit 41, a clock (CLK) oscillator 42, a frequency divider 43, an output circuit 44, an input circuit 45, a multiplexer 46, and a peak operation enable circuit 47. Furthermore, the input circuit 45 is equivalent to... Figure 7 The input receiver 21a and the output circuit 44 are equivalent to Figure 7 The output driver 21b. The control unit 41 controls the entire control logic control circuit 21. The control unit 41 may also be composed of a processor using a CPU, FPGA (Field Programmable Gate Array), etc. The control unit 41 can control each part according to a program stored in a memory (not shown), or it can implement part or all of the functions through hardware electronic circuits. The control unit 41 controls each part based on peak management information.

[0092] Clock oscillator 42 generates a clock at a specified frequency and outputs it to frequency divider 43. Frequency divider 43, through control unit 41, specifies the division number based on the division period information in peak management information, and divides the output clock of clock oscillator 42 to generate clock CK. Frequency divider 43 outputs the divided clock CK to output circuit 44 and multiplexer 46. Clock oscillator 42 and frequency divider 43 constitute clock generation circuit.

[0093] Output circuit 44, controlled by control unit 41, outputs the clock CK from frequency divider 43 to terminal / WP. Additionally, input circuit 45, controlled by control unit 41, receives the clock CK input via terminal / WP. Input circuit 45 outputs the received clock CK to multiplexer 46.

[0094] The multiplexer 46 is controlled by the control unit 41, which selects either the clock CK from the frequency divider 43 or the clock CK received by the input circuit 45 and outputs it to the peak operation enable circuit 47.

[0095] In this embodiment, the control unit 41 determines whether a memory chip is designated as a reader or a follower based on the reader / follower information stored in the peak management information in the ROM register 27b. For memory chips designated as readers, the control unit 41 activates the clock oscillator 42, the frequency divider 43, the output circuit 44, the multiplexer 46, and the peak operation enable circuit 47. For memory chips designated as followers, the control unit 41 activates the input circuit 45, the multiplexer 46, and the peak operation enable circuit 47.

[0096] That is, in the logic control circuit 21 of the memory chip designated as a reader, the clock CK is output via the output circuit 44 to each memory chip 2 connected to the terminal / WP. Additionally, in the logic control circuit 21 of the memory chip designated as a follower, the input circuit 45 receives the clock CK output from other memory chips 2 via the terminal / WP. The control unit 41 of the memory chip designated as a reader causes the multiplexer 46 to select the clock CK output from the frequency divider 43 and provide it to the peak operation enable circuit 47; the control unit 41 of the memory chip designated as a follower causes the multiplexer 46 to select the clock CK output from the frequency divider 43 and provide it to the peak operation enable circuit 47.

[0097] In this embodiment, the peak operation enable circuit 47, which serves as the designated circuit, is controlled by the control unit 41 to generate a peak enable signal for controlling the timing of peak current generation. For example, the peak operation enable circuit 47 may also be configured as a shift register. While resetting the count value based on the total number of time slots, the peak operation enable circuit 47 counts the clock CK input via the multiplexer 46 to identify the current time slot number. The peak operation enable circuit 47 is assigned a time slot allocation number from the control unit 41 and generates the peak enable signal synchronously with the timing of the current time slot number reaching the time slot allocation number. The peak operation enable circuit 47 outputs the generated peak enable signal to the peak control circuit 27a.

[0098] Figure 8 and Figure 9 This is an explanatory diagram used to illustrate the generation of the peak enable signal.

[0099] Figure 8 An example is one where the total number of time slots is 4, and the time slot allocation number is set to 0 in a specific memory chip 2. Additionally, Figure 9 An example is one where the total number of time slots is 8, and the time slot allocation number is set to 2 in a specific memory chip 2.

[0100] As described above, the peak operation allowance circuit 47 obtains the current time slot number by counting the clock CK while resetting the count value according to the total number of time slots. That is, in Figure 8 In the example, the time slot numbers are obtained as 0, 1, 2, 3, 0, 1, ... The peak action enable circuit 47 generates a peak enable signal at the timing when the current time slot number reaches the time slot allocation number. Figure 8 In the example, the time slot allocation number is 0, so whenever the count value becomes 0, a peak enable signal that becomes the H level is obtained.

[0101] In addition, Figure 9 In the example, as time slot numbers, we get 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, ... . In Figure 9 In the example, the time slot allocation number is 2, so whenever the count value becomes 2, a peak enable signal that becomes H level is obtained.

[0102] (action)

[0103] Next, refer to Figures 10 to 13 The operation of this implementation method will be explained. Figure 10 This is an explanatory diagram used to illustrate peak motion control. Figure 11 and Figure 12 This is an explanatory diagram used to illustrate the current generated during peak operation. Figure 13 This is an explanatory diagram used to illustrate peak action control in a specific memory chip 2.

[0104] Figure 10 The horizontal axis represents time, indicating the number of instructions from memory controller 1 and N+1 memory chips 2 (in...). Figure 10 The middle part refers to the peak operation period of the peak operation control for each of the memory chips (Die0 to DieN). Additionally, Figure 10 In the example, the peak management information stored in the ROM region of the memory cell array 23 is set to include the frequency division period, the total number of time slots is N, the time slot allocation number of each of the memory chips Die0 to DieN, and information indicating that memory chip Die0 is a reader and the other memory chips Die1 to DieN are followers.

[0105] After power is turned on, each memory chip (Die0 to DieN) receives the power-on read instruction FFh sent from the memory controller 1. The power-on read instruction FFh is not accompanied by a chip address Cadd. That is, if each memory chip (Die0 to DieN) receives the instruction FFh, it performs the power-on read operation regardless of its chip address. If each memory chip (Die0 to DieN) receives the instruction FFh, it reads system information and peak management information from the ROM area of ​​each memory cell array 23 and stores them in the ROM register 27b of the control circuit 27. Instructions like the power-on read instruction FFh that are not accompanied by a chip address Cadd are called broadcast instructions. In contrast, instructions accompanied by a chip address Cadd are called individual instructions.

[0106] exist Figure 10 In this example, a power-on read (POR) is used to set memory chip Die0 as the reader and 0 as the time slot allocation number. Additionally, memory chips Die1 through DieN are set as followers, with time slot allocation numbers set to 1 through N respectively. Furthermore, information about the clock cycle and the total number of time slots is also set in memory chips Die0 through DieN.

[0107] The control circuits 27 of each memory chip Die0 to DieN wait to receive the peak control start instruction XXh sent from the memory controller 1. This peak control start instruction XXh is not accompanied by a chip address Cadd. That is, if each memory chip Die0 to DieN receives the instruction XXh, peak control begins regardless of the chip address of each memory chip Die0 to DieN. In this embodiment, each memory chip 2 begins peak operation control by receiving the peak control start instruction. That is, the peak control start instruction XXh is a broadcast instruction, which is sent from the memory controller 1 when peak operation control is required. Conversely, when peak operation control is not required, by retaining the transmission of the peak control start instruction from the memory controller 1, peak operation control can be prevented. Furthermore, if the start of peak operation control based on the peak control start instruction is not required, peak operation control can also begin after a predetermined time has elapsed since the start of power-on reading. When each of the control circuits 27 from Die0 to DieN receives a peak control start command, it provides peak management information to the control unit 41 of the logic control circuit 21, thereby starting peak action control.

[0108] The control unit 41 of the memory chip Die0, designated as the reader, activates the clock oscillator 42, frequency divider 43, output circuit 44, multiplexer 46, and peak operation enable circuit 47. The clock oscillator 42 generates a clock signal, and the frequency divider 43 divides the oscillation clock of the clock oscillator 42 by a division number specified by the division period, outputting clock CK. Figure 10 As shown, output circuit 44 outputs clock CK via terminal / WP. Terminals / WP of memory chips Die0 to DieN are connected to each other, and clock CK from memory chip Die0, which acts as a reader, is provided to terminals / WP of memory chips Die1 to DieN, which act as followers. Multiplexer 46 of memory chip Die0, which acts as a reader, outputs clock CK from frequency divider 43 to peak operation enable circuit 47.

[0109] The controller 41 of the memory chips Die1 to DieN, configured as followers, activates the frequency divider 43, the multiplexer 46, and the peak operation enable circuit 47. In the memory chips Die1 to DieN, the input circuit 45 receives the clock CK input via terminal / WP and provides it to the multiplexer 46. The multiplexer 46 of the memory chips Die1 to DieN outputs the clock CK received by the input circuit 45 to the peak operation enable circuit 47.

[0110] Thus, a common clock CK is input to the peak operation enable circuits 47 of each memory chip Die0 to DieN. The peak operation enable circuit 47 counts the clock CK while resetting the count value according to the total number of time slots. Therefore, as... Figure 10 As shown, time slots 0 to N are set synchronously with clock CK. The peak operation enable circuit 47 generates a peak enable signal when the time slot number matches the time slot allocation number.

[0111] Figure 10 The slashed portion indicates the period during which the peak enable signal becomes active. Each Die0 to DieN peak operation enable circuit 47 generates a peak enable signal at the timing corresponding to the time slots numbered 0, 1, 2, ... N, and provides it to the peak control circuit 27a. Thus, each Die0 to DieN peak control circuit 27a performs peak operation control to generate peak current during the time slot period corresponding to its assigned time slot number.

[0112] Figure 11 and Figure 12 This is an example of the voltage variation of each wiring that makes up the memory cell array 23. Figure 11 This indicates the generation of peak current as a result of voltage changes during programming operations. Figure 12 This indicates the generation of peak current as a result of voltage changes during the readout process.

[0113] The memory cell array 23 is equipped with word lines WL, bit lines BL, select gate lines SGD, SGS, and other wiring. Figure 11 This indicates the voltage changes of these wirings during the programming operation. Specifically, for the block BLK to be written (select block BLK), a channel precharge period is set at times t11 to t12 before the application of the programming voltage Vpgm, during which the select gate line SGD is set to, for example, 5V. After the channel precharge period ends, a relatively high voltage Vpass is applied to the unselected word line (non-select WL), and subsequently a high voltage Vpgm is applied to the word line to be written (select WL). In this programming operation, current peaks are generated at the beginning of the channel precharge period, corresponding to the start of the application of voltage Vpass and voltage Vpgm.

[0114] like Figure 12 As shown, during the readout operation (verification operation), an interference prevention period (USTRDIS period) is set between times t21 and t22. During this period, a readout voltage Vr is applied to the select word line WL (hereinafter also referred to as WL_sel) of the select block. After the interference prevention period ends, a readout period is set (after time t22). During the readout period, a voltage VSG (e.g., 5V) is applied to the select gate lines SGD_sel, SGD_usel, and SGS of the select block. Additionally, a sufficiently high voltage VREAD (e.g., 8V) is applied to the select word line WL_sel and the non-select word line WL_usel of the select block. In this readout operation, a current peak is generated at the beginning of the interference prevention period, corresponding to the start of the application of voltage Vpass, and another current peak is generated at a certain timing during the readout period.

[0115] In this embodiment, the peak operation that generates the current peak is performed using time slots assigned to the time slot numbers of the memory chips Die0 to DieN, respectively. Figure 13 This indicates the period of peak operation during programming of a specific memory chip 2. Figure 13 In the example, in a specific memory chip 2, a peak action is performed in time slot number 0.

[0116] exist Figure 13The example shown illustrates a memory chip 2 assigned time slot number 0. The peak control circuit 27a of this memory chip 2 begins channel pre-charging during time slot number 0. This results in a current peak during time slot number 0. The memory chip 2 does not perform peak operation thereafter until time slot number 0. Therefore, for example, even if the channel pre-charging period ends during time slot number 2, programming operation is retained until the next time slot number 0 is reached. If time slot number 0 is reached, programming operation for peak operation restarts.

[0117] Each memory chip 2 performs peak operation in different time slots, and the timing of the current peaks is staggered, so the memory system as a whole can suppress peak current.

[0118] Thus, in this embodiment, in a multi-chip semiconductor memory device, a specific chip is used as a reader, and other chips are used as followers. Peak operation control is implemented for each chip using a clock generated by the reader, thereby suppressing peak current. Furthermore, peak management information for peak operation control is pre-stored in the memory cell array, eliminating the need to supply peak management information from the memory controller 1 to the memory chip 2. Additionally, peak operation control can be initiated via a peak control start command and implemented when necessary.

[0119] Furthermore, the above description illustrates an example of transmitting the clock CK for peak operation control by interconnecting the terminals / WP of each memory chip 2. However, the clock CK can also be transmitted using other terminals of the memory chip 2. For example, the terminal that transmits the ready / busy signal R / B can also be used to transmit the clock CK.

[0120] (Second Implementation)

[0121] Figure 14 These are explanatory diagrams illustrating other embodiments of the present invention. The hardware structure of this embodiment is the same as that of the first embodiment. Furthermore, Figure 15 and Figure 16 It is a timing diagram representing the SetFeature sequence. Figure 15 Represents the overall SetFeature sequence. Figure 16 This represents an individual SetFeature sequence.

[0122] In the first embodiment, an example was described in which peak management information was pre-stored in the memory cell array 23. In contrast, in this embodiment, peak management information is set in each memory chip 2 according to instructions from the memory controller 1. Figure 14In the diagram, the horizontal axis represents time and shows instructions from memory controller 1 and N+1 memory chips 2 (in...). Figure 14 The peak operation period is the peak operation period for each of the memory chips Die0 to DieN.

[0123] After power is turned on, the processor 12 of the memory controller 1 sends a power-on read instruction FFh to all memory chips Die0 to DieN. Upon receiving the instruction FFh, each memory chip Die0 to DieN reads system information from the ROM region of its respective memory cell array 23 and stores it in the ROM register 27b of the control circuit 27. During this stage, peak management information is not stored in the ROM register 27b of memory chips Die0 to DieN. Next, the processor 12 of the memory controller 1 generates a SetFeature instruction EFh for all memory chips Die0 to DieN and sends common peak management information to all memory chips Die0 to DieN. The set feature instruction EFh is not accompanied by a chip address Cadd, therefore it is a broadcast instruction.

[0124] Figure 15 The SetFeature sequence in this case is shown. At the beginning of the SetFeature sequence, the processor 12 of the memory controller 1 enables the CLE signal, generates the SetFeature instruction EFh, and enables the / WE signal, thereby fetching the SetFeature instruction EFh into memory chips Die0 to DieN. Next, the processor 12 enables the ALE signal, generates the feature address Fadd, and thereby fetches the feature address Fadd into memory chips Die0 to DieN.

[0125] Next, processor 12 enables signal DQS multiple times, transmitting SetFeature data D0 to D3 (feature data Fdata). Thus, SetFeature data D0 to D3 are fetched into memory chips Die0 to DieN. Through SetFeature data D0 to D3, the clock cycle and total number of time slots information in the peak management information are transmitted to memory chips Die0 to DieN and stored in ROM register 27b.

[0126] Next, the processor 12 of the memory controller 1 transmits peak management information individually to each memory chip Die0 to DieN. In this case, the processor 12 follows... Figure 16The processor 12 sequentially transmits peak management information to each memory chip (Die0 to DieN) according to the timing sequence. In this case, the transmitted peak management information includes reader / follower information and time slot allocation numbers. The processor 12 generates individual SetFeature instructions D5h to activate the / WE signal. Then, the processor 12 activates the ALE signal, continuously generating chip addresses Cadd and feature addresses Fadd. Next, the processor 12 activates the DQS signal multiple times, transmitting the reader / follower information and time slot allocation numbers as SetFeature data D0 to D3 (feature data Fdata). The set feature instruction D5h is accompanied by the chip address Cadd, therefore it is an individual instruction.

[0127] exist Figure 14 In the example, memory chip Die0 receives information indicating the reader and the time slot allocation number as 0. The control circuit 27 of memory chip Die0 stores the received peak management information in ROM register 27b. Next, memory chips Die1, Die2, ..., DieN sequentially receive reader / follower information and time slot allocation number information. Furthermore, information indicating time slot allocation numbers 1, 2, ..., N is provided to memory chips Die1, Die2, ..., DieN. The control circuit 27 of memory chips Die1, Die2, ..., DieN stores the received information and the time slot allocation number in ROM register 27b. Thus, all peak management information is stored in the ROM registers 27b of memory chips Die0 to DieN.

[0128] In addition, Figure 14 In this context, the SetFeature sequence is represented by D5h-Cadd-Fadd-Fdata, but the omission indicates that the SetFeature sequence applies to memory chips Die1 to DieN. Alternatively, the follower and time slot allocation numbers can be pre-set in all memory chips Die0 to DieN through initial configuration. In this case, only the reader information needs to be provided to one memory chip from Die0 to DieN, allowing the individual SetFeature sequence to be omitted once.

[0129] The processor 12 of the memory controller 1 sends a peak control start command XXh. When the control circuits 27 of each memory chip Die0 to DieN receive the peak control start command XXh sent from the memory controller 1, they provide peak management information to the control unit 41 of the logic control circuit 21 and start peak operation control.

[0130] Furthermore, assuming there are 16 memory chips in the storage system, the instructions that memory controller 1 needs to output are as follows.

[0131] • Power-on read (broadcast command) FFh×1

[0132] • SetFeature (broadcast command) -- Frequency division period × 1

[0133] • SetFeature (broadcast command) -- Total number of time slots × 1

[0134] • SetFeature (Individual Instruction) -- Time slot allocation number × 16

[0135] • SetFeature (Individual Command) -- Reader Information ×1

[0136] • SetFeature (Individual Instruction) -- Follower Information ×15

[0137] • Peak control started (broadcast command) -- ×1

[0138] Other functions and Figure 10 same.

[0139] In this embodiment, the same effects as in the first embodiment can be achieved. Furthermore, since peak management information can be set according to instructions from the memory controller, the degree of freedom in peak motion control can be increased.

[0140] This invention is not limited to the embodiments described above, and various modifications can be made during implementation without departing from its spirit. Furthermore, the invention, which includes various stages in the above embodiments, can be derived through appropriate combinations of the disclosed constituent elements. For example, even if several constituent elements are deleted from all the constituent elements shown in the embodiments, the technical problem described in the "Technical Problem to be Solved by the Invention" column can be solved, and if the effects described in the "Invention Effects" column are obtained, the configuration with the deleted constituent element can be derived as an invention.

[0141] [Explanation of reference numerals in the attached figures]

[0142] 1…Memory controller, 2…Memory chip, 11…RAM, 12…Processor, 13…Host interface, 14…ECC circuit, 15…Memory interface, 16…Internal bus, 21…Logic control circuit, 21a…Input receiver, 21b…Output driver, 22…Input / output circuit, 22a…Input driver, 22b…Output driver, 23…Memory cell array, 24…Sense amplifier, 25…Line decoder, 26a…Address register, 26b…Instruction register, 27…Control circuit, 27a…Peak control circuit, 27b…ROM register, 28…Voltage generation circuit, 30…R / B signal generation circuit, 32…Input / output pad group, 33…Logic control pad group, 41…Control unit, 42…Clock oscillator, 43…Frequency divider, 44…Output circuit, 45…Input circuit, 46…Multiplexer, 47…Peak operation enable circuit.

Claims

1. A semiconductor memory device comprising: First pad; A clock generation circuit includes an oscillator and a frequency divider that divides the output of the oscillator to generate a first clock. The output circuit outputs the first clock from the first pad; The circuit designates one of a plurality of time slots generated based on the first clock as a specific time slot; as well as The peak control circuit, when instructed to act, causes the portion of the action that generates the current peak to be executed at a timing corresponding to the specific time slot. The clock generation circuit, the output circuit, the designation circuit, and the peak control circuit begin to operate upon receiving the first instruction. The output circuit operates when designated as a reader, and does not operate when designated as a follower, regardless of the reception of the first instruction.

2. The semiconductor memory device according to claim 1, The peak control circuit causes the execution of the part of the operation that generates the current peak to standby until the timing corresponding to the specific time slot.

3. The semiconductor memory device according to claim 1, The frequency divider generates a first clock based on the information of the frequency division period. The designated circuit designates the specific time slot based on information about the total number of the plurality of time slots and information about the specific time slot.

4. The semiconductor memory device according to claim 3, It also includes a memory that records at least one of the following: information for specifying the reader or the follower, information for the frequency division period, information for the total number of the plurality of time slots, and information for the specific time slot.

5. The semiconductor memory device according to claim 3, According to a specific transmission format, at least one of the following is received: information specifying the reader or the follower, information about the frequency division period, information about the total number of the plurality of time slots, and information about the specific time slot.

6. The semiconductor memory device according to claim 3, The information about the frequency division period and the total number of the multiple time slots are received as broadcast instructions. Information specifying the reader or the follower, as well as information about the specific time slot, is received as individual instructions.

7. A memory system, comprising: Multiple semiconductor memory devices as described in claim 1; as well as A memory controller that controls the plurality of semiconductor memory devices.

8. The memory system according to claim 7, The memory controller sends at least one of the following to the semiconductor memory device: information about the semiconductor memory device that specifies the reader in the plurality of semiconductor memory devices, information about the division period of the frequency divider, information about the total number of the plurality of time slots, and information about the specific time slot.

9. The memory system according to claim 8, The memory controller transmits information about the frequency division period of the frequency divider and the total number of the multiple time slots via broadcast commands. Information for specifying the reader or follower and information for the specific time slot are sent individually to each of the plurality of semiconductor memory devices.

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