Amplifier, radio frequency chip and electronic device

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device, the amplifier comprises: a field effect tube, the field effect tube comprises a drain, a gate and a source; a drain matching circuit, a first end of the drain matching circuit is connected with the drain of the field effect tube, and a second end thereof is connected with a radio frequency signal output end; a gain equalization circuit, a second end of the gain equalization circuit is connected with the gate of the field effect tube; a gate matching circuit, a first end of the gate matching circuit is connected with a radio frequency signal input end, and a second end thereof is connected with a first end of the gain equalization circuit; a source bias circuit, the source bias circuit is connected with the source of the field effect tube; wherein the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induced magnetic fields. The embodiment of the application can amplify the gain flatness of the amplifier, reduce energy consumption, reduce size and reduce cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, in particular to an amplifier, a radio frequency chip and an electronic device. BACKGROUND

[0002] With the development of communication technology, especially the emergence of 5G technology, high-frequency wireless communication technology has become an important development direction of wireless communication.

[0003] A large number of amplifiers are included in the transceiver system required by high-frequency wireless communication, and the performance of the amplifiers will have an important influence on the performance of the radio frequency transceiver system. Therefore, the high-frequency wireless communication technology puts forward higher requirements on the performance of the amplifiers, such as integration, power consumption, output power, gain flatness, etc. The existing radio frequency or high-frequency amplifier chip is mostly composed of elements such as transistors, lumped parameter elements inductors, lumped parameter elements capacitors, resistors, microstrip lines, etc. Among the elements, inductors, microstrip lines, capacitors, etc. will generate electromagnetic radiation and other induced magnetic fields or electric fields due to signal excitation, which will affect the arrangement and normal work of other elements. In the design or manufacture of the amplifier, in order to solve the electromagnetic compatibility problem between elements, the existing method is to realize electromagnetic compatibility by maintaining a larger arrangement distance between elements, which will result in a larger size of the amplifier, which is not convenient for high-density integration and cost reduction. In addition, electromagnetic radiation, induced magnetic field or electric field will cause energy loss, sacrificing the performance of the amplifier. In order to realize the popularization of high-frequency wireless communication technology, it is urgent to solve the problems of reducing the cost of components and improving the performance of components. SUMMARY

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides an amplifier, a radio frequency chip and an electronic device.

[0005] In a first aspect, the present application provides an amplifier, which comprises:

[0006] a field effect tube, comprising an enhancement mode field effect tube and a depletion mode field effect tube, the field effect tube comprising a drain, a gate and a source, and the field effect tube being used for signal amplification;

[0007] a drain matching circuit, a first end of the drain matching circuit being connected with the drain of the field effect tube, and a second end of the drain matching circuit being connected with a radio frequency signal output end;

[0008] a gain equalization circuit, a second end of the gain equalization circuit being connected with the gate of the field effect tube;

[0009] a gate matching circuit, a first end of the gate matching circuit being connected with a radio frequency signal input end, and a second end of the gate matching circuit being connected with a first end of the gain equalization circuit.

[0010] a source bias circuit connected to a source of the field effect tube;

[0011] The drain matching circuit comprises a first low-coupling inductor pair, and the first low-coupling inductor pair is an inductor pair with opposite induced magnetic fields.

[0012] In the embodiment of the present application, the first low-coupling inductor pair comprises:

[0013] a first inductor, a first end of the first inductor being connected to a drain bias power supply end;

[0014] a second inductor, a first end of the second inductor being connected to a second end of the first inductor, and a second end of the second inductor being connected to a drain of the field effect tube;

[0015] The first inductor and the second inductor are an inductor pair with opposite induced magnetic fields.

[0016] In the embodiment of the present application, the drain matching circuit further comprises:

[0017] a third inductive unit, a first end of the third inductive unit being connected to the second end of the first inductor;

[0018] a second capacitor, a first end of the second capacitor being connected to a second end of the third inductive unit, and a second end of the second capacitor being connected to a radio frequency signal output end;

[0019] a third capacitor, a first end of the third capacitor being connected to the first end of the first inductor, and a second end of the third capacitor being grounded;

[0020] The third inductive unit is one of an inductor, a microstrip line, and a combination of an inductor and a microstrip line.

[0021] In the embodiment of the present application, the gain equalization circuit comprises:

[0022] a first capacitor, a first end of the first capacitor being connected to a first end of the gate matching circuit, and a second end of the first capacitor being connected to a gate of the field effect tube;

[0023] a first unit, a first end of the first unit being connected to the first end of the first capacitor;

[0024] a second unit, a first end of the second unit being connected to a second end of the first unit, and a second end of the second unit being connected to a second end of the first capacitor;

[0025] The first unit is a fourth inductive unit, and the second unit is a first resistor; or the first unit is a first resistor, and the second unit is a fourth inductive unit.

[0026] In the embodiment of the application, the gate matching circuit comprises:

[0027] The first end of the fourth capacitor is connected to the first end of the gate matching circuit and the radio frequency signal input end;

[0028] The first end of the fifth inductive unit is connected to the second end of the fourth capacitor, and the second end of the fifth inductive unit is connected to the first end of the first capacitor as the second end of the gate matching circuit;

[0029] The first end of the sixth inductive unit is connected to the second end of the fifth inductive unit, and the second end of the sixth inductive unit is connected to the third end of the gate matching circuit;

[0030] The fifth inductive unit is one of an inductor, a microstrip line or a combination of an inductor and a microstrip line, and the sixth inductive unit is one of an inductor, a microstrip line or a combination of an inductor and a microstrip line.

[0031] In the embodiment of the application, the fifth inductive unit and the sixth inductive unit are a second low-coupling inductor pair, and the second low-coupling inductor pair is an inductor pair with opposite directions of induced magnetic field.

[0032] In the embodiment of the application, the amplifier further comprises:

[0033] The gate bias circuit is connected to the third end of the gate matching circuit.

[0034] The source bias circuit is connected to the source of the field effect transistor.

[0035] In the embodiment of the application, the gate bias circuit comprises:

[0036] The first end of the fifth capacitor is connected to the ground, the second end of the fifth capacitor is connected to the gate bias power supply end, and the second end of the fifth capacitor is also connected to the second end of the sixth inductive unit.

[0037] In the embodiment of the application, the source bias circuit is the ground.

[0038] In the embodiment of the application, the source bias circuit comprises:

[0039] The first end of the sixth capacitor is connected to the source of the field effect transistor, the first end of the sixth capacitor is also connected to the source bias power supply end, and the second end of the sixth capacitor is connected to the ground.

[0040] In the embodiments of the present application, the gate bias circuit is ground.

[0041] In the embodiments of the present application, the source bias circuit comprises:

[0042] a seventh capacitor, a first end of the seventh capacitor being connected to the source of the field effect transistor, and a second end of the seventh capacitor being grounded;

[0043] a second resistor, a first end of the second resistor being connected to the source of the field effect transistor, and a second end of the second resistor being grounded.

[0044] In the embodiments of the present application, the first inductor and the second inductor are both spiral inductors and are arranged in opposite spiral directions in the amplifier.

[0045] In the embodiments of the present application, the first inductor and the second inductor are arranged to be mirror images of each other in the amplifier.

[0046] In the embodiments of the present application, the first inductor is composed of a first microstrip line and the first microstrip line is wound into a first spiral pattern, and the second inductor is composed of a second microstrip line and the second microstrip line is wound into a second spiral pattern, wherein a first end and a second end of the first microstrip line are respectively a first end and a second end of the first inductor, a first end and a second end of the second microstrip line are respectively a first end and a second end of the second inductor, and the second end of the first microstrip line and the second end of the second microstrip line are connected together so that the first microstrip line and the second microstrip line form a combined microstrip line.

[0047] In the embodiments of the present application, the first and second spiral patterns do not overlap and are adjacent but at a distance in a direction parallel to the wiring layers of the amplifier.

[0048] In the embodiments of the present application, the combined microstrip line is composed of multiple layers of metal materials, wherein each layer of metal material is located in a different wiring layer of the amplifier.

[0049] In the embodiments of the present application, the combined microstrip line is composed of a single layer of metal material, wherein the single layer of metal material is located in the same or different wiring layers of the amplifier.

[0050] In a second aspect, a radio frequency chip is provided, comprising a substrate, and the amplifier as described above on the substrate.

[0051] In a third aspect, an electronic device is provided, comprising the radio frequency chip as described above.

[0052] The embodiment of the present application provides an amplifier, which comprises: a field effect tube, the field effect tube comprising a drain, a gate and a source, and the field effect tube being used for signal amplification; a drain matching circuit, a first end of the drain matching circuit being connected with the drain of the field effect tube, and a second end of the drain matching circuit being connected with a radio frequency signal output end; a gain equalization circuit, a second end of the gain equalization circuit being connected with the gate of the field effect tube; a gate matching circuit, a first end of the gate matching circuit being connected with a radio frequency signal input end, and a second end of the gate matching circuit being connected with a first end of the gain equalization circuit; a source bias circuit, the source bias circuit being connected with the source of the field effect tube; wherein the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induced magnetic fields. The drain matching circuit comprises an inductance pair with opposite induced magnetic fields, further comprises an LC series network, can improve the suppression degree of high frequency harmonics and stray signals in the radio frequency output signal of the field effect tube, can further improve the output power and energy consumption efficiency of the amplifier, can improve the integration of the drain matching circuit, can reduce the size of the circuit, and can reduce the cost. In addition, the gain equalization circuit of the embodiment of the present application can make the gain of the amplifier flat. BRIEF DESCRIPTION OF DRAWINGS

[0053] The drawings incorporated in the specification and constituting a part hereof illustrate embodiments consistent with the present application and together with the specification serve to explain the principles of the present application.

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced hereinafter. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0055] Figures 1 to 7 The circuit schematic diagram of the amplifier in the embodiment of the present application is shown in the figure.

[0056] Figure 8 The schematic diagram of the radio frequency chip in the embodiment of the present application is shown in the figure.

[0057] Figure 9 The arrangement schematic diagram of the first low-coupling inductance pair in the embodiment of the present application in the amplifier is shown in the figure.

[0058] Figure 10 The schematic diagram of the electronic device in the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] The amplifier provided in this application embodiment can be used as a standalone component or applied to radio frequency chips or system integration.

[0061] like Figure 1 As shown in the figure, this application embodiment provides an amplifier, the amplifier comprising:

[0062] A field-effect transistor 110, comprising a drain, a gate, and a source, is used for signal amplification.

[0063] Drain matching circuit 130, the first terminal of the drain matching circuit 130 is connected to the drain of the field effect transistor 110, and the second terminal of the drain matching circuit 130 is connected to the radio frequency signal output terminal RFOUT;

[0064] A gain equalization circuit 120, the second terminal of which is connected to the gate of the field-effect transistor 110;

[0065] A gate matching circuit 140, the first terminal of which is connected to the radio frequency signal input terminal RFIN, and the second terminal of which is connected to the first terminal of the gain equalization circuit 120.

[0066] Source bias circuit 160, which is connected to the source of field-effect transistor 110;

[0067] The drain matching circuit 130 includes a first low-coupling inductor pair 131, which is an inductor pair with opposite induced magnetic fields.

[0068] The field-effect transistor 110 in this embodiment has three terminals: source (S), gate (G), and drain (D), which are used for amplifying radio frequency signals. Further details will not be provided here.

[0069] In this embodiment, the drain matching circuit 130 is used to match the drain output impedance of the field-effect transistor 110 to a first target impedance, which is the output impedance of the amplifier's RF signal output terminal RFOUT.

[0070] In the embodiments of the present application, the gate matching circuit 140 and the gain equalization circuit 120 jointly act to match the gate input impedance of the field effect tube 110 to a second target impedance, which is the input impedance of the amplifier radio frequency signal output end RFIN.

[0071] In the embodiments of the present application, as shown in Figure 2 The first low-coupling inductor pair 131 includes:

[0072] A first inductor L1, a first end of the first inductor L1 being connected to the drain bias power supply end;

[0073] A second inductor L2, a first end of the second inductor L2 being connected to a second end of the first inductor L1, and a second end of the second inductor L2 being connected to the drain of the field effect tube 110;

[0074] The first inductor L1 and the second inductor L2 are an inductor pair with opposite induced magnetic fields.

[0075] The drain matching circuit 130 further includes:

[0076] A third inductive unit L3, a first end of the third inductive unit L3 being connected to the second end of the first inductor L1;

[0077] A second capacitor C2, a first end of the second capacitor C2 being connected to a second end of the third inductive unit L3, and a second end of the second capacitor C2 being connected to the radio frequency signal output end RFOUT;

[0078] A third capacitor C3, a first end of the third capacitor C3 being connected to the first end of the first inductor L1, and a second end of the third capacitor C3 being grounded;

[0079] The third inductive unit L3 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

[0080] In the embodiments of the present application, the first inductor L1 and the second inductor L2 can be planar spiral inductors, and the spiral direction of the first inductor L1 and the spiral direction of the second inductor L2 are opposite.

[0081] The first inductor L1 and the second inductor L2 can also be other structures and physical layouts capable of realizing opposite directions of induced magnetic fields, which are not described herein again.

[0082] In other embodiments of the present application, the first inductor L1 and the second inductor L2 can also be other structures and physical layouts capable of realizing opposite directions of induced magnetic fields, which are not described herein again.

[0083] When the first inductor L1 and the second inductor L2 are excited by a signal, an induced magnetic field is generated, and the induced magnetic field generates an induced electric field, and the induced electric field generates radiation, thereby causing energy loss.

[0084] In the embodiment, the directions of the induced magnetic fields of the first inductor L1 and the second inductor L2 are opposite, so that the directions of the induced electric fields generated by the induced magnetic fields of the first inductor L1 and the second inductor L2 are also opposite. The two opposite induced electric fields can partially offset each other, so that the radiation generated by the induced electric field is reduced, thereby reducing the energy loss.

[0085] Since the induced electric fields between the first inductor L1 and the second inductor L2 partially offset each other, the physical distance between the first inductor L1 and the second inductor L2 can be closer, thereby reducing the size of the circuit and reducing the cost.

[0086] In the embodiment, the drain matching circuit 130 includes the first low-coupling inductor pair 131, which improves the integration of the drain matching circuit 130, reduces the loss of the matching circuit, improves the output power of the amplifier and the energy efficiency. In addition, the physical distance between the first inductor L1 and the second inductor L2 can be closer, which can reduce the size of the circuit and improve the integration of the amplifier.

[0087] In the embodiment, the third inductive unit L3 and the second capacitor C2 can constitute an LC series circuit 132, which has the function of a band-pass filter, and is used to improve the suppression degree of high-frequency harmonics and stray signals in the radio frequency output signal of the field effect tube 110.

[0088] In the embodiment, the resonance point frequency of the third capacitor C3 is close to or the same as the center frequency of the working frequency band of the amplifier, which is used to realize the isolation of the radio frequency signal of the amplifier and the drain bias power supply end VD, and at the same time provides a radio frequency signal ground for the first end of the first inductor L1.

[0089] In the embodiment, the drain matching circuit 130 includes the first low-coupling inductor pair 131 and further includes the LC series circuit 132, which can improve the suppression degree of high-frequency harmonics and stray signals in the radio frequency output signal of the field effect tube 110, improve the output power of the amplifier and the energy efficiency, improve the integration of the drain matching circuit 130, reduce the size of the circuit, and reduce the cost.

[0090] In the embodiment, the gain equalization circuit 120 includes:

[0091] The first capacitor C1 has a first end connected to the second end of the gate matching circuit 140 and a second end connected to the gate of the field effect tube 110.

[0092] The first unit 121, the first end of the first unit 121 is connected to the first end of the first capacitor C1;

[0093] The second unit 122 has a first end connected to the second end of the first unit 121, and the second end of the second unit 122 is connected to the second end of the first capacitor C1.

[0094] Wherein, the first unit 121 is an inductive unit and the second unit 122 is a resistor; or the first unit 121 is a resistor and the second unit 122 is an inductive unit.

[0095] like Figure 2 In the embodiment shown, the first unit 121 is the fourth inductive unit L4, and the second unit 122 is the first resistor R1. At this time, the first end of the fourth inductive unit L4 is connected to the first end of the first capacitor C1, the first end of the first resistor R1 is connected to the second end of the fourth inductive unit L4, and the second end of the first resistor R1 is connected to the second end of the first capacitor C1.

[0096] In other embodiments of this application, the first unit 121 is a first resistor R1, and the second unit 122 is a fourth inductive unit L4. In this case, the first end of the first resistor R1 is connected to the first end of the first capacitor C1, the first end of the fourth inductive unit L4 is connected to the second end of the first resistor R1, and the second end of the fourth inductive unit L4 is connected to the second end of the first capacitor C1.

[0097] The fourth inductive unit L4 is an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

[0098] In this embodiment, the first capacitor C1 is a high-pass component, exhibiting high-pass characteristics, which facilitates the transmission of high-frequency radio frequency signals while relatively suppressing low-frequency radio frequency signals. The LR series circuit composed of the first unit 121 and the second unit 122 exhibits low-pass characteristics, facilitating the transmission of low-frequency radio frequency signals while relatively suppressing high-frequency radio frequency signals. The first resistor in the LR series circuit is a lossy component, and the fourth inductive unit L4 is an inductive element. Therefore, the transmission of high-frequency signals is suppressed with relatively low loss; low-frequency signals are more favorable for transmission than high-frequency signals, but with greater loss.

[0099] The combined effect of the first capacitor C1 and the LR circuit in the gain equalization circuit 120 results in lower high-frequency signal loss and higher low-frequency signal loss. Since the gain of the field-effect transistor 110 decreases with increasing frequency, the gain equalization circuit 120 allows adjustment of the gain within the operating bandwidth of the field-effect transistor 110, thereby flattening the amplifier's gain.

[0100] As Figure 2 shown in the embodiment of the present application, the gate matching circuit 140 comprises:

[0101] a fourth capacitor C4, a first end of the fourth capacitor C4 being connected with the radio frequency signal input end RFIN;

[0102] a fifth inductive unit L5, a first end of the fifth inductive unit L5 being connected with a second end of the fourth capacitor C4, and a second end of the fifth inductive unit L5 being connected with a first end of the first capacitor C1;

[0103] a sixth inductive unit L6, a first end of the sixth inductive unit L6 being connected with a second end of the fifth inductive unit L5;

[0104] wherein the fifth inductive unit L5 is one of an inductor, a microstrip line or a combination of an inductor and a microstrip line, and the sixth inductive unit L6 is one of an inductor, a microstrip line or a combination of an inductor and a microstrip line.

[0105] The fifth inductive unit L5 and the sixth inductive unit L6 are a second low-coupling inductive pair, and the second low-coupling inductive pair is an inductive pair with opposite directions of induced magnetic field, that is, the fifth inductor L5 and the sixth inductor L6 with opposite directions of induced magnetic field constitute the second low-coupling inductive pair, as Figure 5 shown in the figure.

[0106] As described in the above embodiment, the gate matching circuit 140 comprises an inductive pair with opposite directions of induced magnetic field, specifically the fifth inductor L5 and the sixth inductor L6, which can reduce mutual coupling and energy loss. In addition, the physical distance between the fifth inductor L5 and the sixth inductor L6 can be closer, which can improve the integration of the amplifier, reduce the size of the circuit and reduce the cost.

[0107] As Figure 2 shown in the figure, the amplifier of the embodiment of the present application further comprises:

[0108] a gate bias circuit 150, the gate bias circuit 150 being connected with a third end of the gate matching circuit 140;

[0109] a source bias circuit 160, the source bias circuit 160 being connected with a source of the field effect tube 110.

[0110] As Figure 2 shown in the figure, the gate bias circuit 150 comprises:

[0111] a fifth capacitor C5, a first end of the fifth capacitor C5 being grounded, a second end of the fifth capacitor C5 being connected with a gate bias power supply end VG, and the second end of the fifth capacitor C5 also being connected with a second end of the sixth inductive unit L6.

[0112] As Figure 2 shown, the source bias circuit 160 is grounded, that is, the source of the field effect tube 110 is directly grounded.

[0113] In the embodiment of the present application, the fourth capacitor C4, the fifth capacitor C5, the fifth inductive unit L5 and the sixth inductive unit L6 constitute an amplifier input matching network, which, together with the amplifier equalization circuit 120, is used to match the gate input impedance of the field effect tube 110 to the second target impedance of the amplifier.

[0114] In the embodiment of the present application, the resonant point frequency of the fifth capacitor C5 is close to or the same as the center frequency of the working frequency band of the amplifier, which is used to realize the isolation of the amplifier and the radio frequency signal of the gate bias power supply end VG, and at the same time provides the radio frequency signal ground for the second end of the sixth inductive unit L6.

[0115] In the embodiment of the present application Figure 2 , the gate bias voltage VG is provided to the field effect tube 110 through the gate bias power supply end VG, and the drain bias voltage VD is provided to the field effect tube 110 through the drain bias power supply end VD, so that the field effect tube 110 is in a normal working state. The radio frequency signal is input through the radio frequency signal input end RFIN, and after passing through the gate matching circuit 140 and the gain equalization circuit 120, it drives the gate of the field effect tube 110. After being amplified by the field effect tube 110, it passes through the drain matching circuit 130 and is output by the radio frequency signal output end RFOUT.

[0116] In other embodiments of the present application, as Figure 3 shown, the source bias circuit 160 includes:

[0117] The sixth capacitor C6, the first end of the sixth capacitor C6 is connected with the source of the field effect tube 110, and the first end of the sixth capacitor C6 is also connected with the source bias power supply end VS, and the second end of the sixth capacitor C6 is grounded.

[0118] In the embodiment of the present application, the resonant point frequency of the sixth capacitor C6 is close to or the same as the center frequency of the working frequency band of the amplifier, which is used to realize the isolation of the amplifier and the radio frequency signal of the source bias power supply end VS, and at the same time provides the radio frequency signal ground for the source of the field effect tube 110.

[0119] In the embodiment of the present application Figure 3In the shown embodiment, the gate bias power terminal VG is used to provide the gate bias voltage VG for the amplifier, the drain bias power terminal VD is used to provide the drain bias voltage VD for the amplifier, and the source bias power terminal VS is used to provide the source bias voltage VS for the amplifier. The voltage difference between VG and VS is adjusted to be the gate-source bias power for the field effect transistor 110 in the normal working state, and the voltage difference between VD and VS is adjusted to be the drain-source bias power for the field effect transistor 110 in the normal working state, so that the field effect transistor 110 is in the normal working state. The radio frequency signal is input through the radio frequency signal input terminal RFIN, and is driven to the gate of the field effect transistor 110 in the amplifier through the gate matching circuit 140 and the gain equalization circuit 120. After being amplified by the field effect transistor 110, the radio frequency signal is output through the radio frequency signal output terminal RFOUT via the drain matching circuit 130.

[0120] In other embodiments of the present application, as shown in Figure 4 The gate bias circuit 150 is ground. That is, the second end of the sixth inductive element L6 is grounded.

[0121] As shown in Figure 4 At this time, the source bias circuit 160 includes:

[0122] A seventh capacitor C7, a first end of the seventh capacitor C7 is connected to the source of the field effect transistor 110, and a second end of the seventh capacitor C7 is grounded;

[0123] A second resistor R2, a first end of the second resistor R2 is connected to the source of the field effect transistor 110, and a second end of the second resistor R2 is grounded.

[0124] In the embodiments of the present application, the seventh capacitor C7 couples the radio frequency signal output by the source of the field effect transistor 110 to the ground, and provides the radio frequency signal ground for the source of the field effect transistor 110, thereby reducing the energy loss of the source bias circuit 160.

[0125] In the embodiments of the present application, the second resistor R2 is used to raise the source potential of the field effect transistor 110, so that the voltage between the gate and the source of the field effect transistor 110 is negative, thereby maintaining the normal working of the amplifier.

[0126] In the embodiments of the present application Figure 4In the shown embodiment, the field effect tube 110 is provided with a drain bias voltage VD through the drain bias power supply end VD, at this time, the drain-source current of the field effect tube 110 flows through the resistance R2 in the source bias circuit 160, the source potential of the field effect tube 110 is raised, the gate-source voltage of the field effect tube 110 is negative, and the normal work of the field effect tube 110 is maintained. The radio frequency signal is input through the radio frequency signal input end RFIN, passes through the gate matching circuit 140 and the gain equalization circuit 120, drives the gate of the field effect tube 110, and is output through the radio frequency signal output end RFOUT after being amplified by the field effect tube 110 and passing through the drain matching circuit 130.

[0127] In the embodiment of the present application, any one of the third inductive unit L3, the fourth inductive unit L4, the fifth inductive unit L5 and the sixth inductive unit L6 can be one of an inductor, a microstrip line or a combination of an inductor and a microstrip line, or some of the inductive units are inductors, some of the inductive units are microstrip lines, and some of the inductive units are combinations of inductors and microstrip lines; or all are inductors, or all are microstrip lines, or all are combinations of inductors and microstrip lines, which will not be described here. When the fifth inductive unit L5 and the sixth inductive unit L6 constitute the second low-coupling inductive pair, the fifth inductive unit L5 and the sixth inductive unit L6 are inductors.

[0128] In the embodiment of the present application, the inductive pair with opposite magnetic fields can be included only in the drain matching circuit 130, as shown in Figures 2 to 5 , or the inductive pair with opposite magnetic fields can be included in the drain matching circuit 130 and the gate matching circuit 140 respectively, as shown in Figures 5 to 7 .

[0129] Figures 5 to 7 The structure, function, working process and beneficial effects of the circuit shown can refer to the above-mentioned embodiments and Figures 2 to 4 . Figures 1 to 7 In the shown embodiment, the function units with the same reference numerals have the same or similar functions, which will not be described here.

[0130] As shown in Figures 5 to 7 , referring to the above-mentioned embodiments, the inductive pair with opposite magnetic fields included in the gate matching circuit 140 can reduce energy loss, reduce the size of the amplifier and reduce cost.

[0131] In the embodiment of the present application, the power supply bias mode of the amplifier includes single power supply self-bias, double power supply bias and triple power supply bias, the single power supply self-bias means that only the drain bias voltage VD is provided by the outside world, as shown in Figure 4 and Figure 7 ; the double power supply bias means that the drain bias voltage VD and the gate bias voltage VG are provided by the outside world, as shown in Figure 2 and Figure 5As shown in the figure; three power supply bias refers to the external supply of the gate bias voltage VD, gate bias voltage VG and source bias voltage VS, as shown in Figure 3 and Figure 6 Single power supply self-bias power supply is simple, double power supply bias can play a better power performance, three power supply bias is conducive to energy saving, can be configured according to the actual application of power supply bias mode. The power supply bias mode of the embodiment of the application can also be used in other circuits, which will not be described here.

[0132] The embodiment of the application also provides a radio frequency chip, which comprises a substrate and an amplifier as described above on the substrate.

[0133] As shown in the figure Figure 1 The amplifier comprises:

[0134] The field effect transistor 110;

[0135] The drain matching circuit 130, the first end of the drain matching circuit 130 is connected with the drain of the field effect transistor 110, and the second end of the drain matching circuit 130 is connected with the radio frequency signal output end RFOUT;

[0136] The gain equalization circuit 120, the second end of the gain equalization circuit 120 is connected with the gate of the field effect transistor 110;

[0137] The gate matching circuit 140, the first end of the gate matching circuit 140 is connected with the radio frequency signal input end RFIN, and the second end of the gate matching circuit 140 is connected with the first end of the gain equalization circuit 120;

[0138] The source bias circuit 160, the source bias circuit 160 is connected with the source of the field effect transistor 110;

[0139] Among them, the drain matching circuit 130 comprises a first low coupling inductance pair 131, and the first low coupling inductance pair 131 is an inductance pair with opposite induced magnetic fields.

[0140] The field effect transistor 110 in the embodiment of the application can be a field effect transistor 110 with three poles or three terminals, for example, a field effect transistor, the three poles are source (S pole), gate (G pole) and drain (D pole), which will not be described here.

[0141] In the embodiment of the application, the drain matching circuit 130 is used to match the drain output impedance of the field effect transistor 110 to the first target impedance.

[0142] In the embodiment of the application, as shown in the figure Figure 2 The first low coupling inductance pair 131 comprises:

[0143] a first inductor L1, a first end of the first inductor L1 being connected with a drain bias power terminal VD;

[0144] a second inductor L2, a first end of the second inductor L2 being connected with a second end of the first inductor L1, and a second end of the second inductor L2 being connected with a drain of the field effect transistor 110;

[0145] wherein the first inductor L1 and the second inductor L2 are an inductive pair with opposite inductive magnetic fields.

[0146] The drain matching circuit 130 further comprises:

[0147] a third inductive unit L3, a first end of the third inductive unit L3 being connected with the second end of the first inductor L1;

[0148] a second capacitor C2, a first end of the second capacitor C2 being connected with a second end of the third inductive unit L3, and a second end of the second capacitor C2 being connected with an RF signal output terminal RFOUT;

[0149] a third capacitor C3, a first end of the third capacitor C3 being connected with the first end of the first inductor L1, and a second end of the third capacitor C3 being grounded;

[0150] wherein the third inductive unit L3 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

[0151] In the embodiments of the present application, the first inductor L1 and the second inductor L2 can be planar spiral inductors, and the spiral direction of the first inductor L1 and the spiral direction of the second inductor L2 are opposite.

[0152] The first inductor L1 and the second inductor L2 can also be other structures and physical layouts capable of realizing opposite inductive magnetic fields, which are not described herein again.

[0153] In other embodiments of the present application, the first inductor L1 and the second inductor L2 can also be other structures and physical layouts capable of realizing opposite inductive magnetic fields, which are not described herein again.

[0154] When a signal is excited on an inductor, an inductive magnetic field is generated, which generates an inductive electric field, and the inductive electric field generates an inductive eddy current in the substrate of the chip, thereby causing energy loss; therefore, the first inductor L1 and the second inductor L2 also have inductive magnetic fields, and the inductive electric field generated by the inductive magnetic fields generates an inductive eddy current in the substrate of the chip, thereby causing energy loss.

[0155] In the embodiments of the present application, the directions of the induced magnetic fields of the first inductor L1 and the second inductor L2 are opposite, so that the directions of the induced electric fields generated by the induced magnetic fields of the first inductor L1 and the second inductor L2 are also opposite, the directions of the induced eddy currents generated by the two opposite induced electric fields are opposite, the opposite induced eddy currents can partially cancel each other out, so that the induced eddy currents are reduced, the energy loss is reduced, and thus the energy loss of the chip matching network is reduced.

[0156] Since the induced eddy currents generated by the first inductor L1 and the second inductor L2 on the substrate partially cancel each other out, the physical distance between the first inductor L1 and the second inductor L2 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

[0157] In addition, by the same principle, the chip in the embodiments of the present application can include a second low-coupling inductor pair, specifically a fifth inductor L5 and a sixth inductor L6, which can reduce power consumption, reduce the size of the circuit, and reduce cost.

[0158] The specific implementation of the amplifier in the chip in the embodiments of the present application is described with reference to the above embodiments and Figure 1 The above description is not repeated here.

[0159] It can be seen that the radio frequency chip in the embodiments of the present application has low power consumption, small size, and low cost.

[0160] As Figure 8 shown, the radio frequency chip 1500 can include an amplifier 1501, where the amplifier 1501 can be any embodiment of the amplifier described above. One amplifier 1501 can be used alone, or multiple amplifiers 1501 can be used in combination. In an example, the radio frequency chip 1500 can include one or more amplifiers 1501.

[0161] In the embodiments of the amplifier and the radio frequency chip using the low-coupling inductor pair, the layout of the low-coupling inductor pair greatly affects the size of the circuit. When there is a signal excitation in the inductor, an induced magnetic field is generated, the induced magnetic field generates an induced electric field, and the induced electric field generates radiation, thereby causing energy loss. For example, the induced electric field generates an eddy current in the medium of the circuit and electromagnetic radiation in space. If the two inductors are arranged close to each other, mutual coupling occurs between them, which intensifies such loss. The embodiments of the present application at least partially reduce the mutual coupling between the two inductors by configuring the two inductors of the low-coupling inductor pair to generate induced magnetic fields in opposite directions, so that the directions of the induced electric fields caused by the induced magnetic fields of the two inductors are also opposite, thereby partially or completely canceling each other out, thereby reducing or eliminating the energy loss caused by the induced electric field, so that the two inductors of the low-coupling inductor pair can be arranged closer to each other to further reduce the chip area occupied by the amplifier.

[0162] For example, the first inductor L1 and the second inductor L2 of the first low-coupling inductor pair 131 can be configured to be adjacent to each other such that the direction of the induced magnetic field generated by the first inductor L1 is opposite to the direction of the induced magnetic field generated by the second inductor L2.

[0163] In one example, both the first inductor L1 and the second inductor L2 are spiral inductors, and they can be arranged in the amplifier with opposite spiral directions. For example, one inductor has a clockwise spiral and the other has a counterclockwise spiral.

[0164] In one example, the first inductor L1 and the second inductor L2 are arranged as mirror images of each other in the amplifier.

[0165] Figure 9 A schematic diagram of the arrangement of a first low-coupling inductor pair in an amplifier according to an embodiment of this application is shown. Figure 9 This is a schematic diagram of the first low-coupled inductor pair of the amplifier, viewed from above in a direction perpendicular to the amplifier's wiring layer. In one example, the amplifier could be an RF chip.

[0166] like Figure 9 As shown, the first low-coupling inductor pair 131 includes two inductors, which are respectively composed of a first microstrip line 1314 and a second microstrip line 1315. The first microstrip line 1314 is wound into a first helical pattern S1, and the second microstrip line 1315 is wound into a second helical pattern S2. The first end 1311 and the second end 1312 of the first microstrip line 1314 serve as the first end and the second end of the first inductor L1, respectively. The first end 1313 and the second end 1312 of the second microstrip line 1315 serve as the first end and the second end of the second inductor L2, respectively. The second ends 1312 of the first microstrip line 1314 and the second end 1312 of the second microstrip line 1315 are connected together to form a common terminal 1312 of the first inductor L1 and the second inductor L2, thereby forming a merged microstrip line. The first terminal 1311 of the first inductor L1, the first terminal 1313 of the second inductor L2, and the second terminals 1312 of the first inductor L1 and the second inductor L2 are respectively connected to other parts of the amplifier via connecting wires.

[0167] The merged microstrip line (first microstrip line / second microstrip line) of the embodiments of the present application can be composed of single-layer or multi-layer metal materials. In one example, the merged microstrip line is composed of multi-layer metal materials, each of which is located in a different wiring layer of the amplifier. The multi-layer metal materials located in different wiring layers are superimposed together to form the merged microstrip line, and are connected through interlayer vias between the layers. In another example, the merged microstrip line is composed of single-layer metal materials, which can be located in the same or different wiring layers of the amplifier. For example, part of the single-layer metal materials is located in one wiring layer, and the other part is located in one or more different wiring layers. Similarly, the single-layer metal materials located in different wiring layers are connected through vias.

[0168] In Figure 9 In the example of FIG. 13, the first microstrip line 1314 and the second microstrip line 1315 are wound in opposite directions, such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that when the first low-coupling inductance pair 131 is in operation, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the first end of the first inductance L1 or the second inductance L2 to the common end can be referred to as the spiral direction, or the direction from the common end to the first end of the first inductance L1 or the second inductance L2 can also be referred to as the spiral direction.

[0169] In the example of FIG. 13, the first microstrip line 1314 and the second microstrip line 1315 are wound in opposite directions, such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that when the first low-coupling inductance pair 131 is in operation, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the first end of the first inductance L1 or the second inductance L2 to the common end can be referred to as the spiral direction, or the direction from the common end to the first end of the first inductance L1 or the second inductance L2 can also be referred to as the spiral direction.

[0170] In the example of FIG. 13, the first microstrip line 1314 and the second microstrip line 1315 are wound in opposite directions, such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that when the first low-coupling inductance pair 131 is in operation, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the first end of the first inductance L1 or the second inductance L2 to the common end can be referred to as the spiral direction, or the direction from the common end to the first end of the first inductance L1 or the second inductance L2 can also be referred to as the spiral direction. Figure 9 In the example of FIG. 13, the first microstrip line 1314 and the second microstrip line 1315 are wound in opposite directions, such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that when the first low-coupling inductance pair 131 is in operation, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the first end of the first inductance L1 or the second inductance L2 to the common end can be referred to as the spiral direction, or the direction from the common end to the first end of the first inductance L1 or the second inductance L2 can also be referred to as the spiral direction.

[0171] In summary, each spiral pattern in S1 and S2 can wind the microstrip line from its respective first end to the common end in one of the following ways:

[0172] From the inside out;

[0173] From the outside in;

[0174] The combination of the two above.

[0175] exist Figure 9 In one embodiment, the two spiral patterns S1 and S2 do not overlap and are adjacent but spaced a certain distance D in a direction parallel to the amplifier's wiring layer. In this embodiment, as described above, due to the low mutual coupling between the two inductors, the two spiral patterns S1 and S2 can be arranged as close as possible (but without overlapping), thereby reducing circuit size and cost. In one example, the spacing between the two spiral patterns S1 and S2 (e.g., ...) is... Figure 9 The distance D shown can be as small as approximately 3 micrometers. The "spacing between two spiral patterns" mentioned here refers to the distance between the closest microstrip lines of the two spiral patterns. For example... Figure 9 As shown, distance D is the distance between the outermost adjacent turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

[0176] exist Figure 9 In the example, the first microstrip line 1314 and the second microstrip line 1315 are of equal length. That is, the common terminal 1312 is located at the midpoint of the merged microstrip line. It is understood that the common terminal 1312 may not be located at the midpoint of the merged microstrip line, but at other locations, such as closer to S1 or S2.

[0177] like Figure 9 As shown, in this embodiment, the spiral patterns S1 and S2 are arranged in a mirror image; they are mirror images of each other. Figure 9 The spiral patterns S1 and S2 are arranged symmetrically. That is, they have the same configuration, such as the same number of turns, microstrip linewidth, and spacing between adjacent turns, but their patterns are reversed (the winding methods are opposite). They are symmetrical / mirror images of each other about a plane perpendicular to the wiring layer located between them. S1 and S2 can also be arranged differently; for example, they can have different numbers of turns, microstrip linewidths, or spacing between adjacent turns, as long as the induced magnetic fields of the spiral patterns S1 and S2 are in opposite directions.

[0178] Understandable Figure 9 The arrangement of the first spiral pattern S1 and the second spiral pattern S2 can be interchanged.

[0179] In the first low-coupling inductor pair 131 according to the above-mentioned embodiments of the present application, the microstrip lines of the two inductors have a common end, and are arranged as two spiral patterns with opposite spiral directions. When an excitation signal is applied to the first low-coupling inductor pair 131 in the working state, the excitation signal is split at the common end to the two spirals (the microstrip lines of the two inductors), so that the directions of the induced magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing the mutual coupling / mutual inductance between the two inductors.

[0180] In the above-mentioned inductor pair embodiments, as shown in Figure 9 the inductor pair is arranged in the integrated circuit chip to have three ends: a common end 1312, a head end 1311 as a first branch end of the inductor pair, and a tail end 1313 as a second branch end of the inductor pair. As mentioned above, the three ends of the inductor pair can be connected to an excitation signal or other circuit parts through lead wires. For example, a radio frequency excitation signal can be accessed from the common end 1312 of the inductor pair, and the radio frequency excitation signal is split at the common end 1312 to the first microstrip line (the first inductor) and the second microstrip line (the second inductor). The radio frequency excitation signal is generally a periodically varying signal, for example, a sinusoidal signal. Assuming that the excitation signal accessed at the common end 1312 is i com = I com · sin ωt. The excitation signal is split at the common end 1312 into two branches, one of which flows through the common end 1312 to the first spiral pattern S1 of the first branch end (the head end) 1311, and the other of which flows through the common end 1312 to the second spiral pattern S2 of the second branch end (the tail end) 1313. Assuming that the excitation signal in the first spiral pattern S1 is i1(t), and the excitation signal in the second spiral pattern S2 is i2(t), if there is no reflection, then i1(t) + i2(t) = I com · sin ωt. If the common end is located at the midpoint of the merged microstrip line, and S1 and S2 are patterns that are axisymmetric, then at any time, the excitation signals in S1 and S2 are exactly the same, i.e. The excitation signals i1(t) and i2(t) in the inductor pair are periodically varying signals, and the current magnitudes thereof periodically and unevenly vary, so the induced magnetic fields generated thereby are also periodically and unevenly varying; the varying magnetic fields in turn generate electric fields, thereby generating electromagnetic waves. In the case where the excitation signals in S1 and S2 are exactly the same, since the spiral directions of S1 and S2 are opposite, at any time, the induced magnetic field generated by S1 is of the same magnitude as the induced magnetic field generated by S2, but the directions of the two magnetic fields are opposite, and the corresponding induced electric fields are also of opposite directions and periodically change directions. Therefore, the induced magnetic fields generated by S1 and S2 will almost completely cancel out in many regions, and will partially cancel out in some regions, so the corresponding electric fields or electromagnetic waves caused by the induced magnetic fields will also be partially canceled out, thereby reducing the loss of the inductor pair.

[0181] If the common end is not located at the midpoint of the merged microstrip line, or S1 and S2 are patterns with different configurations, it is possible that the excitation signals in S1 and S2 are not exactly the same, and thus the degree of mutual cancellation of the induced magnetic fields of S1 and S2 is weakened compared with the case where the excitation signals in S1 and S2 are exactly the same, but the induced magnetic fields generated by S1 and S2 still partially cancel each other out and weaken the electromagnetic radiation intensity at any moment, thereby reducing the loss of the inductive pair to a certain extent.

[0182] It should be noted that, in theory, the inductive pair with three ports (a common end, a first end of the merged microstrip line as a first branch end, and a second end of the merged microstrip line as a second branch end) as described above is a passive lossless network, and since a passive network has reciprocity, the loss and transmission characteristics of the inductive pair are reciprocal regardless of which port the excitation signal is input from.

[0183] The first low-coupling inductive pair 131 composed of the first inductor L1 and the second inductor L2 in the amplifier can adopt the low-coupling inductive pair arrangement as described above. The above description of the low-coupling inductive pair applies to all low-coupling inductive pairs involved herein, and for brevity, will not be repeated hereinafter.

[0184] In the above-described amplifier embodiments, the low-coupling inductive pair as described above is used, which makes the amplifier of the present application have the following advantages: by configuring the two inductors that constitute the inductive pair such that the directions of their respective induced magnetic fields are opposite, the inductive pair is a low-coupling inductive pair, which can reduce the loss of the amplifier input matching circuit. In addition, since the coupling between the two inductors that constitute the low-coupling inductive pair and the radiation range of the induced electric field and the induced magnetic field of the inductors can be reduced in this way, the inductors and other components can be arranged closer together, further reducing the circuit size.

[0185] The embodiments of the present application also provide an electronic device, which includes the radio frequency chip as described above, and the radio frequency chip including the amplifier embodiments of the present application can be used in the electronic device.

[0186] As shown in FIG. 16, the electronic device 1600 includes the radio frequency chip 1500 as shown in FIG. 15. The electronic device 1600 can be a wireless device or any other electronic device that can use an amplifier. Figure 10 Figure 8 As shown in FIG. 16, the electronic device 1600 includes the radio frequency chip 1500 as shown in FIG. 15. The electronic device 1600 can be a wireless device or any other electronic device that can use an amplifier.

[0187] ​A wireless device can be a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. A wireless device can also be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. A wireless device can be capable of communicating with a wireless communication system, and can be capable of receiving signals from a broadcast station, from one or more satellites, etc. A wireless device can support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

[0188] The embodiment of the present application provides an amplifier, a radio frequency chip and an electronic device. The amplifier comprises: a field effect tube; a drain matching circuit, a first end of the drain matching circuit being connected with a drain of the field effect tube, and a second end of the drain matching circuit being connected with a radio frequency signal output end; a gain equalization circuit, a second end of the gain equalization circuit being connected with a gate of the field effect tube; a gate matching circuit, a first end of the gate matching circuit being connected with a radio frequency signal input end, and a second end of the gate matching circuit being connected with a first end of the gain equalization circuit; and a source bias circuit, the source bias circuit being connected with a source of the field effect tube. The drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induced magnetic fields. The drain matching circuit comprises an inductance pair with opposite induced magnetic fields and an LC series network, can improve the suppression degree of high-frequency harmonics and stray signals in the radio frequency output signal of the field effect tube, can improve the output power and energy consumption efficiency of the amplifier, can improve the integration of the drain matching circuit, can reduce the size of the circuit, and can reduce the cost. In addition, the gain equalization circuit can make the gain of the amplifier flat. In the embodiment of the present application, the comprehensive effect of the first capacitor C1 in the gain equalization circuit and the LR series circuit can make the loss of high-frequency signals small and the loss of low-frequency signals large. The gain of the field effect tube decreases with the increase of the frequency, and the gain equalization circuit can adjust the gain within the working bandwidth of the amplifier, so that the gain of the amplifier tends to be flat.

[0189] The amplifier in the embodiment of the present application can be independently used, or can be used in multiple stages in cascade, or can be applied to an integrated system, or can be applied to a multifunctional chip. The radio frequency chip in the embodiment of the present application can also comprise an independently used amplifier, or can comprise a plurality of amplifiers used in cascade, or can comprise a plurality of independently used amplifiers.

[0190] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for easy distinction from each other, and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the context, which will not be repeated here.

[0191] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description in other embodiments.

[0192] The units or modules described as separate components can or can not be physically separated, and the components shown as units or modules can or can not be physical units, which can be located in one place or distributed to multiple functional units. Part or all of the units or modules can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0193] In addition, each functional unit or module in each embodiment of the present application can be integrated in one chip unit, or each unit or module can exist physically, or two or more units or modules can be integrated in one unit.

[0194] It should be noted that, in this paper, relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "include", "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the sentence "including a…" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0195] The foregoing detailed description of the application has been presented for purposes of illustration and description. Various modifications and changes can be made to these embodiments without departing from the spirit and scope of the application. It is intended that the scope of the application should not be limited by the particular representative embodiments described above.

Claims

1. An amplifier, characterized in that, The amplifier includes: A field-effect transistor, comprising a drain, a gate, and a source, wherein the field-effect transistor is used for signal amplification; A drain matching circuit, wherein the first terminal of the drain matching circuit is connected to the drain of the field-effect transistor, and the second terminal of the drain matching circuit is connected to the radio frequency signal output terminal; A gain equalization circuit, wherein the second terminal of the gain equalization circuit is connected to the gate of the field-effect transistor; A gate matching circuit, wherein the first terminal of the gate matching circuit is connected to the radio frequency signal input terminal, and the second terminal of the gate matching circuit is connected to the first terminal of the gain equalization circuit. A source bias circuit, wherein the source bias circuit is connected to the source of the field-effect transistor; The drain matching circuit includes a first low-coupling inductor pair, which is an inductor pair with opposite induced magnetic fields. The gain equalization circuit includes: A first capacitor, wherein a first terminal of the first capacitor is connected to a second terminal of the gate matching circuit, and a second terminal of the first capacitor is connected to the gate of the field-effect transistor; The first unit, wherein the first terminal of the first unit is connected to the first terminal of the first capacitor; The second unit has a first end connected to the second end of the first unit, and the second end of the second unit is connected to the second end of the first capacitor. Wherein, the first unit is a fourth inductive unit and the second unit is a first resistor; or the first unit is a first resistor and the second unit is a fourth inductive unit.

2. The amplifier according to claim 1, characterized in that, The first low-coupling inductor pair includes: The first inductor, the first end of the first inductor is connected to the drain bias power supply terminal; The second inductor has its first end connected to the second end of the first inductor, and its second end connected to the drain of the field-effect transistor. Among them, the first inductor and the second inductor are an inductor pair with opposite induced magnetic fields.

3. The amplifier according to claim 2, characterized in that, The drain matching circuit further includes: The third inductive unit, wherein the first end of the third inductive unit is connected to the second end of the first inductor; The second capacitor has its first terminal connected to the second terminal of the third inductive unit, and its second terminal connected to the radio frequency signal output terminal. The third capacitor has its first terminal connected to the first terminal of the first inductor, and its second terminal grounded. The third inductive unit is an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

4. The amplifier according to claim 3, characterized in that, The gate matching circuit includes: The fourth capacitor, the first terminal of which is connected to the radio frequency signal input terminal as the first terminal of the gate matching circuit; The fifth inductive unit has its first end connected to the second end of the fourth capacitor, and its second end serves as the second end of the gate matching circuit, which is connected to the first end of the first capacitor. A sixth sensor unit, wherein the first end of the sixth sensor unit is connected to the second end of the fifth sensor unit, and the second end of the sixth sensor unit serves as the third end of the gate matching circuit; The fifth inductive unit is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line, and the sixth inductive unit is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

5. The amplifier according to claim 4, characterized in that, The fifth and sixth inductive units are a second low-coupling inductor pair, which is an inductor pair with opposite directions of induced magnetic fields.

6. The amplifier according to claim 4 or 5, characterized in that, The amplifier also includes: A gate bias circuit, wherein the gate bias circuit is connected to the third terminal of the gate matching circuit; A source bias circuit is connected to the source of the field-effect transistor.

7. The amplifier according to claim 6, characterized in that, The gate bias circuit includes: The fifth capacitor has its first terminal grounded, its second terminal connected to the gate bias power supply terminal, and its second terminal also connected to the second terminal of the sixth inductive unit.

8. The amplifier according to claim 7, characterized in that, The source bias circuit is ground.

9. The amplifier according to claim 7, characterized in that, The source bias circuit includes: The sixth capacitor has its first terminal connected to the source of the field-effect transistor and its first terminal also connected to the source bias power supply terminal. The second terminal of the sixth capacitor is grounded.

10. The amplifier according to claim 6, characterized in that, The gate bias circuit is ground.

11. The amplifier according to claim 10, characterized in that, The source bias circuit includes: The seventh capacitor has its first terminal connected to the source of the field-effect transistor and its second terminal grounded. The second resistor has its first end connected to the source of the field-effect transistor and its second end grounded.

12. The amplifier according to claim 2, characterized in that, Both the first and second inductors are spiral inductors and are arranged in the amplifier with opposite spiral directions.

13. The amplifier according to claim 2, characterized in that, The first inductor and the second inductor are arranged as mirror images of each other in the amplifier.

14. The amplifier according to claim 2, characterized in that, The first inductor is composed of a first microstrip line wound into a first spiral pattern, and the second inductor is composed of a second microstrip line wound into a second spiral pattern. The first end and the second end of the first microstrip line serve as the first end and the second end of the first inductor, respectively, and the first end and the second end of the second microstrip line serve as the first end and the second end of the second inductor, respectively. The second end of the first microstrip line and the second end of the second microstrip line are connected together to form a merged microstrip line.

15. The amplifier according to claim 14, characterized in that, The first and second spiral patterns do not overlap and are adjacent but spaced apart in a direction parallel to the wiring layer of the amplifier.

16. The amplifier according to claim 14, characterized in that, The merged microstrip line is composed of multiple layers of metal material, with each layer of metal material located in a different wiring layer of the amplifier.

17. The amplifier according to claim 14, characterized in that, The merged microstrip line is made of a single layer of metal material, wherein the single layer of metal material is located in the same or different wiring layers of the amplifier.

18. A radio frequency chip, characterized in that, The radio frequency chip includes a substrate and an amplifier as described in any one of claims 1 to 17 on the substrate.

19. An electronic device, characterized in that, Including the radio frequency chip as described in claim 18.

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