Amplifier, radio frequency chip and electronic device

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier comprises: a three-port transistor, configured to receive a to-be-amplified radio frequency signal from a third pole of the three-port transistor, amplify the to-be-amplified radio frequency signal, and output an in-phase amplified signal from a first pole of the three-port transistor and an anti-phase amplified signal from a second pole of the three-port transistor; a first pole matching circuit, the first pole matching circuit comprises N branches, and a jth branch of the first pole matching circuit is configured to transmit the anti-phase amplified signal to a jth radio frequency signal output end to become a jth amplified signal; a second pole matching circuit, the second pole matching circuit comprises N branches, and a jth branch of the second pole matching circuit is configured to transmit the in-phase amplified signal to an N+jth radio frequency signal output end to become an N+jth amplified signal; wherein j=1...N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1. The application can realize multi-way amplification of a radio frequency signal by using one three-port transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, in particular to an amplifier, a radio frequency chip and an electronic device. BACKGROUND

[0002] With the development of high-frequency wireless communication technology, especially the commercialization of 5G technology and Massive MIMO technology, high-frequency wireless communication technology has become an important development direction of wireless communication.

[0003] A large number of amplifiers are included in a radio frequency communication transceiver system in a high-frequency wireless communication system, and the performance of the amplifiers has an important influence on the performance of the radio frequency communication transceiver system. Therefore, high-frequency wireless communication puts forward higher requirements for the amplifiers, such as the ratio of gain to power consumption. SUMMARY

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides an amplifier, a radio frequency chip and an electronic device.

[0005] In a first aspect, the present application provides an amplifier, which comprises:

[0006] a three-port transistor comprising a first pole, a second pole and a third pole, the three-port transistor being configured to receive a to-be-amplified radio frequency signal from the third pole of the three-port transistor, amplify the to-be-amplified radio frequency signal, and output an inverted amplified signal from the first pole of the three-port transistor and output a non-inverted amplified signal from the second pole of the three-port transistor;

[0007] a first pole matching circuit comprising N branches,

[0008] a first end of a jth branch of the first pole matching circuit being connected to the first pole of the three-port transistor, and a second end of the jth branch of the first pole matching circuit being connected to a jth radio frequency signal output end,

[0009] the jth branch of the first pole matching circuit being configured to match the impedance of the first pole of the three-port transistor to a jth target impedance, the jth target impedance being the output impedance of the jth radio frequency signal output end, and the jth branch of the first pole matching circuit being further configured to transmit the inverted amplified signal to the jth radio frequency signal output end as a jth amplified signal;

[0010] a second pole matching circuit comprising N branches,

[0011] a first end of a jth branch of the second pole matching circuit being connected to the second pole of the three-port transistor, and a second end of the jth branch of the second pole matching circuit being connected to an N+jth radio frequency signal output end,

[0012] The jth branch of the second pole matching circuit is configured to match the impedance of the second pole of the three-port transistor to an N+j target impedance, the N+j target impedance being an output impedance of an N+j radio frequency signal output end, and to transmit the in-phase amplified signal to the N+j radio frequency signal output end as an N+j amplified signal.

[0013] wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0014] In the embodiments of the present application, the jth amplified signal and the N+j amplified signal are synthesized.

[0015] wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0016] In the embodiments of the present application, the jth amplified signal and the N+j amplified signal are synthesized, including:

[0017] The jth radio frequency signal output end is connected to the N+j radio frequency signal output end.

[0018] wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0019] In the embodiments of the present application, the amplifier further includes:

[0020] N impedance transformation circuits,

[0021] wherein the first end of the jth impedance transformation circuit is connected to the jth radio frequency signal output end, and the second end of the jth impedance transformation circuit is connected to a 2N+j radio frequency signal output end.

[0022] wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0023] In the embodiments of the present application, the amplifier further includes N synthesis circuits,

[0024] The jth amplified signal and the N+j amplified signal are synthesized, including:

[0025] The jth radio frequency signal output end is connected to the first end of the jth synthesis circuit, and the N+j radio frequency signal output end is connected to the second end of the jth synthesis circuit, so that the jth amplified signal and the N+j amplified signal are synthesized.

[0026] wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0027] In the embodiments of the present application, the amplifier further includes:

[0028] N impedance conversion circuits,

[0029] a first end of the jth impedance conversion circuit is connected with a third end of the jth combining circuit, and a second end of the jth impedance conversion circuit is connected with a 2N+jth radio frequency signal output end;

[0030] wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0031] In the embodiment of the application, the amplifier further comprises:

[0032] a third pole matching circuit, a first end of the third pole matching circuit being connected with the radio frequency signal input end, and a second end of the third pole matching circuit being connected with a third pole of the three-port transistor;

[0033] a third pole biasing circuit, the third pole biasing circuit being connected with a third end of the third pole matching circuit;

[0034] N first pole biasing circuits, a first end of the jth first pole biasing circuit being connected with a jth first pole biasing power supply end;

[0035] N second pole biasing circuits, a first end of the jth second pole biasing circuit being connected with a third end of a jth branch of the second pole matching circuit;

[0036] wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0037] In the embodiment of the application, the first pole matching circuit

[0038] the jth branch comprises:

[0039] a jth branch first inductive unit, a second end of the jth branch first inductive unit being connected with the first pole of the three-port transistor;

[0040] a jth branch second inductive unit, a first end of the jth branch second inductive unit being connected with the jth first pole biasing power supply end, and a second end of the jth branch second inductive unit being connected with a first end of the jth branch first inductive unit;

[0041] a jth branch third inductive unit, a first end of the jth branch third inductive unit being connected with the first end of the jth branch first inductive unit, and a second end of the jth branch third inductive unit being connected with the jth radio frequency signal output end;

[0042] wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0043] In the embodiment of the present application, the second pole matching circuit jth branch comprises:

[0044] The jth branch fourth inductive unit, the first end of the jth branch fourth inductive unit is connected with the second pole of the three-port transistor;

[0045] The jth branch fifth inductive unit, the first end of the jth branch fifth inductive unit is connected with the second end of the jth branch fourth inductive unit;

[0046] The jth branch first capacitor, the first end of the jth branch first capacitor is connected with the second end of the jth branch fourth inductive unit, and the second end of the jth branch first capacitor is connected with the N+j radio frequency signal output end;

[0047] Wherein, j = 1 … … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0048] In the embodiment of the present application, the third pole matching circuit comprises:

[0049] The sixth inductive unit, the first end of the sixth inductive unit is connected with the third pole of the three-port transistor;

[0050] The seventh inductive unit, the first end of the seventh inductive unit is connected with the second end of the sixth inductive unit, and the second end of the seventh inductive unit is connected with the third pole bias circuit;

[0051] The second capacitor, the first end of the second capacitor is connected with the radio frequency signal input end, and the second end of the second capacitor is connected with the second end of the sixth inductive unit.

[0052] In the embodiment of the present application, the jth branch first inductive unit and the jth branch second inductive unit are an inductance pair with opposite induced magnetic fields; and / or

[0053] The jth branch fourth inductive unit and the jth branch fifth inductive unit are an inductance pair with opposite induced magnetic fields; and / or

[0054] The sixth inductive unit and the seventh inductive unit are an inductance pair with opposite induced magnetic fields;

[0055] Wherein, j = 1 … … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0056] In the embodiment of the present application, the third pole bias circuit comprises:

[0057] The third capacitor, the first end of the third capacitor is grounded, the second end of the third capacitor is connected with the second end of the seventh inductive unit, and the second end of the third capacitor is also connected with the third pole bias power supply end.

[0058] In the embodiments of the present application, the jth second electrode biasing circuit comprises:

[0059] a jth fourth capacitor, a first end of the jth fourth capacitor being connected with the second end of the jth branch fifth inductive unit, the first end of the jth fourth capacitor also being connected with the jth second electrode biasing power supply end, and a second end of the jth fourth capacitor being grounded;

[0060] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0061] In the embodiments of the present application, the jth second electrode biasing circuit is ground.

[0062] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0063] In the embodiments of the present application, the third electrode biasing circuit is ground.

[0064] In the embodiments of the present application, the jth second electrode biasing circuit comprises:

[0065] a jth sixth capacitor, a first end of the jth sixth capacitor being connected with the second end of the jth branch fifth inductive unit, and a second end of the jth sixth capacitor being grounded;

[0066] a jth first resistor, a first end of the jth first resistor being connected with the second end of the jth branch fifth inductive unit, and a second end of the jth first resistor being grounded;

[0067] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0068] In the embodiments of the present application, the jth first electrode biasing circuit comprises:

[0069] a jth seventh capacitor, a first end of the jth seventh capacitor being grounded, and a second end of the jth seventh capacitor being connected with the jth first electrode biasing power supply end;

[0070] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0071] In a second aspect, the present application provides a radio frequency chip, which comprises a substrate and an amplifier as described above on the substrate.

[0072] In a third aspect, an electronic device is provided, which comprises a radio frequency chip as described above.

[0073] The embodiment of the present application provides an amplifier, which comprises: a three-port transistor comprising a first pole, a second pole and a third pole, the three-port transistor is used for receiving a to-be-amplified radio frequency signal from the third pole of the three-port transistor, outputting an inverted amplified signal from the first pole of the three-port transistor after amplifying the to-be-amplified radio frequency signal, and outputting a non-inverted amplified signal from the second pole of the three-port transistor; a first pole matching circuit, the first pole matching circuit comprises N branches, a first end of the jth branch of the first pole matching circuit is connected with the first pole of the three-port transistor, and a second end of the jth branch of the first pole matching circuit is connected with a jth radio frequency signal output end, the jth branch of the first pole matching circuit is used for matching the impedance of the first pole of the three-port transistor to a jth target impedance, the jth target impedance is the output impedance of the jth radio frequency signal output end, and the jth branch of the first pole matching circuit is also used for transmitting the inverted amplified signal to the jth radio frequency signal output end to become a jth amplified signal; a second pole matching circuit, the second pole matching circuit comprises N branches, a first end of the jth branch of the second pole matching circuit is connected with the second pole of the three-port transistor, and a second end of the jth branch of the second pole matching circuit is connected with an N+jth radio frequency signal output end, the jth branch of the second pole matching circuit is used for matching the output impedance of the second pole of the three-port transistor to an N+jth target impedance, the N+jth target impedance is the output impedance of the N+jth radio frequency signal output end, and the jth branch of the second pole matching circuit is also used for transmitting the non-inverted amplified signal to the N+jth radio frequency signal output end to become an N+jth amplified signal; wherein, j=1...N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1. The embodiment of the present application can realize multi-way amplification of a radio frequency signal by using one three-port transistor, thereby improving the functional density of the amplifier and improving the ratio of gain to power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0074] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows, and obviously, other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0076] Figures 1-26 、 Figures 30-36 The structural schematic diagram of the amplifier in the embodiment of the present application;

[0077] Figures 27-29 The signal schematic diagram of the amplifier in the embodiment of the present application;

[0078] Figure 37 a schematic diagram of a radio frequency chip in an embodiment of the present application;

[0079] Figure 38 a schematic diagram of arrangement of low-coupling inductors in an amplifier in an embodiment of the present application;

[0080] Figure 39 a schematic diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0082] The amplifier provided by the embodiments of the present application can be applied as an independent component, or can be applied in a radio frequency chip or a system integration.

[0083] As shown in Figure 1 the amplifier comprises:

[0084] a three-port transistor 111, comprising a first pole, a second pole and a third pole, the three-port transistor 111 being configured to receive a to-be-amplified radio frequency signal SIN from the third pole of the three-port transistor 111, amplify the to-be-amplified radio frequency signal SIN, and output an in-phase amplified signal SO2 from the second pole of the three-port transistor 111 and an anti-phase amplified signal SO1 from the first pole of the three-port transistor 111;

[0085] a first pole matching circuit 112, the first pole matching circuit 112 comprising N branches,

[0086] a first end of a jth branch 112_j of the first pole matching circuit 112 being connected to the first pole of the three-port transistor 111, and a second end of the jth branch 112_j of the first pole matching circuit 112 being connected to a jth radio frequency signal output end RFOUT_j,

[0087] The jth branch 112_j of the first pole matching circuit 112 is configured to match the impedance of the first pole of the three-port transistor 111 to a jth target impedance ZO_j, the jth target impedance ZO_j being an output impedance of a jth radio frequency signal output terminal RFOUT_j, and the jth branch 112_j of the first pole matching circuit 112 is further configured to transmit the inverted amplified signal SO1 to the jth radio frequency signal output terminal RFOUT_j to become a jth amplified signal S_j;

[0088] The second pole matching circuit 113 includes N branches,

[0089] The first end of the jth branch 113_j of the second pole matching circuit 113 is connected to the second pole of the three-port transistor 111, and the second end of the jth branch 113_j of the second pole matching circuit 113 is connected to an N+jth radio frequency signal output terminal RFOUT_N+j,

[0090] The jth branch 113_j of the second pole matching circuit 113 is configured to match the output impedance of the second pole of the three-port transistor 111 to an N+jth target impedance ZO_N+j, the N+jth target impedance ZO_N+j being an output impedance of the N+jth radio frequency signal output terminal RFOUT_N+j, and the jth branch 113_j of the second pole matching circuit 113 is further configured to transmit the in-phase amplified signal SO2 to the N+jth radio frequency signal output terminal RFOUT_N+j to become an N+jth amplified signal S_N+j.

[0091] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0092] In the embodiments of the present application, the three-port transistor 111 can be a field effect transistor 1111 or a triode 1112.

[0093] In the embodiments of the present application, the jth amplified signal S_j and the N+jth amplified signal S_N+j are combined.

[0094] wherein j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0095] In the embodiments of the present application, the jth amplified signal S_j and the N+jth amplified signal S_N+j can be directly combined, as shown in Figure 2 or can be combined through a combining circuit, as shown in Figure 3 .

[0096] As shown in Figure 2 , the combination of the jth amplified signal S_j and the N+jth amplified signal S_N+j includes:

[0097] The jth radio frequency signal output end RFOUT_j is connected with the N+jth radio frequency signal output end RFOUT_N+j.

[0098] Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0099] As shown in the figure, the amplifier further comprises: Figure 2

[0100] N impedance transformation circuits 150,

[0101] Wherein, the first end of the jth impedance transformation circuit 150_j is connected with the jth radio frequency signal output end RFOUT_j, and the second end of the jth impedance transformation circuit 150_j is connected with the 2N+jth radio frequency signal output end RFOUT_2N+j.

[0102] Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0103] As shown in the figure, the amplifier further comprises N synthesis circuits 170, Figure 3

[0104] The jth amplified signal S_j is synthesized with the N+jth amplified signal S_N+j, comprising:

[0105] The jth radio frequency signal output end RFOUT_j is connected with the first end of the jth synthesis circuit 170_j, and the N+jth radio frequency signal output end RFOUT_N+j is connected with the second end of the jth synthesis circuit 170_j, so that the jth amplified signal S_j and the N+jth amplified signal S_N+j are synthesized.

[0106] Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0107] As shown in the figure, the amplifier further comprises: Figure 3

[0108] N impedance transformation circuits 150,

[0109] The first end of the jth impedance transformation circuit 150_j is connected with the third end of the jth synthesis circuit 170_j, and the second end of the jth impedance transformation circuit 150_j is connected with the 2N+jth radio frequency signal output end RFOUT_2N+j.

[0110] Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0111] As shown in the figure, the amplifier further comprises: Figure 1

[0112] ​​​​A third pole matching circuit 130, a first end of the third pole matching circuit 130 is connected with the radio frequency signal input end RFIN, and a second end of the third pole matching circuit 130 is connected with the third pole of the three-port transistor 111;

[0113] A third pole bias circuit 160, the third pole bias circuit 160 is connected with a third end of the third pole matching circuit 130;

[0114] N first pole bias circuits 120, a first end of the jth first pole bias circuit 120_j is connected with a jth first pole bias power supply end V1_j;

[0115] N second pole bias circuits 140, a first end of the jth second pole bias circuit 140_j is connected with a third end of the jth branch 113_j of the second pole matching circuit 113;

[0116] Wherein, j = 1 … … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0117] In the embodiment of the application, the jth first pole bias circuit 120_j is used to provide the first pole of the three-port transistor 111 with a bias power supply V1_j, and simultaneously provide the third end of the jth branch 112_j of the first pole matching circuit 112 with a radio frequency signal ground.

[0118] The third pole matching circuit 130 is used to match the input impedance of the third pole of the three-port transistor 111 to a third target impedance, the third target impedance is the impedance of the radio frequency signal input end RFIN, and the input impedance matching of the amplifier is realized.

[0119] The jth second pole bias circuit 140_j is used to provide the second pole of the three-port transistor 111 with a bias power supply V2_j (not marked in the figure), and simultaneously provide the third end of the jth branch 113_j of the second pole matching circuit 113 with a radio frequency signal ground.

[0120] In the embodiment of the application, the plurality of first pole bias power supply ends can be physically independent, but electrically equivalent. Therefore, for the convenience of description, in the embodiment of the application and the drawings, the first pole bias power supply end V1_j can be directly recorded as the first pole bias power supply end V1.

[0121] In the embodiment of the application, although there are a plurality of first pole bias power supply ends V1, only any first pole bias power supply end V1 needs to be connected with the first pole bias power supply. Similarly, the second pole bias power supply V2 can be set as above.

[0122] The third pole bias circuit 160 is used to provide the third pole of the three-port transistor 111 with a bias power supply V3 (not marked in the figure), and simultaneously provide the third end of the third pole matching circuit 130 with a radio frequency signal ground.

[0123] In the embodiment of the present application, the jth branch 112_j of the first pole matching circuit 112 and the three-port transistor 111 constitute a first radio frequency signal amplification link, and the jth branch 113_j of the second pole matching circuit 113 and the three-port transistor 111 constitute a second radio frequency signal amplification link. Therefore, the amplifier of the embodiment of the present application can amplify the input radio frequency signal in 2N ways, thereby improving the functional density of the amplifier.

[0124] In the above description, j = 1 … N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

[0125] In the embodiment of the present application, the input signal, the output signal and the amplified signal are all radio frequency signals.

[0126] Hereinafter, the case of N = 1 and the three-port transistor 111 being a field effect transistor 1111 is taken as an example for description.

[0127] In the embodiment of the present application, when the three-port transistor 111 is a field effect transistor 1111, as shown in FIG. 1, the first pole is the drain (D pole), the second pole is the source (S pole), and the third pole is the gate (G pole). At this time, the first pole matching circuit 112 is a drain matching circuit 112, the second pole matching circuit 112 is a source matching circuit 113, the third pole matching circuit 130 is a gate matching circuit 130, the first pole bias circuit 120_1 is a first drain bias circuit 120_1, the second pole bias circuit 140_1 is a first source bias circuit 140_1, and the third pole bias circuit 160 is a gate bias circuit 160. Figure 4 In the prior art, according to the working principle of the field effect transistor 1111, the drain current of the field effect transistor 1111 and the source current of the field effect transistor 1111 are inversely proportional, and in an ideal state, the drain current and the source current are equal.

[0128] In the embodiment of the present application, as shown in FIG. 1, the amplifier based on the field effect transistor 1111 for amplifying radio frequency signals can be decomposed into two radio frequency signal amplifiers.

[0129] Figure 4 In the embodiment of the present application, as shown in FIG. 1, the amplifier based on the field effect transistor 1111 for amplifying radio frequency signals can be decomposed into two radio frequency signal amplifiers. Figure 5 Figure 6 ​​The source follower amplifier is shown. The radio frequency signal is input from the gate matching circuit 130, so that the radio frequency signal to be amplified SIN is amplified by the equivalent common source amplifier to become the first amplified signal S_1, and is output through the first radio frequency signal output end RFOUT_1; the radio frequency signal is simultaneously input from the gate matching circuit 130, so that the radio frequency signal to be amplified SIN is amplified by the equivalent source follower amplifier to become the second amplified signal S_2, and is output through the second radio frequency signal output end RFOUT_2.

[0130] As shown in Figure 5 , the field effect transistor 1111, the gate matching circuit 130, the gate bias circuit 160, the first branch 112_1 of the drain matching circuit 112, the first drain bias circuit 120_1, and the source equivalent impedance ZS constitute an equivalent common source amplifier, wherein the source equivalent impedance ZS is the equivalent impedance of the first end of the first branch 113_1 of the source matching circuit 113. The radio frequency signal is input from the gate matching circuit 130, so that the radio frequency signal to be amplified SIN drives the gate of the field effect transistor 1111, and the inverted amplified signal SO1 is output after being inverted and amplified by the field effect transistor 1111. The inverted amplified signal SO1 passes through the first branch 112_1 of the drain matching circuit 112, and the first amplified signal S_1 is output.

[0131] As shown in Figure 6 , the field effect transistor 1111, the gate matching circuit 130, the gate bias circuit 160, the first branch 113_1 of the source matching circuit 113, the first source bias circuit 140_1, and the drain equivalent impedance ZD constitute an equivalent source follower amplifier, wherein the drain equivalent impedance ZD is the equivalent impedance of the first end of the first branch 112_1 of the drain matching circuit 112. The radio frequency signal is input from the gate matching circuit 130, so that the radio frequency signal to be amplified SIN drives the gate of the field effect transistor 1111, and the non-inverted amplified signal SO2 is output after being non-inverted and amplified by the field effect transistor 1111. The non-inverted amplified signal SO2 passes through the first branch 113_1 of the source matching circuit 113, and the second amplified signal S_2 is output.

[0132] The amplifier of the embodiment of the application only uses one field effect transistor 1111, and performs two-way amplification on the radio frequency input signal, that is, realizes two-way amplification of the radio frequency input signal through the common source amplifier and the source follower amplifier.

[0133] As shown in Figure 7 , the first branch 112_1 of the drain matching circuit 112 comprises:

[0134] The first inductive unit L1_1 of the first branch, wherein the second end of the first inductive unit L1_1 is connected to the drain of the field effect transistor 1111;

[0135] A first branch second inductive unit L2_1, a first end of the first branch second inductive unit L2_1 is connected with a first drain bias power supply end VD, a second end of the first branch second inductive unit L2_1 is connected with a first end of the first branch first inductive unit L1_1;

[0136] A first branch third inductive unit L3_1, a first end of the first branch third inductive unit L3_1 is connected with the first end of the first branch first inductive unit L1_1, and a second end of the first branch third inductive unit L3_1 is connected with the first radio frequency signal output end RFOUT_1.

[0137] In the embodiments of the present application, the plurality of first pole / drain bias power supply ends can be physically independent, but electrically equivalent. Therefore, for the convenience of description, in the embodiments of the present application and the drawings, the first pole / drain bias power supply end VD_1 can be directly recorded as the first pole / drain bias power supply end VD. Similarly, the second pole / source bias power supply end VS_1 can also be set as above.

[0138] As shown in FIG. 1, the source matching circuit 113 includes: Figure 7

[0139] A first branch fourth inductive unit L4_1, a first end of the first branch fourth inductive unit L4_1 is connected with the source of the field effect transistor 1111;

[0140] A first branch fifth inductive unit L5_1, a first end of the first branch fifth inductive unit L5_1 is connected with a second end of the first branch fourth inductive unit L4_1;

[0141] A first branch first capacitor C1_1, a first end of the first branch first capacitor C1_1 is connected with the second end of the first branch fourth inductive unit L4_1, and a second end of the first branch first capacitor C1_1 is connected with the second radio frequency signal output end RFOUT_2.

[0142] As shown in FIG. 1, the third pole matching circuit 130 includes: Figure 7

[0143] A sixth inductive unit L6, a first end of the sixth inductive unit L6 is connected with the gate of the field effect transistor 1111;

[0144] A seventh inductive unit L7, a first end of the seventh inductive unit L7 is connected with a second end of the sixth inductive unit L6, and a second end of the seventh inductive unit L7 is connected with the third pole bias circuit 160;

[0145] ​​A second capacitor C2, a first end of the second capacitor C2 is connected with the radio frequency signal input end RFIN, a second end of the second capacitor C2 is connected with the second end of the sixth inductive unit L6.

[0146] In the embodiment of the present application, the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch are an inductive pair with opposite magnetic fields; and / or

[0147] The fourth inductive unit L4_1 and the fifth inductive unit L5_1 of the first branch are an inductive pair with opposite magnetic fields; and / or

[0148] The sixth inductive unit L6 and the seventh inductive unit L7 are an inductive pair with opposite magnetic fields.

[0149] In the embodiment of the present application, the inductive pair with opposite magnetic fields is composed of a pair of inductors with opposite magnetic fields. That is, when the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch are an inductive pair with opposite magnetic fields, they can only be the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch. Other inductive pairs are the same as the above inductive pair, which will not be described here.

[0150] When a signal is excited on an inductor, an induced magnetic field is generated, which generates an induced electric field, and the induced electric field generates radiation, thereby causing energy loss.

[0151] In the embodiment of the present application, the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch are a low-coupling inductive pair, the directions of the induced magnetic fields of the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch are opposite, so that the directions of the induced electric fields generated by the induced magnetic fields of the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch are also opposite, and the two opposite induced electric fields can partially offset, so that the radiation generated by the induced electric field is reduced, thereby reducing the energy loss. Since the induced electric field between the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch is partially offset, the induced electric field of the second inductive unit L2_1 weakens the influence range of the induced electric field of the first inductive unit L1_1, and for the same reason, the induced electric field of the first inductive unit L1_1 weakens the influence range of the induced electric field of the second inductive unit L2_1, so the physical distance between the first inductive unit L1_1 and the second inductive unit L2_1 of the first branch can be closer. For the same reason, the physical distance between the low-coupling inductive pair and other devices can also be closer, thereby reducing the size of the circuit and reducing the cost. For the same reason, the directions of the induced magnetic fields of the fourth inductive unit L4_1 and the fifth inductive unit L5_1 of the first branch are opposite, which can reduce the energy loss, reduce the size of the circuit, and reduce the cost, which will not be described here.

[0152] In the embodiments of the present application, any inductive unit is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line. In the embodiments of the present application, any one of the plurality of inductive units can be one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line, or some of the inductive units are inductors, some of the inductive units are microstrip lines, and some of the inductive units are combinations of inductors and microstrip lines; or all are inductors, or all are microstrip lines, or all are combinations of inductors and microstrip lines, which will not be described here.

[0153] In the embodiments of the present application, the inductive units constituting the low-coupling inductor pair can only be two inductors, which will not be described here. Therefore, in the embodiments of the present application, the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field can be referred to as a low-coupling inductor pair, and by analogy, the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field can also be referred to as a low-coupling inductor pair, and the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field can also be referred to as a low-coupling inductor pair.

[0154] The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5. Figure 7 The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5. Figure 8 The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5. Figure 9 The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5. Figure 10 The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5. Figures 11-13 The amplifier core unit in the embodiments of the present application can have no any low-coupling inductor pair, as shown in FIG. 1; or can include a low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 2; or can include a low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch with opposite directions of induced magnetic field, as shown in FIG. 3; or can include a low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of induced magnetic field, as shown in FIG. 4; or can include any two or three of the above three low-coupling inductor pairs, as shown in FIG. 5.

[0155] As shown in FIG. 6, the gate bias circuit 160 includes: Figure 7 As shown in FIG. 6, the gate bias circuit 160 includes:

[0156] The third capacitor C3 has a first end grounded, a second end connected to the second end of the seventh inductive unit L7, and a second end connected to the third gate bias power supply end VG.

[0157] In the embodiments of the present application, the resonant point frequency of the third capacitor C3 is close to or the same as the center frequency of the working frequency band of the amplifier, for realizing the isolation of the amplifier and the radio frequency alternating current signal of the gate bias power supply end VG, and simultaneously providing the second end of the seventh inductive unit L7 with a radio frequency signal ground.

[0158] As Figure 7 shown, the first second pole bias circuit 140_1 includes:

[0159] A first fourth capacitor C4_1, a first end of the first fourth capacitor C4_1 is connected with a second end of the first branch fifth inductive unit L5_1, and the first end of the first fourth capacitor C4_1 is also connected with a source bias power supply end VS, and a second end of the first fourth capacitor C4_1 is grounded.

[0160] In the embodiment of the application, the resonance point frequency of the first fourth capacitor C4_1 is close to or the same as the center frequency of the amplifier working frequency band, which is used to realize the isolation of the radio frequency alternating current signal of the amplifier and the source bias power supply end VS, and at the same time, the radio frequency signal ground is provided for the second end of the first branch fifth inductive unit L5_1.

[0161] As Figure 7 shown, the first second pole bias circuit 140_1 includes:

[0162] A first seventh capacitor C7_1, a first end of the first seventh capacitor C7_1 is grounded, and a second end of the first seventh capacitor C7_1 is connected with a first drain bias power supply end VD.

[0163] In the embodiment of the application, the resonance point frequency of the first seventh capacitor C7_1 is close to or the same as the center frequency of the amplifier working frequency band, which is used to realize the isolation of the radio frequency alternating current signal of the amplifier and the first drain bias power supply end VD, and at the same time, the radio frequency signal ground is provided for the first end of the first branch second inductive unit L2_1.

[0164] In the embodiment of the application Figures 8-13 , the gate bias voltage VG is provided for the field effect transistor 1111 of the amplifier through the gate bias power supply end VG, the drain bias voltage VD is provided for the field effect transistor 1111 of the amplifier through the drain bias power supply end VD, the source bias voltage VS is provided for the field effect transistor 1111 of the amplifier through the source bias power supply end VS, the voltage difference between VG and VS is adjusted to be the gate-source bias voltage difference in the normal working state of the field effect transistor 1111, the voltage difference between VD and VS is adjusted to be the drain-source bias voltage difference in the normal working state of the field effect transistor 1111, and the field effect transistor 1111 is in the normal working state. The input signal is input through the radio frequency signal input end RFIN, drives the gate of the field effect transistor 1111 in the amplifier core unit through the gate matching circuit 130, and after being amplified by the field effect transistor 1111, the first amplification signal S_1 and the second amplification signal S_2 are formed through the first branch 112_1 of the drain matching circuit 112 and the first branch 113_1 of the source matching circuit 113 respectively.

[0165] As Figure 14As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded.

[0166] Figure 14 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded. Figures 15-18 As shown, the specific implementation is described above with reference to the above embodiment and the accompanying drawings, which will not be repeated here.

[0167] The present application Figures 14-18 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded.

[0168] The present application Figures 14-18 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded. Figure 14 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded. Figures 15-18 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded.

[0169] The present application Figure 19 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded.

[0170] As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded. Figure 19 As shown, in the embodiment of the present application, the first source bias circuit 140_1 is ground. That is, the second end of the first branch fifth inductive unit L5_1 is directly grounded.

[0171] The first sixth capacitor C6_1, the first end of the first sixth capacitor C6_1 is connected with the second end of the first branch fifth inductive unit L5_1, and the second end of the first sixth capacitor C6_1 is grounded.

[0172] The first first resistor R1_1, the first end of the first first resistor R1_1 is connected with the second end of the first branch fifth inductive unit L5_1, and the second end of the first first resistor R1_1 is grounded.

[0173] In the embodiment of the present application, the first sixth capacitor C6_1 is used to couple the signal output by the source of the field effect transistor 1111 and passing through the inductor to the ground, thereby constituting the radio frequency signal ground and reducing the energy loss of the source circuit.

[0174] In the embodiment of the present application, the first resistor R1_1 is used to raise the source potential of the field effect transistor 1111, so that the voltage from the gate to the source of the field effect transistor 1111 (depletion type field effect transistor) is negative, thereby maintaining the normal operation of the amplifier.

[0175] In the embodiment of the present application, Figures 19-23 In the embodiment of the present application, the first sixth capacitor C6_1 is used to couple the signal output by the source of the field effect transistor 1111 and passing through the inductor to the ground, thereby constituting the radio frequency signal ground and reducing the energy loss of the source circuit.

[0176] In the embodiment of the present application, Figures 19-23 In the embodiment of the present application, the low-coupling inductor pair can not be included, as shown in Figure 19 Or at least one low-coupling inductor pair can be included, as shown in Figures 20-23 The combination mode of all low-coupling inductor pairs is not shown in the drawings of the present application, and will not be described here.

[0177] Figures 19-23 In the N=1 embodiment shown in

[0178] In an embodiment of the present application, the first branch first capacitor C1_1 can not be included in the first branch 112_1 of the source matching circuit 112, but a capacitor is arranged in the first branch 113_1 of the drain matching circuit 113, that is, the positions of the first branch third inductive capacitor L3_1 and the first branch first capacitor C1_1 in Figure 7 are interchanged. The connection mode of other parts of the circuit after interchanging can refer to the above-mentioned embodiments and the drawings shown, and the working principle and working process are similar or the same as the above-mentioned embodiments, and will not be described here.

[0179] In the embodiments of this application, the power supply biasing methods of the amplifier include single-supply self-biasing, dual-supply biasing, and triple-supply biasing. Single-supply self-biasing refers to the amplifier being biased by only the drain bias voltage VD provided externally, such as... Figures 19-23 As shown; dual-supply bias refers to the external supply of drain bias voltage VD and gate bias voltage VG, such as... Figures 14-18 As shown; three-supply bias refers to the external supply of gate bias voltage VD, gate bias voltage VG, and source bias voltage VS, as shown. Figures 7-13 As shown. Single-supply self-biased power supply is simple, dual-supply biased power supply can achieve better power performance, and triple-supply biased power supply is beneficial for energy saving. The power supply biasing method can be configured according to the actual application. The power supply biasing method of the embodiments of this application can also be used in other circuits, which will not be described in detail here.

[0180] In this embodiment of the application, the first amplified signal S_1 and the second amplified signal S_2 are synthesized. The synthesis method can be direct synthesis, such as... Figure 24 As shown, it can also be synthesized through a synthesis circuit, such as Figure 25 As shown.

[0181] like Figure 24 As shown, the first amplified signal S_1 and the second amplified signal S_2 are combined, including:

[0182] The first radio frequency signal output terminal RFOUT_1 and the second radio frequency signal output terminal RFOUT_2 are connected.

[0183] like Figure 24 As shown, the amplifier also includes a first impedance transformation circuit 150_1. The first terminal of the first impedance transformation circuit 150_1 is connected to the first radio frequency signal output terminal RFOUT_1. At this time, the first terminal of the first impedance transformation circuit 150_1 is also connected to the second radio frequency signal output terminal RFOUT_2. The second terminal of the first impedance transformation circuit 150_1 is connected to the third radio frequency signal output terminal RFOUT_3.

[0184] The first impedance transformation circuit 150_1 in this embodiment has a DC blocking function from the first terminal of the first impedance transformation circuit 150_1 to ground, and also has a DC blocking function from the first terminal of the first impedance transformation circuit 150_1 to the second terminal of the first impedance transformation circuit 150_1.

[0185] The first impedance transformation circuit 150_1 in this application embodiment can be a λ / 4 impedance transformation circuit in the prior art, or any impedance matching circuit in the prior art that can meet the amplifier requirements of this application embodiment.

[0186] The first impedance transformation circuit 150_1 is used to transform the combined impedance of the first target impedance ZO_1 and the second target impedance ZO_2 to the output impedance of the amplifier.

[0187] In the embodiments of this application, Figure 5 and Figure 6 The amplifier's RF signal input terminal is connected, which can be equivalent to... Figure 26 In the circuit shown, the first amplified signal S_1 and the second amplified signal S_2 will be superimposed on each other.

[0188] Figure 5 The phase and sum of the inverted amplified signal SO1 output by the common-source amplifier shown Figure 6 The phase of the in-phase amplified signal SO2 output by the source follower amplifier shown is out of phase, as... Figure 27 (a) and Figure 27 As shown in (b), if SO1 and SO2 are directly synthesized, their amplitudes will cancel each other out. Under ideal conditions, SO1 and SO2 will completely cancel each other out after synthesis. The synthesis state after complete cancellation is shown in the figure. Figure 27 As shown in (c), at this time, the amplifier that combines the two amplified signals cannot effectively amplify the radio frequency signal.

[0189] In the embodiments of this application, Figure 5 amplifier and Figure 6 The amplifier employs a corresponding matching circuit, ideally ensuring that the phase difference between the first amplified signal S_1 and the second amplified signal S_2 is 2nπ, where n is an integer. Figure 28 (a) and Figure 28 As shown in (b), when two continuous, periodic signals with a phase difference of 2nπ are superimposed, their corresponding peaks and troughs can be superimposed, thus enhancing the signal amplitude. One possible scenario is that the phase difference between the peaks of the two signals is 0, resulting in the superposition as shown in (b). Figure 28 As shown in (c).

[0190] The following explains the effect of the matching circuit on the phase of the amplified signal.

[0191] In this embodiment, the first branch 112_1 of the drain matching circuit 112 and the first branch 113_1 of the source matching circuit 113 include an inductive unit and a capacitor. Therefore, the phase of the RF signal at the drain of the three-port transistor and the phase of the RF signal at the source will shift accordingly. For example, a series inductive unit will cause phase lag, and a series capacitor will cause phase lead. The first branch 112_1 of the drain matching circuit 112 causes the phase of the signal S_1 relative to the signal SO1 to shift by Δφ1, and the first branch 113_1 of the source matching circuit 113 causes the phase of the signal S_2 relative to the signal SO2 to shift by Δφ2.Figure 29 The absolute value of the difference between Δφ1 and Δφ2 is (2n-1)π, and n is an integer. Since SO1 and SO2 are in opposite phase, the phase difference is π, so the phase difference between S_1 and S_2 is 2nπ, and n is an integer. As shown in the schematic diagram shown in FIG. 6, only one period of signals of SO1, SO2, S_1 and S_2 is shown, and in fact, SO1, SO2, S_1 and S_2 are all periodic continuous signals. Figure 29 The absolute value of the difference between Δφ1 and Δφ2 is (2n-1)π, and n is an integer. Since SO1 and SO2 are in opposite phase, the phase difference is π, so the phase difference between S_1 and S_2 is 2nπ, and n is an integer. As shown in the schematic diagram shown in FIG. 6, only one period of signals of SO1, SO2, S_1 and S_2 is shown, and in fact, SO1, SO2, S_1 and S_2 are all periodic continuous signals. Figure 29 Only the case where the phase difference is a certain difference is shown, and in fact, the phase difference between S_1 and S_2 is 2nπ, and n is an integer.

[0192] In the embodiment of the present application, S_1 and S_2 are superimposed at the first end of the first impedance conversion circuit 150_1, and the signal amplitude is enhanced, so that the gain of the amplifier of the embodiment of the present application is greater than that of a single common source amplifier or source follower amplifier. In an ideal state, when N=1, the gain of the amplifier of the embodiment of the present application is twice that of a single common source amplifier or source follower amplifier.

[0193] In addition, in the embodiment of the present application, by adjusting the first branch 112_1 of the drain matching circuit 112 and the first branch 113_1 of the source matching circuit 113, optimization for gain, power and noise can also be achieved.

[0194] In the embodiment of the present application, the first amplified signal S_1 and the second amplified signal S_2 can also be synthesized by a synthesis circuit. As shown in FIG. 7, the first amplified signal S_1 and the second amplified signal S_2 are synthesized, which comprises: Figure 25

[0195] The first radio frequency signal output end RFOUT_1 is connected to the first end of the first synthesis circuit 170_1, the second radio frequency signal output end RFOUT_2 is connected to the second end of the first synthesis circuit 170_1, and the first synthesis circuit 170_1 is used to synthesize the first amplified signal S_1 and the second amplified signal S_2.

[0196] The amplifier further comprises a first impedance conversion circuit 150_1, the first end of the first impedance conversion circuit 150_1 is connected to the third end of the first synthesis circuit 170_1, the second end of the first impedance conversion circuit 150_1 is connected to the third radio frequency signal output end RFOUT_3, and the first impedance conversion circuit 150_1 is used to convert the synthesis impedance of the third end of the first synthesis circuit 170_1 to the output impedance of the amplifier.

[0197] In the embodiment of the present application, the first synthesis circuit 170_1 can be a coupler, or can be a synthesizer with a phase shift function, or can be other circuits that can synthesize radio frequency signals. ​

[0198] The first synthesis circuit 170_1 can synthesize the first amplified signal S_1 and the second amplified signal S_2 after phase shifting, and make the output signal enter the first impedance conversion circuit 150_1.

[0199] The first synthesis circuit 170_1 can synthesize the first amplified signal S_1 and the second amplified signal S_2 after phase shifting, and make the output signal enter the first impedance conversion circuit 150_1.

[0200] As described in the above embodiment, the purpose of phase shifting of the first amplified signal S_1 and / or the second amplified signal S_2 by the first synthesis circuit 170_1 is to make the phase difference of the two signals 2nπ, where n is an integer, so that the two amplified signals can be synthesized with amplitude superposition, and the amplifier has higher gain.

[0201] In the embodiment of the application, the first synthesis circuit 170_1 can be split into two sub-circuits, both of which can realize phase shifting of the radio frequency signal, and the two sub-circuits are integrated with the first branch 112_1 of the drain matching circuit 112 and the first branch 113_1 of the source matching circuit 113 respectively, to realize phase shifting of the first amplified signal S_1 and / or the second amplified signal S_2, and the first amplified signal S_1 and the second amplified signal S_2 after phase shifting are directly synthesized; or, the first synthesis circuit 170_1 can be integrated with the first impedance conversion circuit 150_1, and the first amplified signal S_1 and / or the second amplified signal S_2 are phase shifted and synthesized in the first impedance conversion circuit 150_1. The above two specific embodiments can be equivalent to the circuit shown in the following formula. Figure 24

[0202] In the embodiment of the application, as shown in the following formula, Figures 30-35 is a schematic diagram of the circuit of the amplifier for synthesizing the first amplified signal S_1 and the second amplified signal S_2. Among them, Figure 30 and Figure 31 are three-bias amplifiers, which synthesize two amplified signals, and output the synthesized amplified signal through the first impedance conversion circuit 150_1 and the third radio frequency signal output end RFOUT_3; Figure 32 and Figure 33 are double-bias amplifiers, which synthesize two amplified signals, and output the synthesized amplified signal through the first impedance conversion circuit 150_1 and the third radio frequency signal output end RFOUT_3; Figure 34 and Figure 35 are single-bias amplifiers, which synthesize two amplified signals, and output the synthesized amplified signal through the first impedance conversion circuit 150_1 and the third radio frequency signal output end RFOUT_3.

[0203] ​Figures 30-35 The structures and functions of other circuits in the amplifier, such as the first drain bias circuit 120_1, the first source bias circuit 140_1, the gate matching circuit 130, the gate bias circuit 160, and the like, are the same as those in the above embodiment, and are not described here again.

[0204] In the embodiment of the present application, only one three-port transistor is included in the amplifier, and the power consumption of the three-port transistor determines the power consumption of the amplifier. Therefore, the amplifier of the embodiment of the present application realizes the gain superposition of two amplifiers without doubling the power consumption, thereby improving the gain-to-power ratio of the amplifier. That is, the power consumption of the amplifier of the embodiment of the present application is only comparable to that of one common-source amplifier or one source follower amplifier, but the gain is greater, and therefore the gain-to-power ratio is greater.

[0205] In the prior art, if two amplifiers are simply combined, that is, two amplifiers amplify and output the same input signal at the same time and then directly superimpose, since the two amplifiers each include one three-port transistor, the power consumption of the combined circuit is also doubled. The amplifier of the embodiment of the present application enables the gain superposition of the amplifiers, but since only one three-port transistor is used, the power consumption is not doubled, thereby improving the power-to-power ratio of the amplifier. That is, the gain of the embodiment of the present application is comparable to that of the signal amplified by the two amplifiers simply combined and then superimposed, but the power consumption is only half of that of the combined amplifier, and therefore the gain-to-power ratio is greater.

[0206] In other embodiments of the present application, the three-port transistor 111 can be a triode 1112, so that the first pole of the transistor 111 is the collector pole (C pole), the second pole is the emitter pole (E pole), and the third pole is the base pole (B pole).

[0207] Figure 36 The circuit shown is an application scenario for N = 1, at this time, the first pole matching circuit 112_1 of the amplifier is the collector pole matching circuit 112_1, the second pole matching circuit 113_1 is the emitter pole matching circuit 113_1, the first first pole bias circuit 120_1 is the first collector pole bias circuit 120_1, the first second pole bias circuit 140_1 is the first emitter pole bias circuit 140_1, the third pole bias circuit 160 is the base pole bias circuit 160, and the amplifier further includes an impedance conversion circuit 150.

[0208] As shown in FIG. 1, the amplifier can be decomposed into two amplifiers, one common emitter amplifier and one source follower amplifier, based on the amplification principle of the triode 1112 radio frequency signal. Figure 36

[0209] ​Single power supply can be provided by the collector bias power supply end VC for the collector voltage VC, the collector bias power supply end VC provides the current mirror power supply voltage, the current mirror generates the base bias current IB, the emitter bias power supply end VE is grounded, the collector voltage VC and the base current IB together provide bias for the transistor; or is supplied by the emitter bias power supply end VE (negative voltage), the emitter bias power supply end VE supplies power for the current mirror, the current mirror generates the base current IB, VE and IB together provide bias for the transistor (VE and IB are not shown in the figure).

[0210] Dual power supply can be provided by the collector bias power supply end VC for the collector voltage VC, the base bias power supply end IB provides the base current IB for the base (IB is not shown in the figure).

[0211] Three power supply is provided by the collector bias power supply end VC for the collector voltage VC, the emitter bias power supply end VE provides the emitter voltage VE, and the base bias power supply end IB provides the base current IB for the base (VE and IB are not shown in the figure).

[0212] When the amplifier uses the transistor 1112, the synthesis of the amplified signal can be direct synthesis; or can use a synthesis circuit to synthesize, which will not be described here.

[0213] When the amplifier uses the transistor 1112, its working principle, circuit composition mode, and beneficial effects are the same as or similar to the above-mentioned embodiments, but part of the circuit can be adjusted according to the actual application scene, which will not be described here.

[0214] As described above, the amplifier of the embodiment of the application uses the transistor 1112 to amplify the radio frequency input signal in two ways, that is, to realize two-way amplification of the radio frequency signal through the common emitter amplifier and the emitter follower amplifier; in addition, the amplifier of the embodiment of the application also synthesizes the signals amplified in two ways, so that the signal amplitude of the amplifier is superimposed, and the amplifier has higher gain.

[0215] As described above, by the same reason, when N is an integer greater than or equal to 1, the amplifier of the present application includes a three-port transistor, and the first pole matching circuit includes N branches, and the second pole matching circuit also includes N branches, and 2N amplified signals can be output respectively, one amplified signal output through the first pole matching circuit and one amplified signal output through the second pole matching circuit are synthesized, thus N synthesized amplified signals can be output, and the functional density of the amplifier is improved; in addition, the amplifier gain can be stacked, and the amplifier has higher gain; in the embodiment of the present application, only one three-port transistor is included in the amplifier, and the power consumption of the three-port transistor determines the power consumption of the amplifier, thus the amplifier of the embodiment of the present application realizes the gain stacking of the multi-channel amplifier without doubling the power consumption, thereby improving the power consumption ratio of the amplifier.

[0216] The embodiment of the present application provides an amplifier and a radio frequency chip, the amplifier includes a substrate, and the amplifier as described above on the substrate.

[0217] The chip as described above can realize multi-channel amplification of radio frequency signals, which will not be described here again.

[0218] The chip as described above can realize multi-channel amplification of radio frequency signals and synthesis of amplified signals, which will not be described here again.

[0219] The chip as described above is still taken as an example of N = 1 and a field effect transistor. In the first branch 112_1 of the first pole matching circuit 112, the first branch 113_1 of the second pole matching circuit 113 and the third pole matching circuit 130, no low-coupling inductor pair can be included; or at least one pair is a low-coupling inductor pair, for example, any one of the low-coupling inductor pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch, the low-coupling inductor pair composed of the fourth inductor L4_1 and the fifth inductor L5_1 of the first branch, the low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7, or any two pairs thereof, or three pairs thereof, and the specific structure is described in the above embodiment, which will not be described here again.

[0220] In the embodiment of the present application, the inductors in the low-coupling inductor pair can be single-layer wiring spiral inductors or multi-layer wiring spiral inductors.

[0221] When the inductor is excited by a signal, an induced magnetic field is generated, the induced magnetic field generates an induced electric field, and the induced electric field generates an induced eddy current in the substrate of the chip, thereby generating energy loss.

[0222] The chip in this application embodiment includes the aforementioned amplifier. The amplifier may include a low-coupling inductor pair, for example, the first inductor L1_1 and the second inductor L2_1 of the first branch are a low-coupling inductor pair. The induced magnetic fields on the first inductor L1_1 and the second inductor L2_1 of the first branch are in opposite directions, so that the induced electric field generated by the induced magnetic field of the first inductor L1_1 and the induced electric field generated by the induced magnetic field of the second inductor L2_1 of the first branch are also in opposite directions. The induced eddy currents generated by the two opposite induced electric fields are in opposite directions. The induced eddy currents in opposite directions can partially cancel each other out, thereby reducing the induced eddy currents and reducing the energy loss, thus reducing the energy loss of the chip matching network.

[0223] In this embodiment, in the first branch 112_1 of the drain matching circuit 112 of the amplifier circuit in the chip, the induced magnetic fields of the first inductor L1_1 and the second inductor L2_1 of the first branch are in opposite directions, which can cancel out the induced eddy currents in the substrate and reduce energy loss. Furthermore, the physical distance between the first inductor L1_1 and the second inductor L2_1 of the first branch can be closer, and the physical distance between the low-coupling inductor pair and other devices can also be closer, thereby reducing the chip size and cost.

[0224] In the chip of this application embodiment, the effect of the low-coupling inductor pair composed of other inductor pairs with opposite induced magnetic fields is as described above, and will not be repeated here.

[0225] like Figure 37 As shown, the RF chip 2000 may include an amplifier 2001, wherein the amplifier 2001 may be any embodiment of the amplifier described above. A single amplifier 2001 may be used, or multiple amplifiers 2001 may be combined. In one example, the RF chip 2000 may include one or more amplifiers 2001.

[0226] In embodiments of the amplifier and the RF chip employing a low-coupling inductor pair, the layout of the low-coupling inductor pair greatly affects the size of the circuit. When an inductor is excited by a signal, an induced magnetic field is generated, which in turn generates an induced electric field, which in turn generates radiation, resulting in energy loss. For example, the induced electric field generates eddy current in the medium of the circuit, and electromagnetic radiation in the space. If two inductors are placed close to each other, they will be mutually coupled, which will exacerbate such loss. Embodiments of the present application at least partially reduce the mutual coupling between the two inductors of the low-coupling inductor pair by configuring the two inductors to generate induced magnetic fields in opposite directions, so that the induced electric fields caused by the induced magnetic fields of the two inductors are also in opposite directions, thereby partially or completely canceling out, thereby reducing or eliminating the energy loss caused by the induced electric field, so that the two inductors of the low-coupling inductor pair can be placed closer to each other to further reduce the chip area occupied by the amplifier.

[0227] For example, the first inductor L1_1 of the first branch and the second inductor L2_1 of the first branch of the low-coupling inductor pair can be configured to be adjacent to each other and such that the induced magnetic field generated by the first inductor L1_1 of the first branch is in the opposite direction of the induced magnetic field generated by the second inductor L2_1 of the first branch.

[0228] In one example, the first inductor L1_1 of the first branch and the second inductor L2_1 of the first branch are both spiral inductors, and they can be arranged in the amplifier with opposite spiral directions. For example, one inductor has a clockwise spiral direction, and the other has a counterclockwise spiral direction.

[0229] In one example, the first inductor L1_1 of the first branch and the second inductor L2_1 of the first branch are arranged in the amplifier as mirror images of each other.

[0230] Figure 38 A schematic diagram of the layout of the low-coupling inductor pair in the amplifier according to an embodiment of the present application is shown. Figure 38 A schematic diagram of the low-coupling inductor pair of the amplifier is shown from the direction perpendicular to the wiring layer of the amplifier. In one example, the amplifier can be an RF chip.

[0231] As Figure 38As shown, the low coupling inductor includes two inductors, each of which is composed of the first microstrip line 1314 and the second microstrip line 1315, and the first microstrip line 1314 is wound into the first spiral pattern W1 and the second microstrip line 1315 is wound into the second spiral pattern W2. The first end 1311 and the second end 1312 of the first microstrip line 1314 are respectively the first end and the second end of the first inductor L1_1 of the first branch. The first end 1313 and the second end 1312 of the second microstrip line 1315 are respectively the first end and the second end of the second inductor L2_1 of the first branch. The second end 1312 of the first microstrip line 1314 and the second end 1312 of the second microstrip line 1315 are connected together to form the common end 1312 of the first inductor L1_1 and the second inductor L2_1 of the first branch, and the first microstrip line 1314 and the second microstrip line 1315 form a combined microstrip line. The first end 1311 of the first inductor L1_1, the first end 1313 of the second inductor L2_1, and the second end 1312 of the first inductor L1_1 and the second inductor L2_1 of the first branch are respectively connected to other parts of the amplifier through the connecting lines.

[0232] The combined microstrip line (the first microstrip line / second microstrip line) of the embodiment of the present application can be composed of single-layer or multi-layer metal materials. In one example, the combined microstrip line is composed of multi-layer metal materials, each of which is located in a different wiring layer of the amplifier. The multi-layer metal materials located in different wiring layers are superimposed together to form the combined microstrip line, and are connected through interlayer vias between the metal materials. In another example, the combined microstrip line is composed of single-layer metal materials, which can be located in the same or different wiring layers of the amplifier. For example, part of the single-layer metal materials is located in a wiring layer, and the other part is located in one or more different wiring layers. Similarly, the single-layer metal materials located in different wiring layers are connected through vias.

[0233] In Figure 38 the example, both spiral patterns W1 and W2 include multiple turns, and it can be understood that they can also each include one turn, or one includes multiple turns and the other includes multiple turns.

[0234] As an example, the first microstrip line 1314 and the second microstrip line 1315 can be wound in opposite directions, such that the helical directions of the first helical pattern W1 and the second helical pattern W2 are opposite. This results in the induced magnetic fields caused by the currents in the microstrip lines forming the two helical patterns W1 and W2 being in opposite directions when the low-coupling inductor pair is in operation. For example, one of W1 and W2 can be helical in a counter-clockwise direction, and the other in a clockwise direction. Here, the direction from the first end of the first inductor L1_1 or the second inductor L2_1 of the first branch to the common end can be called the helical direction, or the direction from the common end to the first end of the first inductor L1_1 or the second inductor L2_1 of the first branch can also be called the helical direction.

[0235] exist Figure 38 In this embodiment, the first microstrip line 1314 is wound from the first end 1311 to the common end 1312 in a counterclockwise direction, forming a first spiral pattern W1, from the inside out (inner turns first, then outer turns). Similarly, the second microstrip line 1315 is wound from the first end 1313 to the common end 1312 in a clockwise direction, forming a second spiral pattern W2, from the inside out (inner turns first, then outer turns). It is understood that one can be wound from the inside out and the other from the outside in (outer turns first, then inner turns), or both can be wound from the outside in. It is also understood that when winding the microstrip lines into spiral patterns W1 or W2, it is not necessary to always wind them in an inside-out or outside-in direction; the direction can be changed once or multiple times. For example, it can start from the inside out and then change to the outside in, or vice versa.

[0236] In summary, each spiral pattern in W1 and W2 can wind the microstrip line from its respective first end to the common end in one of the following ways:

[0237] From the inside out;

[0238] From the outside in;

[0239] The combination of the two above.

[0240] exist Figure 38 In one embodiment, the two spiral patterns W1 and W2 do not overlap and are adjacent but spaced a certain distance D in a direction parallel to the amplifier's wiring layer. In this embodiment, as described above, due to the low mutual coupling between the two inductors, the two spiral patterns W1 and W2 can be arranged as close as possible (but without overlapping), thereby reducing circuit size and cost. In one example, the spacing between the two spiral patterns W1 and W2 (e.g., ...) Figure 38The minimum distance D) shown can be about 3 microns. The "distance between the two spiral patterns" as used herein refers to the distance between the closest microstrip lines of the two spiral patterns. As shown in Figure 38 The distance D is the distance between the outermost turns of W1 and W2. In practice, the minimum distance between the two spiral patterns is determined by the chip manufacturing process.

[0241] In the example shown in Figure 38 , the length of the first microstrip line 1314 is equal to the length of the second microstrip line 1315. That is, the common end 1312 is located at the midpoint of the merged microstrip line. It can be appreciated that the common end 1312 can also be located at other positions, such as a position closer to W1 or W2.

[0242] As shown in Figure 38 , in this embodiment, the spiral patterns W1 and W2 are arranged in mirror image, that is, mirror image patterns, which are shown in Figure 38 as arranged in axial symmetry. That is, the spiral patterns W1 and W2 have the same configuration, such as the same number of turns, microstrip line width, and distance between adjacent turns, etc., except that their patterns are opposite (the winding direction is opposite), and the two are symmetrically / mirror image about a plane perpendicular to the wiring layer located between the two. W1 and W2 can also not be arranged in mirror image, for example, W1 and W2 have different configurations, such as W1 and W2 have different numbers of turns, microstrip line widths, or distances between adjacent turns, etc., as long as the inductive magnetic field directions of the spiral patterns W1 and W2 wound are opposite.

[0243] It can be appreciated that Figure 38 the arrangement of the first spiral pattern W1 and the second spiral pattern W2 in

[0244] In the low-coupling inductor pair according to the above-described embodiments of the present application, the microstrip lines of the two inductors have a common end and are arranged as two spiral patterns with opposite spiral directions. When an excitation signal is applied to the low-coupling inductor pair in the working state, the excitation signal is split at the common end to the two spirals (microstrip lines of the two inductors), so that the directions of the inductive magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing the mutual coupling / mutual inductance between the two inductors.

[0245] In the above-described inductor pair embodiments, as Figure 39As shown, the inductive pair is arranged in the integrated circuit chip to have three terminals: a common terminal 1312, a head terminal 1311 as a first branch terminal of the inductive pair, and a tail terminal 1313 as a second branch terminal of the inductive pair. As mentioned before, the three terminals of the inductive pair can be connected to an excitation signal or other circuit parts through leads. For example, a radio frequency excitation signal can be accessed from the common terminal 1312 of the inductive pair, and the radio frequency excitation signal is split into two branches at the common terminal 1312 to the first spiral pattern W1 of the first branch terminal (head terminal) 1311 and to the second spiral pattern W2 of the second branch terminal (tail terminal) 1313. Assuming that the excitation signal accessed at the common terminal 1312 is i com = I com · sin ωt. The excitation signal is split into two branches at the common terminal 1312, one branch flows through the common terminal 1312 to the first spiral pattern W1 of the first branch terminal (head terminal) 1311, and the other branch flows through the common terminal 1312 to the second spiral pattern W2 of the second branch terminal (tail terminal) 1313. Assuming that the excitation signal in the first spiral pattern W1 is i1(t), and the excitation signal in the second spiral pattern W2 is i2(t), if there is no reflection, then i1(t) + i2(t) = I com · sin ωt. If the common terminal is located at the midpoint of the merged microstrip line, and W1 and W2 are patterns with axial symmetry, then at any time, the excitation signals in W1 and W2 are exactly the same, i.e. The excitation signals i1(t) and i2(t) in the inductive pair are periodic signals, and the current amplitudes change periodically and non-uniformly, so the induced magnetic fields generated are also periodic and non-uniformly changing; the changing magnetic fields in turn generate electric fields, thereby generating electromagnetic waves. In the case where the excitation signals in W1 and W2 are exactly the same, since the spiral directions of W1 and W2 are opposite, at any time, the induced magnetic field generated by W1 is the same in size as the induced magnetic field generated by W2, but the directions are opposite, and the corresponding induced electric fields also have opposite directions and change direction periodically. Therefore, the induced magnetic fields generated by W1 and W2 will almost completely cancel out in many areas, and will partially cancel out in some areas, so the corresponding electric fields or electromagnetic waves caused by the induced magnetic fields will also be partially canceled out, thereby reducing the loss of the inductive pair.

[0246] If the common terminal is not located at the midpoint of the merged microstrip line, or W1 and W2 are patterns with different configurations, it may not be possible to guarantee that the excitation signals in W1 and W2 are exactly the same, so the degree of mutual cancellation of the induced magnetic fields of W1 and W2 is weakened compared to the case where the excitation signals in W1 and W2 are exactly the same, but at any time, the induced magnetic fields generated by W1 and W2 will still partially cancel each other out, weakening the electromagnetic radiation intensity, thereby reducing the loss of the inductive pair to some extent.

[0247] It should be noted that, theoretically, the inductive pair with three ports (a common port, a first branch port being the first end of the merged microstrip line, and a second branch port being the second end of the merged microstrip line) as described above is a passive lossless network, and since a passive network has reciprocity, the loss and transmission characteristics of the inductive pair are reciprocal regardless of the input of the excitation signal from which port of the three ports.

[0248] The low-coupling inductive pair composed of the first inductor L1_1 and the second inductor L2_1 of the first branch in the amplifier can adopt the low-coupling inductive pair arrangement as described above. The above description of the low-coupling inductive pair applies to all the low-coupling inductive pairs involved herein, and for the sake of brevity, will not be repeated hereinafter.

[0249] In each of the above-described amplifier embodiments, the low-coupling inductive pair as described above is used, which makes the amplifier of the present application have the following advantages: by configuring the two inductors that constitute the inductive pair such that the directions of their respective induced magnetic fields are opposite, the inductive pair is a low-coupling inductive pair, which can reduce the loss of the amplifier input matching circuit. In addition, since the coupling between the two inductors that constitute the low-coupling inductive pair and the radiation range of the induced electric field and the induced magnetic field of the inductors can be reduced in this way, the inductors and other components can be arranged closer together, further reducing the size of the circuit.

[0250] The embodiments of the present application also provide an electronic device, which comprises the radio frequency chip described above, and the radio frequency chip comprising the amplifier embodiments of the present application can be used in the electronic device.

[0251] As shown in Figure 37 , the electronic device 3000 comprises the radio frequency chip 2000 as shown in ​ . The electronic device 3000 can be a wireless device or any other electronic device that can use an amplifier.

[0252] The wireless device can be a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device can also be a cellular phone, a smartphone, a tablet computer, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. The wireless device can be capable of communicating with a wireless communication system, and can also be capable of receiving signals from a broadcast station, from one or more satellites, etc. The wireless device can support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

[0253] The embodiment of the present application provides an amplifier, a radio frequency chip and an electronic device, the amplifier comprises a three-port transistor, and further comprises a first pole matching circuit and a second pole matching circuit, wherein the first pole matching circuit comprises N branches, and the second pole matching circuit also comprises N branches. Each branch of the first pole matching circuit and the three-port transistor can constitute an amplification link, and N amplified signals are output; each branch of the second pole matching circuit and the three-port transistor can also constitute an amplification link, and N amplified signals are output, so that the amplifier can output 2N amplified signals. In the embodiment of the present application, one amplified signal output by the first pole matching circuit and one amplified signal output by the second pole matching circuit are synthesized, N synthesized amplified signals can be output, and the functional density of the amplifier is improved; in addition, the amplifier gain is superimposed, and the amplifier has higher gain. In the embodiment of the present application, only one three-port transistor is included in the amplifier, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the amplifier of the embodiment of the present application realizes the gain superposition of the multi-path amplifier without the power consumption being multiplied, thereby improving the power consumption ratio of the amplifier.

[0254] In the embodiment of the present application, function units with the same or similar functions in the same figure have the same or similar functions, which will not be described here.

[0255] The amplifier in the embodiment of the present application can be independently used, or can be used in multiple levels in cascade, or can be used in cascade with other circuits with various functions; the radio frequency chip in the embodiment of the present application can comprise an amplifier used independently, or can comprise a plurality of amplifiers used in combination, or can comprise a plurality of amplifiers used independently; the radio frequency chip in the embodiment of the present application can be independently used, or can be used in multiple levels in combination, or can be used in combination with other chips / circuits with various functions.

[0256] In the embodiment of the present application, the bias circuit of each pole of the three-port transistor comprises a plurality of implementation forms, which can also be applied to other circuits, or can be combined with other implementation forms, or combined with each other, which will not be described here.

[0257] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for easy distinction from each other, and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the context, which will not be repeated here.

[0258] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description in other embodiments.

[0259] The units or modules described as separate components can or can not be physically separated, and the components shown as units or modules can or can not be physical units, which can be located in one place or distributed to multiple functional units. Part or all of the units or modules can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0260] In addition, each functional unit or module in each embodiment of the present application can be integrated in one chip unit, or each unit or module can exist physically, or two or more units or modules can be integrated in one unit.

[0261] It should be noted that, in this paper, relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "include", "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the sentence "including a…" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0262] The foregoing detailed description of the application has been presented for purposes of illustration and description. Various modifications and changes can be made to these embodiments without departing from the spirit and scope of the application. It is intended that the scope of the application should not be limited by the particular representative embodiments described above.

Claims

1. An amplifier characterized by, The amplifier comprises: a three-port transistor comprising a first pole, a second pole and a third pole, the three-port transistor being configured to receive a to-be-amplified radio frequency signal from the third pole of the three-port transistor, amplify the to-be-amplified radio frequency signal, and output an in-phase amplified signal from the second pole of the three-port transistor and an anti-phase amplified signal from the first pole of the three-port transistor; a first pole matching circuit comprising N branches, a first end of a jth branch of the first pole matching circuit being connected to the first pole of the three-port transistor, and a second end of the jth branch of the first pole matching circuit being connected to a jth radio frequency signal output end, the jth branch of the first pole matching circuit being configured to match an impedance of the first pole of the three-port transistor to a jth target impedance, the jth target impedance being an output impedance of the jth radio frequency signal output end, and the jth branch of the first pole matching circuit being further configured to transmit the anti-phase amplified signal to the jth radio frequency signal output end as a jth amplified signal; a second pole matching circuit comprising N branches, a first end of a jth branch of the second pole matching circuit being connected to the second pole of the three-port transistor, and a second end of the jth branch of the second pole matching circuit being connected to an N+jth radio frequency signal output end, the jth branch of the second pole matching circuit being configured to match an impedance of the second pole of the three-port transistor to an N+jth target impedance, the N+jth target impedance being an output impedance of the N+jth radio frequency signal output end, and the jth branch of the second pole matching circuit being further configured to transmit the in-phase amplified signal to the N+jth radio frequency signal output end as an N+jth amplified signal; wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1; the jth amplified signal and the N+jth amplified signal are combined; wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1; the jth amplified signal and the N+jth amplified signal are combined, comprising: the jth radio frequency signal output end is connected to the N+jth radio frequency signal output end; wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1; the amplifier further comprises N combining circuits, the jth amplified signal and the N+jth amplified signal are combined, comprising: the jth radio frequency signal output end is connected to a first end of a jth combining circuit, and the N+jth radio frequency signal output end is connected to a second end of the jth combining circuit, so that the jth amplified signal and the N+jth amplified signal are combined; wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

2. The amplifier of claim 1, wherein The amplifier further comprises: N impedance conversion circuits, wherein a first end of a jth impedance conversion circuit is connected to the jth radio frequency signal output end, and a second end of the jth impedance conversion circuit is connected to a 2N+jth radio frequency signal output end; wherein j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

3. The amplifier of claim 1, wherein, The amplifier further comprises: N impedance conversion circuits, A first end of the jth impedance conversion circuit is connected to a third end of the jth combining circuit, and a second end of the jth impedance conversion circuit is connected to a 2N+jth radio frequency signal output end; Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

4. The amplifier of claim 1, wherein, The amplifier further comprises: A third pole matching circuit, a first end of the third pole matching circuit being connected to a radio frequency signal input end, and a second end of the third pole matching circuit being connected to a third pole of the three-port transistor; A third pole biasing circuit, the third pole biasing circuit being connected to a third end of the third pole matching circuit; N first pole biasing circuits, a first end of the jth first pole biasing circuit being connected to a jth first pole biasing power supply end; N second pole biasing circuits, a first end of the jth second pole biasing circuit being connected to a third end of the jth branch of the second pole matching circuit; Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

5. The amplifier of claim 1, wherein, The first pole matching circuit jth branch comprises: A jth branch first inductive unit, a second end of the jth branch first inductive unit being connected to a first pole of the three-port transistor; A jth branch second inductive unit, a first end of the jth branch second inductive unit being connected to a jth first pole biasing power supply end, and a second end of the jth branch second inductive unit being connected to a first end of the jth branch first inductive unit; A jth branch third inductive unit, a first end of the jth branch third inductive unit being connected to the first end of the jth branch first inductive unit, and a second end of the jth branch third inductive unit being connected to the jth radio frequency signal output end; Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1. The second pole matching circuit jth branch comprises:

6. The amplifier of claim 5, wherein, A jth branch fourth inductive unit, a first end of the jth branch fourth inductive unit being connected to a second pole of the three-port transistor; A jth branch fifth inductive unit, a first end of the jth branch fifth inductive unit being connected to a second end of the jth branch fourth inductive unit; A jth branch first capacitor, a first end of the jth branch first capacitor being connected to the second end of the jth branch fourth inductive unit, and a second end of the jth branch first capacitor being connected to a N+jth radio frequency signal output end; Wherein, j=1…N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1. The third pole matching circuit comprises:

7. The amplifier of claim 4, wherein, A sixth inductive unit, a first end of the sixth inductive unit being connected to a third pole of the three-port transistor; A seventh inductive unit, a first end of the seventh inductive unit being connected to a second end of the sixth inductive unit, and a second end of the seventh inductive unit being connected to the third pole biasing circuit; A second capacitor, a first end of the second capacitor being connected to the radio frequency signal input end, and a second end of the second capacitor being connected to the second end of the sixth inductive unit.

8. The amplifier of claim 7, the jth branch first inductive unit and the jth branch second inductive unit being a pair of inductors with opposite magnetic fields; and / or ​ The jth branch fourth inductive unit and the jth branch fifth inductive unit are an inductive pair with opposite induced magnetic fields; and / or The sixth inductive unit and the seventh inductive unit are an inductive pair with opposite induced magnetic fields. wherein, j=1……N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

9. The amplifier of claim 7, wherein, The third pole bias circuit comprises: A third capacitor, a first end of the third capacitor being grounded, a second end of the third capacitor being connected with a second end of the seventh inductive unit, and the second end of the third capacitor also being connected with a third pole bias power supply end.

10. The amplifier of claim 9, wherein, The jth second pole bias circuit comprises: A jth fourth capacitor, a first end of the jth fourth capacitor being connected with a second end of the jth branch fifth inductive unit, the first end of the jth fourth capacitor also being connected with a jth second pole bias power supply end, and a second end of the jth fourth capacitor being grounded; Wherein, j=1……N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

11. The amplifier of claim 9, wherein, The jth second pole bias circuit is grounded. Wherein, j=1……N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

12. The amplifier of claim 7, wherein, The third pole bias circuit is grounded.

13. The amplifier of claim 12, wherein, The jth second pole bias circuit comprises: A jth sixth capacitor, a first end of the jth sixth capacitor being connected with a second end of the jth branch fifth inductive unit, and a second end of the jth sixth capacitor being grounded; A jth first resistor, a first end of the jth first resistor being connected with a second end of the jth branch fifth inductive unit, and a second end of the jth first resistor being grounded; Wherein, j=1……N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

14. The amplifier of claim 4, wherein, The jth first pole bias circuit comprises: A jth seventh capacitor, a first end of the jth seventh capacitor being grounded, and a second end of the jth seventh capacitor being connected with a jth first pole bias power supply end; Wherein, j=1……N, j is an integer greater than or equal to 1, and N is an integer greater than or equal to 1.

15. A radio frequency chip, comprising: The radio frequency chip comprises a substrate and an amplifier as claimed in any one of claims 1 to 14 on the substrate.

16. An electronic device, comprising: The radio frequency chip as claimed in claim 15 is included. The radio frequency chip as claimed in claim 15 is included.

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