Timing signal generator

Abstract

A timing signal generator includes a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a timing signal synthesizer, and a time difference extractor. The first current source is configured to generate a first current according to an input voltage. The first switch includes a control terminal configured to receive a charging signal. The second current source is configured to generate a second current according to the input voltage. The second switch includes a control terminal configured to receive a time difference signal. The third switch includes a control terminal configured to receive a reset signal. The capacitor is coupled between a charging terminal and a ground terminal. The signal synthesizer is configured to generate a timing signal according to the charging voltage and a reference voltage. The time difference extractor is configured to generate the time difference signal according to the timing signal and a time difference timing signal.

Description

Technical Field

[0001] This invention relates to a timing signal generator, and more particularly to a timing signal generator capable of correcting the pulse width of a timing signal. Background Technology

[0002] In analog circuits, the value of an analog signal can change continuously, with almost no limitations on time or amplitude; it can essentially take any real value, and the input and output exhibit linear changes. Therefore, voltage and current can be directly used to control objects in analog circuits, such as volume control in household appliances or brightness control in halogen bulb lighting fixtures. However, analog circuits have many problems, such as control signals being prone to drift over time, difficulty in adjustment, high power consumption, and susceptibility to noise and environmental interference.

[0003] Unlike analog circuits, digital circuits take values ​​within a predetermined range. At any given time, their output can only be in either ON or OFF state. Therefore, voltage or current is applied to analog loads using repetitive pulse sequences with both open and closed circuits. A timing signal generator is a circuit used to generate precise clock signals with adjustable timing, providing the "heartbeat" signal needed for the operation of various digital circuits. It is widely used in electronic instruments and chip systems, such as chip testers, pulse width modulation generators, logic analyzers, oscilloscopes, and time-to-digital converters. For example, in a personal computer system, each system uses one or two clock generators to provide more than ten sets of reference signals to control and regulate processing speed, memory access, streaming media, network transmission, and wireless communication. The applications of timing signal generators have now extended beyond computers, providing reference clock timing for the vast majority of electronic devices, from central office telecommunications switches to home video game consoles and digital cameras.

[0004] With advancements in integrated circuit technology, timing signal generators can be integrated with other analog and digital circuits onto the same chip. However, after the timing signal generated by the timing signal generator passes through external circuits, the timing signal may experience delays or distortions due to various circuit operation effects, causing the pulse width of the timing signal to differ from the preset value. Modern high-speed circuits operate on the nanosecond scale, and delays or distortions in the timing signal can lead to asynchrony within the chip's internal circuitry and subsequently cause other errors. Summary of the Invention

[0005] This embodiment provides a timing signal generator, comprising a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a timing signal synthesizer, and a time difference extractor. The first current source generates a first current based on an input voltage. The first switch includes a first terminal coupled to the first current source, a second terminal coupled to a charging terminal, and a control terminal for receiving a charging signal. The second current source generates a second current based on the input voltage. The second switch includes a first terminal coupled to the second current source, a second terminal coupled to the charging terminal, and a control terminal for receiving a time difference signal. The third switch includes a first terminal coupled to the charging terminal, a second terminal coupled to a ground terminal, and a control terminal for receiving a reset signal. A capacitor is coupled between the charging terminal and the ground terminal. The signal synthesizer is coupled to the charging terminal and generates a timing signal based on the charging voltage and a reference voltage. The time difference extractor is coupled to the control terminal of the signal synthesizer and the second switch and generates a time difference signal based on the timing signal and the time difference timing signal.

[0006] An embodiment provides another timing signal generator, comprising a first current source, a first switch, a second switch, a second current source, a third switch, a fourth switch, a first capacitor, a second capacitor, a timing signal synthesizer, and a time difference extractor. The first current source generates a first current based on an input voltage. The first switch includes a first terminal coupled to the first current source, a second terminal coupled to a charging terminal, and a control terminal for receiving a charging signal. The second switch includes a first terminal coupled to a bias terminal, a second terminal, and a control terminal for receiving a time difference signal. The second current source is coupled to the second terminal of the second switch to generate a second current based on the input voltage. The third switch includes a first terminal coupled to the charging terminal, a second terminal coupled to a ground terminal, and a control terminal for receiving a reset signal. The fourth switch includes a first terminal and a second terminal coupled to a bias terminal, and a control terminal for receiving a reset signal. The first capacitor is coupled between the charging terminal and the ground terminal. The second capacitor is coupled to the bias terminal and is used to receive a reference voltage. The signal synthesizer is coupled to the charging terminal and generates a timing signal based on the charging voltage and the offset reference voltage. The time difference extractor is coupled to the control terminal of the signal synthesizer and the second switch to generate a time difference signal based on the timing signal and the time difference timing signal. Attached Figure Description

[0007] Figure 1 is a schematic diagram of the timing signal generator in the embodiment.

[0008] Figure 2 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 1.

[0009] Figure 3 is a schematic diagram of a timing signal generator according to another embodiment.

[0010] Figure 4 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 3.

[0011] Figure 5 is a schematic diagram of a timing signal generator according to another embodiment.

[0012] Figure 6 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 5.

[0013] Figure 7 is a schematic diagram of a timing signal generator according to another embodiment.

[0014] Figure 8 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 7.

[0015] Figure 9 is a schematic diagram of a timing signal generator according to another embodiment.

[0016] Figure 10 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 9.

[0017] Figure 11 is a schematic diagram of a timing signal generator according to another embodiment.

[0018] Figure 12 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 11.

[0019] Figure 13 is a schematic diagram of a timing signal generator according to another embodiment.

[0020] Figure 14 is a timing diagram of the operation signals of the timing signal generator in the embodiment of Figure 13. Detailed Implementation

[0021] The architecture, number of components, number of layers, positional distribution, and proportions shown in the illustrations are merely examples to aid in understanding the embodiments and are not intended to limit the form and scope of the embodiments. The use of ordinal numbers such as "first," "second," etc., in this document is solely for distinguishing different components and does not limit their order or importance.

[0022] Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the specification and claims, words such as "having" and "comprising" are open-ended terms and should therefore be interpreted as "including but not limited to...".

[0023] Figure 1 is a schematic diagram of the timing generator 10 of the embodiment. It includes a first current source CS1, a first switch S1, a second switch S2, a capacitor C, and a signal synthesizer SS. The first current source CS1 generates a first current I1 based on the input voltage Vin. The first switch S1 includes a first terminal coupled to the first current source CS1, a second terminal coupled to the charging terminal VT, and a control terminal for receiving a charging signal Tcharge. The capacitor C is coupled between the charging terminal VT and the ground terminal GND. The signal synthesizer SS generates a timing signal Ton based on the charging voltage Vramp and the reference voltage Vref. The signal synthesizer SS includes a comparator COMP and a latch SR. The comparator COMP includes a negative input terminal for receiving the reference voltage Vref and a positive input terminal coupled to the charging terminal VT for receiving the charging voltage Vramp. The latch SR includes a setting terminal S for receiving the charging signal Tcharge, a reset terminal R coupled to the output of the comparator COMP, and an output terminal Q for outputting the timing signal Ton. When the timing signal Ton passes through the external circuit EXT, the timing signal Ton may be delayed or deformed due to various circuit operation effects, causing the pulse width of the timing signal Ton to differ from the preset pulse width. This result is referred to as the time difference timing signal Ton_f in the embodiment. The transmission delay of the timing signal Ton may cause the falling edge of the time difference timing signal Ton_f to lag behind the falling edge of the timing signal Ton, while the start-up delay of the timing signal Ton may cause the rising edge of the timing signal Ton to lag behind the rising edge of the time difference timing signal Ton_f.

[0024] Please refer to Figures 1 and 2. Figure 2 is a timing diagram of the operating signals of the timing signal generator 10 in the embodiment of Figure 1. Between time t1 and t2, the charging signal Tcharge is low (e.g., 0V), causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref (e.g., 5V), causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing the output terminal Q to output a low-level timing signal Ton (e.g., 0V). When the timing signal Ton passes through the external circuit EXT, the timing signal Ton may be delayed or deformed due to various circuit operation effects, causing the pulse width of the timing signal Ton to be different from the preset pulse width, so that the time difference timing signal Ton_f between time t1 and t2 may be high.

[0025] Between time t2 and t3, the charging signal Tcharge rises to a high level. The high-level charging signal Tcharge turns on the first switch S1, and the first current source CS1 begins to charge the capacitor C with the first current I1, causing the charging voltage Vramp to rise continuously. The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Q to rise to a high level (e.g., 5V).

[0026] At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of comparator COMP rises to a high level, and the charging signal Tcharge drops to a low level. Latch SR simultaneously receives the low-level charging signal Tcharge and the high-level output signal of comparator COMP, causing the timing signal Ton output from output Q to drop to a low level. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the second switch S2 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing the charging voltage Vramp to drop rapidly to a low level. However, between times t3 and t4, the timing signal Ton is low, while the time difference timing signal Ton_f may remain high due to delays caused by various circuit operation effects, leading to asynchrony in the internal circuitry of the chip and causing other errors. Therefore, the correction mechanism described in the following embodiment can be used to restore the pulse width of the time difference timing signal Ton_f to the preset pulse width of the timing signal Ton.

[0027] Figure 3 is a schematic diagram of the timing generator 100 according to the embodiment. The timing generator 100 includes a first current source CS1, a first switch S1, a second current source CS2, a second switch S2, a third switch S3, a capacitor C, a comparator COMP, and a time difference extractor TE. The first current source CS1 generates a first current I1 based on the input voltage Vin. The first switch S1 includes a first terminal coupled to the first current source CS1, a second terminal coupled to the charging terminal VT, and a control terminal for receiving a charging signal Tcharge. The second current source CS2 generates a second current I2 based on the input voltage Vin. The second switch S2 includes a first terminal coupled to the second current source CS2, a second terminal coupled to the charging terminal VT, and a control terminal for receiving a time difference signal Td. The third switch S3 includes a first terminal coupled to the charging terminal VT, a second terminal coupled to the ground terminal GND, and a control terminal for receiving a reset signal RST. The capacitor C is coupled between the charging terminal VT and the ground terminal GND. The signal synthesizer SS includes a comparator COMP and a latch SR. Comparator COMP includes a negative input to receive the reference voltage Vref, a positive input coupled to the charging terminal VT to receive the charging voltage Vramp, and an output terminal Q. Latch SR includes a setting terminal S to receive the charging signal Tcharge, a reset terminal R coupled to the output of comparator COMP, and an output terminal Q to output the timing signal Ton. The time difference extractor TE generates a time difference signal Td based on the timing signal Ton and the time difference timing signal Ton_f. The time difference extractor TE includes a first input coupled to the output of the signal synthesizer SS, a second input to receive the time difference timing signal Ton_f output by the external circuit EXT, and an output terminal to output the time difference signal Td.

[0028] In this embodiment, the first switch S1, the second switch S2, and the third switch S3 can be N-type transistors, such as bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or FinFETs. However, this embodiment is not limited to these, and other types of transistors should also be within the scope of this invention. The time difference extractor TE can be an XOR gate. The time difference between the time difference timing signal Ton_f and the timing signal Ton is generated by the external circuit EXT. That is, after the timing signal Ton passes through the external circuit EXT, the timing signal Ton may be delayed or deformed due to various circuit operation effects, causing the pulse width of the timing signal Ton to be different from the preset value. The result is referred to as the time difference timing signal Ton_f in this embodiment. The transmission delay of the timing signal Ton may cause the falling edge of the time difference timing signal Ton_f to lag behind the falling edge of the timing signal Ton, while the start-up delay of the timing signal Ton may cause the rising edge of the timing signal Ton to lag behind the rising edge of the time difference timing signal Ton_f. Modern high-speed circuits operate in nanosecond increments, and delays or distortions in the timing signal Ton can lead to asynchrony and other errors within the chip's internal circuitry. Therefore, the time difference extractor TE can be used to extract the time difference between the timing signal Ton and the time difference timing signal Ton_f; the extracted result is the time difference signal Td. The timing signal generator 100 has a feedback mechanism that can use the time difference signal Td to correct for delays or distortions in the timing signal Ton, thereby ensuring accurate operation of the high-speed circuit.

[0029] Please refer to Figures 3 and 4. Figure 4 is a timing diagram of the operation signals of the timing signal generator 100 in the embodiment of Figure 3. Between time t1 and t2, the charging signal Tcharge is low (e.g., 0V), causing the first switch S1 to turn off. The charging voltage Vramp level is lower than the reference voltage Vref level (e.g., 5V), causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level output signal of the comparator COMP, causing the output terminal Q to output a low-level timing signal Ton. At this time, the timing signal Ton is low (e.g., 0V), and the time difference timing signal Ton_f is high. The time difference extractor TE performs an XOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, between time t1 and t2, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 charges the capacitor C with the second current I2, causing the charging voltage Vramp to rise.

[0030] Between time t2 and t3, the charging signal Tcharge rises to a high level (e.g., 5V). The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Q to rise to a high level (e.g., 5V). At this time, the timing signal Ton is high, and the time difference timing signal Ton_f is also high. The time difference extractor TE performs an XOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops charging the capacitor C, while the first current source CS1 starts charging the capacitor C with the first current I1, continuously increasing the charging voltage Vramp. It should be noted that, in order to ensure that the charging voltage Vramp rises at a consistent rate, the value of the first current I1 is actually equal to the value of the second current I2.

[0031] At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of comparator COMP rises high, and the charging signal Tcharge drops low. Latch SR simultaneously receives the low-level charging signal Tcharge and the high-level output signal of comparator COMP, causing the timing signal Ton output by output Q to drop low, while the time difference timing signal Ton_f remains high. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing Vramp to drop rapidly to a low level. Furthermore, between times t3 and t4, the time difference signal Td generated by the time difference extractor TE in the above operating mode rises high, causing the second switch S2 to turn on again, charging capacitor C with the second current I2, and causing the charging voltage Vramp to rise again.

[0032] At time t4, the time difference timing signal Ton_f drops to a low level, and the timing signal Ton remains low. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off the second switch S2. Therefore, both the first current source CS1 and the second current source CS2 stop charging the capacitor C. The third switch S3 is in the closed state, so the charging voltage Vramp remains at the level before the power was cut off.

[0033] At time t5, timing signal generator 100 begins generating the timing signal for the next cycle. The low-level charging signal Tcharge turns off the first switch S1. The charging voltage Vramp is lower than the reference voltage Vref, causing comparator COMP to output a low-level signal. Latch SR simultaneously receives both the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing output Q to output a low-level timing signal Ton. At this time, timing signal Ton is low, and the time difference timing signal Ton_f is high. Time difference extractor TE performs an XOR operation on the pulse width difference between timing signal Ton and time difference timing signal Ton_f to generate the time difference signal Td. Therefore, at time t5, time difference signal Td is high, turning on the second switch S2. The second current source CS2 charges capacitor C with the second current I2, causing the charging voltage Vramp to rise from its previous level. The subsequent operation repeats from time t1 to t4, and will not be described further here. In this way, the timing signal generator 100 can continuously generate a timing signal Ton in each cycle according to the circuit function and requirements.

[0034] The pulse width of the timing signal Ton can be corrected using the following formula:

[0035] I2×Td=C×Vos

[0036]

[0037] I1×Ton=C×(Vref-Vos)

[0038]

[0039]

[0040] I1 is the first current, I2 is the second current, C is the capacitance value, Td is the pulse width of the time difference signal, Ton is the pulse width of the timing signal, Ton_f is the pulse width of the time difference timing signal, Vos is the offset voltage value, and Vref is the reference voltage value. The offset voltage Vos, as shown in Figure 2, is the voltage accumulated by the second current source CS2 charging capacitor C with the second current I2. The voltage accumulated by the first current source CS1 charging capacitor C with the first current I1 is Vref - Vos.

[0041] As described above, in one operating cycle, the capacitor C is first charged with the second current I2, raising the charging voltage Vramp to a level called the offset voltage Vos. Since the comparator COMP compares the current or voltage at its two input terminals and outputs different voltage results, this reduces the time it takes for the first current I1 to raise the charging voltage Vramp (received from the positive input terminal) to reach the voltage level received at the negative input terminal of the comparator COMP. This is used to correct the timing signal Ton, shortening its pulse width. The delay generated when the timing signal Ton passes through the external circuit EXT can be used to correct the timing signal Ton, making the pulse width of the time difference timing signal Ton_f essentially equal to the preset pulse width of the timing signal Ton. Therefore, this mechanism can correct the delay or distortion of the timing signal Ton caused by the external circuit EXT, enabling the high-speed circuit to operate accurately.

[0042] Figure 5 is a schematic diagram of the timing signal generator 200 according to an embodiment. The timing signal generator 200 includes a first current source CS1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a second current source CS2, a first capacitor C1, a second capacitor C2, a comparator COMP, and a time difference extractor TE. The first current source CS1 generates a first current I1 based on the input voltage Vin. The first switch S1 includes a first terminal coupled to the first current source CS1, a second terminal coupled to the charging terminal VT, and a control terminal for receiving a charging signal Tcharge. The second switch S2 includes a first terminal coupled to the bias terminal OS, a second terminal, and a control terminal for receiving a time difference signal Td. The second current source CS2 is coupled to the second terminal of the second switch S2 to generate a second current I2 based on the input voltage Vin. The third switch S3 includes a first terminal coupled to the charging terminal VT, a second terminal coupled to the ground terminal GND, and a control terminal for receiving a reset signal RST. The fourth switch S4 includes a first terminal, a second terminal coupled to the bias terminal OS, and a control terminal for receiving the reset signal RST. The first capacitor C1 is coupled between the charging terminal VT and the ground terminal GND. The first terminal of the second capacitor C2 is coupled to the bias terminal OS, and the second terminal is used to receive the reference voltage Vref. The signal synthesizer SS is coupled to the charging terminal VT and is used to generate the timing signal Ton based on the charging voltage Vramp and the offset reference voltage Vref_os. The signal synthesizer SS includes a comparator COMP and a latch SR. The comparator COMP includes a negative input terminal coupled to the bias terminal OS for receiving the offset reference voltage Vref_os, and a positive input terminal coupled to the charging terminal VT for receiving the charging voltage Vramp. The latch SR includes a setting terminal S for receiving the charging signal Tcharge, a reset terminal R coupled to the output terminal of the comparator COMP, and an output terminal Q for outputting the timing signal Ton. The time difference extractor TE is coupled to the output of the signal synthesizer SS and the control terminal of the second switch S2, and is used to generate a time difference signal Td based on the timing signal Ton and the time difference timing signal Ton_f. The time difference extractor TE includes a first input terminal coupled to the output of the signal synthesizer SS, a second input terminal for receiving the time difference timing signal Ton_f output by the external circuit EXT, and an output terminal for outputting the time difference signal Td.

[0043] In this embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be N-type transistors, such as bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or FinField-Effect Transistors (FinFETs). However, this embodiment is not limited to these, and other types of transistors should also be within the scope of this invention. The time difference extractor TE can be an XOR gate. The time difference between the time difference timing signal Ton_f and the timing signal Ton is generated by the external circuit EXT. That is, after the timing signal Ton passes through the external circuit EXT, the timing signal Ton may be delayed or deformed due to various circuit operation effects, causing the pulse width of the timing signal Ton to be different from the preset value. The result is referred to as the time difference timing signal Ton_f in this embodiment. Modern high-speed circuits operate in nanosecond increments or faster. Delays or distortions in the timing signal Ton can easily lead to asynchrony and other errors within the chip's internal circuitry. Therefore, a time difference extractor TE can be used to extract the time difference between the timing signal Ton and the time difference timing signal Ton_f, the result of which is the time difference signal Td. The timing signal generator 200, another embodiment of the invention, has a feedback mechanism that can use the time difference signal Td to correct for delays or distortions in the timing signal Ton, thereby enabling the high-speed circuit to operate accurately.

[0044] Please refer to Figures 5 and 6. Figure 6 is a timing diagram of the operating signals of the timing signal generator 200 in the embodiment of Figure 5. Between time t1 and t2, the charging signal Tcharge is low, causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref, causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing the output terminal Q to output a low-level timing signal Ton. At this time, the timing signal Ton is low, and the time difference timing signal Ton_f is high. The time difference extractor TE performs an XOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, at time t1, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 discharges the second capacitor C2 with the second current I2, thereby causing the offset reference voltage Vref_os to decrease.

[0045] Between time t2 and t3, the charging signal Tcharge rises to a high level. The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Q to rise to a high level. At this time, the timing signal Ton is high, and the time difference timing signal Ton_f is also high. The time difference extractor TE performs an XOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops discharging the second capacitor C2, and the offset reference voltage Vref_os stops decreasing. Meanwhile, the first current source CS1 begins charging the first capacitor C1 with the first current I1, causing the charging voltage Vramp to rise. It should be noted that, in order to ensure that the charging voltage Vramp rises at the same rate as the offset reference voltage Vref_os falls at the same rate, the value of the first current I1 is actually equal to the value of the second current I2.

[0046] At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of comparator COMP rises to a high level, and the charging signal Tcharge drops to a low level. Latch SR simultaneously receives the low-level charging signal Tcharge and the high-level comparator COMP output signal, causing the timing signal Ton output from output Q to drop to a low level, while the time difference timing signal Ton_f remains high. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing Vramp to quickly drop to a low level. Simultaneously, the reset signal RST also turns on the fourth switch S4 for a very short time, pulling the offset reference voltage Vref_os back to the level of the reference voltage Vref. Furthermore, between time t3 and t4, the time difference extractor TE generates a time difference signal Td that rises to a high level in the above-described operation mode, causing the second switch S2 to turn on again, and the second current I2 to discharge the second capacitor C2, causing the offset reference voltage Vref_os to drop again.

[0047] At time t4, the time difference timing signal Ton_f drops to a low level, and the timing signal Ton remains low. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off both second switches S2. The first current source CS1 stops charging the first capacitor C1, and the second current source CS2 stops discharging the second capacitor C2. The third switch S3 is in the closed state, so the offset reference voltage Vref_os remains at the level before the power-off.

[0048] At time t5, timing signal generator 200 begins generating the timing signal for the next cycle. The low-level charging signal Tcharge turns off the first switch S1. The charging voltage Vramp is lower than the reference voltage Vref, causing comparator COMP to output a low-level signal. Latch SR simultaneously receives both the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing output Q to output a low-level timing signal Ton. At this time, timing signal Ton is low, and the time difference timing signal Ton_f is high. Time difference extractor TE performs an XOR operation on the pulse width difference between timing signal Ton and time difference timing signal Ton_f to generate time difference signal Td. Therefore, at time t5, time difference signal Td is high, turning on the second switch S2. The second current source CS2 discharges the second capacitor C2 with the second current I2, causing the offset reference voltage Vref_os to drop from its previous level. The subsequent operation repeats from time t1 to t4, and will not be described further here. In this way, the timing signal generator 200 can continuously generate a timing signal Ton in each cycle according to the circuit function and requirements.

[0049] The pulse width of the timing signal Ton can be corrected using the following formula:

[0050] I2×Td=C×Vos

[0051]

[0052] I1×Ton=C×(Vref_os)=C×(Vref-Vos)

[0053]

[0054]

[0055] I1 is the first current, I2 is the second current, C is the capacitance of the first capacitor C1 and the second capacitor C2 (the capacitance of the first capacitor is essentially equal to the capacitance of the second capacitor), Td is the pulse width of the time difference signal, Ton is the pulse width of the timing signal, Ton_f is the pulse width of the time difference timing signal, Vos is the offset voltage, and Vref is the reference voltage. The offset voltage Vos, as shown in Figure 4, is the voltage at which the second capacitor C2 is discharged by the second current source CS2 with the second current I2 (causing the reference voltage Vref to decrease). The decrease in the reference voltage Vref after discharge is Vref - Vos.

[0056] As described above, in one operating cycle, the second current I2 first discharges the second capacitor C2, causing the reference voltage Vref to drop and rise to a certain level, called the offset reference voltage Vref_os. Since the comparator COMP compares the magnitudes of the current or voltage at its two input terminals and outputs different voltage results, this reduces the time required for the first current I1 to raise the charging voltage Vramp (received from the positive input terminal) to reach the voltage level received at the negative input terminal of the comparator COMP, thus correcting the timing signal Ton and shortening its pulse width. The delay generated when the timing signal Ton passes through the external circuit EXT can be used to correct the timing signal Ton, making the pulse width of the time difference timing signal Ton_f essentially equal to the preset pulse width of the timing signal Ton. Therefore, this mechanism can correct the delay or distortion of the timing signal Ton caused by the external circuit EXT, enabling the high-speed circuit to operate accurately.

[0057] Figure 7 is a schematic diagram of the timing signal generator 300 in this embodiment. The circuit layout of the timing signal generator 300 is similar to that of the timing signal generator 100. The difference is that the time difference timing signal Ton_f formed by the timing signal Ton generated by the timing signal generator 300 after passing through the external circuit EXT is out of phase with the timing signal Ton. Therefore, the time difference extractor TE of the timing signal generator 300 can be replaced by a NOR gate. All other components are the same as those of the timing signal generator 100 and will not be described in detail here.

[0058] Figure 8 is a timing diagram of the operation signals of the timing signal generator 300 in the embodiment of Figure 7. The timing diagram of the operation signals of the timing signal generator 300 is similar to that of the timing signal generator 100. The difference is that the time difference timing signal Ton_f of the timing signal generator 300 is out of phase with the time difference timing signal Ton_f of the timing signal generator 100. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td of the timing signal generator 300 is in phase with the time difference signal Td of the timing signal generator 100. All other operation signals are the same as those of the timing signal generator 100.

[0059] Specifically, between times t1 and t2, the charging signal Tcharge is low, causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref, causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level output signal of the comparator COMP, causing the output terminal Q to output a low-level timing signal Ton. At this time, the timing signal Ton is low, and the time difference timing signal Ton_f is also low. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, between times t1 and t2, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 charges the capacitor C with the second current I2, causing the charging voltage Vramp to rise. Between times t2 and t3, the charging signal Tcharge rises to a high level. The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Q to rise to a high level. At this time, the timing signal Ton is high, while the time difference timing signal Ton_f is low. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops charging the capacitor C, while the first current source CS1 starts charging the capacitor C with the first current I1, continuously causing the charging voltage Vramp to rise. At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of the comparator COMP rises to a high level, and the charging signal Tcharge drops to a low level. The latch SR simultaneously receives the low-level charging signal Tcharge and the high-level output signal of the comparator COMP, causing the timing signal Ton output by the output terminal Q to drop to a low level, while the time difference timing signal Ton_f remains low. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing the charging voltage Vramp to drop rapidly to a low level. Furthermore, between times t3 and t4, the time difference signal Td generated by the time difference extractor TE in the above operating mode rises to a high level, causing the second switch S2 to turn on again, charging the capacitor C with the second current I2, and causing the charging voltage Vramp to rise again.At time t4, the time difference timing signal Ton_f rises to a high level, and the timing signal Ton remains low. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off the second switch S2. Therefore, both the first current source CS1 and the second current source CS2 stop charging the capacitor C. The third switch S3 is in the closed state, so the charging voltage Vramp remains at the level before the power was cut off. The subsequent operation process repeats from time t1 to t4, and will not be described in detail here.

[0060] Figure 9 is a schematic diagram of the timing signal generator 400 in this embodiment. The circuit layout of the timing signal generator 400 is similar to that of the timing signal generator 200. The difference is that the time difference timing signal Ton_f formed by the timing signal Ton generated by the timing signal generator 400 after passing through the external circuit EXT is out of phase with the timing signal Ton. Therefore, the time difference extractor TE of the timing signal generator 400 can be replaced by a NOR gate. All other components are the same as those of the timing signal generator 200 and will not be described in detail here.

[0061] Figure 10 is a timing diagram of the operation signals of the timing signal generator 400 in the embodiment of Figure 9. The timing diagram of the operation signals of the timing signal generator 400 is similar to that of the timing signal generator 200. The difference is that the time difference timing signal Ton_f of the timing signal generator 400 is out of phase with the timing signal Ton. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td of the timing signal generator 400 is in phase with the time difference signal Td of the timing signal generator 200. All other operation signals are the same as those of the timing signal generator 200.

[0062] Specifically, between times t1 and t2, the charging signal Tcharge is low, causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref, causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing the output terminal Q to output a low-level timing signal Ton. At this time, the timing signal Ton is low, and the time difference timing signal Ton_f is also low. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate a time difference signal Td. Therefore, at time t1, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 discharges the second capacitor C2 with the second current I2, thereby causing the offset reference voltage Vref_os to decrease. Between time t2 and t3, the charging signal Tcharge rises to a high level. The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Q to rise to a high level. At this time, the timing signal Ton is high, and the time difference timing signal Ton_f is still low. The time difference extractor TE performs a NOR operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops discharging the second capacitor C2, and the offset reference voltage Vref_os stops decreasing. Meanwhile, the first current source CS1 begins charging the first capacitor C1 with the first current I1, causing the charging voltage Vramp to rise. At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of comparator COMP rises high, and the charging signal Tcharge drops low. Latch SR simultaneously receives the low-level charging signal Tcharge and the high-level comparator COMP output signal, causing the timing signal Ton output from output Q to drop low, while the time difference timing signal Ton_f remains low. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing Vramp to quickly drop low. Simultaneously, the reset signal RST also turns on the fourth switch S4 for a very short time, pulling the offset reference voltage Vref_os back to the level of the reference voltage Vref.Between times t3 and t4, the time difference signal Td generated by the time difference extractor TE in the above operating mode rises to a high level, causing the second switch S2 to turn on again, discharging the second capacitor C2 with the second current I2, and causing the offset reference voltage Vref_os to drop again. At time t4, the time difference timing signal Ton_f rises to a high level, and the timing signal Ton remains at a low level. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off both second switches S2. The first current source CS1 stops charging the first capacitor C1, and the second current source CS2 stops discharging the second capacitor C2. The third switch S3 is in the closed state, so the offset reference voltage Vref_os remains at the level before the power-off. The subsequent operation process repeats between times t1 and t4, and will not be described in detail here.

[0063] Figure 11 is a schematic diagram of the timing signal generator 500 in this embodiment. The circuit layout of the timing signal generator 500 is similar to that of the timing signal generator 100. The difference is that the output Qb of the latch SR of the timing signal generator 500 can output an inverted timing signal Ton. Therefore, the timing signal Ton generated by the timing signal generator 500 is out of phase with the timing signal Ton generated by the timing signal generator 100. Furthermore, the time difference timing signal Ton_f formed by the timing signal Ton generated by the timing signal generator 500 after passing through the external circuit EXT is out of phase with the timing signal Ton. Therefore, the time difference extractor TE of the timing signal generator 500 can be replaced by an AND gate. All other components are the same as those of the timing signal generator 100 and will not be described in detail here.

[0064] Figure 12 is a timing diagram of the operation signals of the timing signal generator 500 in the embodiment of Figure 11. The timing diagram of the operation signals of the timing signal generator 500 is similar to that of the timing signal generator 100. The difference is that the output Qb of the latch SR of the timing signal generator 500 can output an inverted timing signal Ton. Therefore, the timing signal Ton generated by the timing signal generator 500 is out of phase with the timing signal Ton generated by the timing signal generator 100. Furthermore, the time difference timing signal Ton_f formed by the timing signal Ton generated by the timing signal generator 500 after passing through the external circuit EXT is out of phase with the timing signal Ton. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td of the timing signal generator 500 is in phase with the time difference signal Td of the timing signal generator 100. All other operation signals are the same as those of the timing signal generator 100.

[0065] Specifically, between times t1 and t2, the charging signal Tcharge is low, causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref (e.g., 5V), causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level output signal of the comparator COMP, causing the output terminal Qb to output a high-level timing signal Ton. At this time, the timing signal Ton is high, and the time difference timing signal Ton_f is also high. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate a time difference signal Td. Therefore, between times t1 and t2, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 charges the capacitor C with the second current I2, causing the charging voltage Vramp to rise. Between times t2 and t3, the charging signal Tcharge rises to a high level. The latch SR simultaneously receives both the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Qb to drop to a low level. At this time, the timing signal Ton is low, and the time difference timing signal Ton_f is high. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops charging the capacitor C, while the first current source CS1 starts charging the capacitor C with the first current I1, continuously causing the charging voltage Vramp to rise. At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of the comparator COMP rises to a high level, and the charging signal Tcharge drops to a low level. The latch SR simultaneously receives the low-level charging signal Tcharge and the high-level output signal of the comparator COMP, causing the timing signal Ton output by the output terminal Qb to rise to a high level, while the time difference timing signal Ton_f remains high. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing the charging voltage Vramp to drop rapidly to a low level. Furthermore, between times t3 and t4, the time difference extractor TE, operating in the above manner, generates a time difference signal Td that rises to a high level, causing the second switch S2 to turn on again, charging the capacitor C with the second current I2, and causing the charging voltage Vramp to rise again.At time t4, the time difference timing signal Ton_f drops to a low level, while the timing signal Ton remains high. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off the second switch S2. Therefore, both the first current source CS1 and the second current source CS2 stop charging the capacitor C. The third switch S3 is in the closed state, so the charging voltage Vramp remains at the level before the power was cut off. The subsequent operation process repeats from time t1 to t4, and will not be described in detail here.

[0066] Figure 13 is a schematic diagram of the timing signal generator 600 in this embodiment. The circuit layout of the timing signal generator 600 is similar to that of the timing signal generator 200. The difference lies in that the output Qb of the latch SR in the timing signal generator 600 can output an inverted timing signal Ton. Therefore, the timing signal Ton generated by the timing signal generator 600 is out of phase with the timing signal Ton generated by the timing signal generator 200. Furthermore, the time difference timing signal Ton_f formed by the timing signal Ton generated by the timing signal generator 600 after passing through the external circuit EXT is out of phase with the timing signal Ton. Therefore, the time difference extractor TE of the timing signal generator 600 can be replaced by an AND gate. All other components are the same as those in the timing signal generator 200 and will not be described in detail here.

[0067] Figure 14 is a timing diagram of the operation signals of the timing signal generator 600 in the embodiment of Figure 13. The timing diagram of the operation signals of the timing signal generator 600 is similar to that of the timing signal generator 200. The difference is that the timing signal Ton of the timing signal generator 600 is out of phase with the timing signal Ton of the timing signal generator 200. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td of the timing signal generator 600 is in phase with the time difference signal Td of the timing signal generator 200. All other signals are the same as the operation signals of the timing signal generator 200.

[0068] Specifically, between times t1 and t2, the charging signal Tcharge is low, causing the first switch S1 to turn off. The charging voltage Vramp is lower than the reference voltage Vref, causing the comparator COMP to output a low-level signal. The latch SR simultaneously receives the low-level charging signal Tcharge and the low-level comparator COMP output signal, causing the output terminal Qb to output a high-level timing signal Ton. At this time, the timing signal Ton is high, and the time difference timing signal Ton_f is also high. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, at time t1, the time difference signal Td is high, causing the second switch S2 to turn on. The second current source CS2 discharges the second capacitor C2 with the second current I2, thereby causing the offset reference voltage Vref_os to decrease. Between time t2 and t3, the charging signal Tcharge rises to a high level. The latch SR simultaneously receives the high-level charging signal Tcharge and the low-level comparator COMP output signal, causing the timing signal Ton output by the output terminal Qb to drop to a low level. At this time, the timing signal Ton is low, and the time difference timing signal Ton_f is high. The time difference extractor TE performs an AND operation on the pulse width difference between the timing signal Ton and the time difference timing signal Ton_f to generate the time difference signal Td. Therefore, the time difference signal Td generated by the time difference extractor TE will drop to a low level. The high-level charging signal Tcharge turns on the first switch S1, and the low-level time difference signal Td turns off the second switch S2. The second current source CS2 stops discharging the second capacitor C2, and the offset reference voltage Vref_os stops decreasing. Meanwhile, the first current source CS1 begins charging the first capacitor C1 with the first current I1, causing the charging voltage Vramp to rise. At time t3, the charging voltage Vramp reaches the level of the reference voltage Vref, the output signal of comparator COMP rises high, and the charging signal Tcharge drops low. Latch SR simultaneously receives the low-level charging signal Tcharge and the high-level comparator COMP output signal, causing the timing signal Ton output from output Qb to rise high, while the time difference timing signal Ton_f remains high. Ideally, the pulse width of the charging signal Tcharge is essentially equal to the pulse width of the timing signal Ton. At this time, the reset signal RST (a pulse signal with rapidly changing amplitude) is activated, turning on the third switch S3 for a very short time, releasing the charging voltage Vramp accumulated at the charging terminal VT, causing Vramp to quickly drop low. Simultaneously, the reset signal RST also turns on the fourth switch S4 for a very short time, pulling the offset reference voltage Vref_os back to the level of the reference voltage Vref.Between times t3 and t4, the time difference signal Td generated by the time difference extractor TE in the above operating mode rises to a high level, causing the second switch S2 to turn on again, discharging the second capacitor C2 with the second current I2, and causing the offset reference voltage Vref_os to drop again. At time t4, the time difference timing signal Ton_f drops to a low level, and the timing signal Ton remains at a high level. The time difference signal Td generated by the time difference extractor TE in the above operating mode drops to a low level. The low-level charging signal Tcharge turns off the first switch S1, and the low-level time difference signal Td turns off both second switches S2. The first current source CS1 stops charging the first capacitor C1, and the second current source CS2 stops discharging the second capacitor C2. The third switch S3 is in the closed state, so the offset reference voltage Vref_os remains at the level before the power-off. The subsequent operation process repeats between times t1 and t4, and will not be described in detail here.

[0069] In summary, the timing signal generator of this invention can correct the timing signal to shorten its pulse width. The delay generated when the timing signal passes through the external circuit can be used to correct the timing signal, making the pulse width of the timing signal substantially equal to the preset timing signal pulse width. Therefore, this mechanism can correct the delay or distortion of the timing signal caused by the external circuit, enabling high-speed circuits to operate accurately.

[0070] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0071] [Symbol Explanation]

[0072] 10, 100, 200, 300, 400, 500, 600: Timing signal generator

[0073] EXT: External Circuits

[0074] CS1, CS2: Current sources

[0075] S1~S4: Switches

[0076] C, C1, C2: Capacitors

[0077] SS: Signal Synthesizer

[0078] COMP: Comparator

[0079] TE: Time Difference Extractor

[0080] SR: Latch

[0081] VT: Charging end

[0082] GND: Ground terminal

[0083] S: Settings

[0084] R: Reset End

[0085] Q, Qb: Output terminals

[0086] OS: Bias end

[0087] Tcharge: Charging signal

[0088] RST: Reset signal

[0089] Ton: Timing signal

[0090] Ton_f: Time difference timing signal

[0091] Td: Time difference signal

[0092] Vin: Input voltage

[0093] Vref: Reference voltage

[0094] Vref_os: Offset reference voltage

[0095] Vos: Offset Voltage

[0096] Vramp: Charging voltage

[0097] I1, I2: Current

[0098] t1~t5: Time

Claims

1. A timing signal generator, comprising: The first current source is used to generate a first current based on the input voltage; The first switch includes: The first end is coupled to the first current source; The second end is coupled to the charging end; and The control terminal is used to receive charging signals; A second current source is used to generate a second current based on the input voltage; The second switch includes: The first terminal is coupled to the second current source; The second end is coupled to the charging end; and The control unit is used to receive time difference signals; The third switch includes: The first end is coupled to the charging end; The second terminal is coupled to the ground terminal; and The control terminal is used to receive reset signals; A capacitor is coupled between the charging terminal and the grounding terminal; A signal synthesizer, coupled to the charging terminal, is used to generate a timing signal based on the charging voltage and a reference voltage. and A time difference extractor, coupled to the control terminal of the signal synthesizer and the second switch, is used to generate the time difference signal based on the timing signal and the time difference timing signal, wherein the time difference timing signal is generated by the timing signal through an external circuit.

2. The timing signal generator as claimed in claim 1, wherein the signal synthesizer comprises: A comparator, comprising: The negative input terminal is used to receive the reference voltage; The positive input terminal, coupled to the charging terminal, is used to receive the charging voltage; and Output terminal; and A latch contains: The setting end is used to receive the charging signal; The reset terminal is coupled to the output terminal of the comparator; and The output terminal is used to output the timing signal.

3. The timing signal generator as claimed in claim 1, wherein the time difference extractor comprises: The first input terminal is coupled to the output terminal of the signal synthesizer; The second input terminal is used to receive the time difference timing signal; and The output terminal is used to output the time difference signal.

4. The timing signal generator as described in claim 3, wherein the time difference extractor is an XOR gate.

5. The timing signal generator as claimed in claim 3, wherein the time difference extractor is a NOR gate.

6. The timing signal generator as claimed in claim 3, wherein the time difference extractor is an AND gate.

7. The timing signal generator as claimed in claim 1, wherein the pulse width of the timing signal is greater than the pulse width of the time difference signal.

8. The timing signal generator as claimed in claim 1, wherein the current value of the first current is substantially equal to the current value of the second current.

9. The timing signal generator as claimed in claim 1, wherein the first switch, the second switch and the third switch are N-type transistors.

10. A timing signal generator, comprising: The first current source is used to generate a first current based on the input voltage; The first switch includes: The first end is coupled to the first current source; The second end is coupled to the charging end; and The control terminal is used to receive charging signals; The second switch includes: The first end is coupled to the bias terminal; The second end; and The control unit is used to receive time difference signals; A second current source is coupled to the second terminal of the second switch to generate a second current according to the input voltage; The third switch includes: The first end is coupled to the charging end; The second terminal is coupled to the ground terminal; and The control terminal is used to receive reset signals; The fourth switch includes: First end; The second end is coupled to the bias terminal; and The control terminal is used to receive the reset signal; A first capacitor is coupled between the charging terminal and the grounding terminal; The second capacitor is coupled between the bias terminal and the first terminal of the fourth switch; A signal synthesizer, coupled to the charging terminal, is used to generate a timing signal based on the charging voltage and the offset reference voltage. and A time difference extractor, coupled to the control terminal of the signal synthesizer and the second switch, is used to generate the time difference signal based on the timing signal and the time difference timing signal, wherein the time difference timing signal is generated by the timing signal through an external circuit.

11. The timing signal generator of claim 10, wherein the signal synthesizer comprises: A comparator, comprising: The negative input terminal is coupled to the bias terminal to receive the offset reference voltage; The positive input terminal, coupled to the charging terminal, is used to receive the charging voltage; and Output terminal; and A latch, comprising: The setting end is used to receive the charging signal; The reset terminal is coupled to the output terminal of the comparator; and The output terminal is used to output the timing signal.

12. The timing signal generator of claim 10, wherein the time difference extractor comprises: The first input terminal is coupled to the output terminal of the signal synthesizer; The second input terminal is used to receive the time difference timing signal; and The output terminal is used to output the time difference signal.

13. The timing signal generator of claim 12, wherein the time difference extractor is an XOR gate.

14. The timing signal generator of claim 12, wherein the time difference extractor is a NOR gate.

15. The timing signal generator of claim 12, wherein the time difference extractor is an AND gate.

16. The timing signal generator of claim 10, wherein the pulse width of the timing signal is greater than the pulse width of the time difference signal.

17. The timing signal generator of claim 10, wherein the current value of the first current is substantially equal to the current value of the second current.

18. The timing signal generator of claim 10, wherein the first switch, the second switch, the third switch and the fourth switch are N-type transistors.

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