A sigma-delta analog-to-digital converter with high energy efficiency and high area efficiency

Abstract

The application relates to a Sigma-Delta analog-digital converter with high energy consumption efficiency and high area efficiency, which comprises a loop integrator, a SAR ADC, a comparator, a buffer, a CDAC module and a clock generation module, and is described by a signal flow as a description path; in a first step conversion, an input signal is connected to the SAR ADC and the CDAC module respectively; the SAR ADC is sequentially connected to the CDAC module, the loop integrator, the comparator and the CDAC module, and a Sigma-Delta loop is formed; in a second step conversion, no input signal is received, the comparator is closed, and the buffer is opened; after the loop integrator is reconstructed, the loop integrator is sequentially connected to the buffer, the SAR ADC, the CDAC module and the loop integrator, and a Sigma-Delta loop is formed. The architecture and technology provided by the application can improve the energy consumption efficiency and the area efficiency of the ADC.

Description

Technical Field

[0001] This invention relates to a Sigma-Delta analog-to-digital converter with high energy efficiency and high area efficiency. Background Technology

[0002] Sensors are essential in many applications, such as sensing audio, temperature, light, magnetism, force, and capacitance, as well as biopotential acquisition in wearable devices. They typically handle narrowband signals ranging from DC to tens of kHz. For battery-powered sensor systems, energy-efficient analog-to-digital converters (ADCs) are particularly important and are often custom-designed to meet the sensor's requirements. These ADCs must also be robust to offset and flicker noise. Furthermore, these on-chip ADCs often require multiplexing in applications with many channels and those demanding large numbers of channels, such as image sensors or biopotential acquisition sensors, where devices must be highly efficient in terms of both energy and area.

[0003] Among all types of ADCs, the Sigma-Delta ADC, which utilizes oversampling and noise shaping, is widely used to achieve high resolution. This architecture comprises three main essential components: a loop filter, a quantizer, and a feedback digital-to-analog converter (DAC). The modulator oversamples the analog input signal, and then the loop filter integrates the residual error between that input and the estimated output (from the DAC). After the loop filter, the quantizer digitizes the processed signal and provides information via the feedback DAC. The Sigma-Delta modulator operates continuously without resetting the loop integrator, generating shaped quantization noise. Therefore, filtering out-of-band quantization noise with a low-pass digital decimation filter while preserving in-band signal power guarantees a high in-band signal-to-quantization-to-noise ratio (SQNR). Furthermore, higher loop orders generate more out-of-band quantization noise, resulting in higher resolution performance. Periodically resetting the loop filter and digital filter constitutes an incremental ADC (IADC). While IADCs disrupt the continuity of the loop, they offer advantages such as ease of multiplexing, low latency, less susceptibility to idle tones, and simpler filtering, making them widely used in sensor applications. Because IADCs are reset periodically, they can also be considered Nyquist-type ADCs, which allows for their mixed application with other Nyquist-type ADCs.

[0004] First-order IADCs require long conversion times, resulting in low energy efficiency. To shorten conversion times and thus improve energy efficiency, higher-order IADCs can be used. However, they are more prone to instability and have a smaller input range. Therefore, hybrid IADCs combined with Nyquist rate ADCs are investigated. In hybrid IADC architectures, techniques such as zoom and two-step and multi-step architectures are widely used.

[0005] The most significant advantage of Zoom technology is that it can reduce the swing of the loop integrator, thus allowing the use of high-efficiency amplifiers without sacrificing the input signal range, thereby saving energy. The most significant advantage of two-step and multi-step architectures is that they can reduce the ADC oversampling rate (OSR) while achieving the same signal-to-noise ratio (SNR) through multiple conversion steps, thereby reducing the clock frequency and the overall system power consumption. Summary of the Invention

[0006] The purpose of this invention is to provide a Sigma-Delta analog-to-digital converter with high energy efficiency and high area efficiency.

[0007] This invention provides a high-energy-efficiency and high-area-efficiency Sigma-Delta analog-to-digital converter, comprising: a loop integrator, a quantizer, a comparator, a buffer, a capacitor DAC (CDAC) module, and a clock generation module. The quantizer is a SARADC, using the signal flow as the description path, wherein: In the first conversion step, the input signal is connected to the input terminal of the SAR ADC and the input terminal of the CDAC module respectively; the output terminal of the SAR ADC is connected to the input terminal of the CDAC module; the output terminal of the CDAC module is connected to the input terminal of the loop integrator; the output terminal of the loop integrator is connected to the input terminal of the comparator; and the output terminal of the comparator is connected to the input terminal of the CDAC module, thus forming a Sigma-Delta loop. In the second conversion step, no input signal is received, the comparator is turned off, and the buffer is turned on. After the loop integrator is reconstructed, the output of the loop integrator is connected to the input of the buffer, the output of the buffer is connected to the input of the SAR ADC, the output of the SAR ADC is connected to the input of the CDAC module, and the output of the CDAC module is connected to the input of the loop integrator, thus forming a Sigma-Delta loop.

[0008] This invention proposes an operating method for a Sigma-Delta analog-to-digital converter with high energy efficiency and high area efficiency. The specific steps are as follows: In the first conversion step, the SAR ADC first quantizes the input signal, and its conversion result is combined with the comparison result of the comparator to generate the reference level of the CDAC module. Then, the input signal and the CDAC module generate the input value of the loop integrator. At this time, the buffer is turned off. In the second conversion step, no input signal is received, the comparator is turned off, the SAR ADC is used as the quantizer in the Sigma-Delta loop, the buffer is turned on, and a new loop is formed. The final output is generated by the SAR ADC conversion results from the first and second conversion steps.

[0009] In this invention, the Zoom technology is implemented using a combination of a SAR ADC and a one-bit comparator.

[0010] In this invention, a two-step architecture reconstructs the loop quantizer and only enables the buffer module in the second step. During the first step, the quantizer is implemented using a one-bit comparator, and Zoom technology is enabled simultaneously; the buffer is not enabled at this time. During the second step, the buffer that was not enabled in the first step is activated, Zoom technology is disabled, and the SAR ADC used for Zoom quantization is reconstructed as a loop quantizer.

[0011] This invention combines a two-step architecture and Zoom technology, significantly reducing the input and output swing of the loop integrator module, making it possible to use high-efficiency amplifiers. Simultaneously, by utilizing the second-step re-conversion, the OSR is greatly reduced while achieving the same SNR, making it possible to further reduce power consumption while meeting high accuracy requirements.

[0012] The first step of this invention uses a SAR ADC-assisted zoom technology, and the second step uses a SAR ADC quantizer, making it possible to reuse SAR ADCs. In this invention, the same SAR ADC is used for quantization conversion in both the first and second steps, saving not only power consumption but also area and hardware overhead.

[0013] The buffer module used in the second-step conversion proposed in this invention is periodically turned on and off because it is only effective in the second step; that is, it is turned on only in the second step. This periodic on / off operation significantly reduces average power consumption, further achieving a low-power design and improving energy efficiency.

[0014] 1. This invention innovatively combines Zoom technology with a two-step architecture. In the first conversion step, Zoom technology is used to quantize the input signal using a SAR ADC. In the second conversion step, the same SAR ADC is used to quantize the output of the loop integrator. Therefore, the SAR ADC is reused, making full use of Zoom technology to reduce the loop swing and reduce energy consumption. The two-step reuse further improves energy efficiency and area efficiency.

[0015] 2. This invention innovatively involves periodically turning the buffer module on and off. The buffer module is not turned on in the first conversion step, but is turned on in the second conversion step. This distributes the high energy consumption of the buffer across the entire cycle, significantly reducing average power consumption and improving energy efficiency.

[0016] In summary, the architecture and technology proposed in this invention can improve the energy efficiency and area efficiency of ADCs. Attached Figure Description

[0017] Figure 1 The ADC architecture diagram proposed in this invention; Figure 2 Ideally, the output of the loop integrator modeled in Matlab Simulink; Figure 3 Ideally, this structure would have an SNDR (OSR=264). Figure 4 The overall implementation method of the ADC architecture proposed in this invention; Figure 5 A high-efficiency amplifier according to Embodiment 2 of the present invention. Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Unless otherwise expressly specified and limited, the terms "connected," "linked," etc., shall be interpreted broadly; for example, they may refer to electrical connection or mutual communication; they may refer to direct connection or indirect connection through an intermediate medium. It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0020] Example 1: Optionally, such as Figure 1 This allows the loop integrator to be a first-order integrator. The loop integrator can be selected to be second-order or higher, resulting in a higher SNR in the first conversion step while maintaining the same OSR, at the cost of reduced thermal noise suppression.

[0021] Optionally, give Figure 1The parameters are set as a1=0.75, a1ff_c=3, and x=2.25. The parameter selection is mainly based on the following considerations: in the first conversion step, a1 is selected to ensure proper control of the integrator swing; in the second conversion step, x is set to a1*a1ff_c, and the value of x must be chosen to ensure that the loop does not oscillate.

[0022] Optionally, let the signal bandwidth be 24kHz. The first step converts 256 cycles, and the second step converts 8 cycles. Therefore, OSR = 256 + 8 = 264, and the sampling frequency is 24kHz * 2 * 264 = 12.672MHz. The signal bandwidth, OSR, and sampling frequency can be selected according to the actual application scenario and process requirements of the ADC to make it suitable for more ADC applications.

[0023] Alternatively, the SAR ADC can be a five-bit SAR ADC. One option for a smaller control loop integrator swing is to use a higher bit SAR ADC, which would increase the design complexity of the SAR ADC as well as hardware and power consumption.

[0024] Optionally, in the first conversion step, the quantizer is a one-bit comparator, which, together with the five-bit SAR ADC, forms a zoom technology. The quantizer module can be made with a higher bit depth to achieve finer conversion, at the cost of increased design complexity and hardware overhead.

[0025] Under the parameters given in Embodiment 1 of this invention, ideally, the output swing of the loop integrator can be obtained by modeling in Matlab Simulink as follows: Figure 2 As shown (only a segment is shown; the unsegmented portion also falls within this swing range), the swing is only -0.08 to 0.08 (the full swing is set to -1 to +1), which is only 8% of the full swing. It is evident that this invention effectively reduces the swing of the loop integrator and improves energy efficiency.

[0026] Under the parameters given in Embodiment 1 of the present invention, with OSR=264, ideally, SNDR=132.6dB can be obtained, such as... Figure 3 As shown. Without the second step, using only the first-order loop integrator from the first step, theoretically, 2^32 cycles are needed to achieve 21-bit precision. 21 =2097152, which means OSR=2 is required. 21 It is evident that this invention significantly shortens the conversion time and improves energy efficiency.

[0027] In Embodiment 1 of this invention, the architecture functions correctly and successfully performs SAR ADC multiplexing. The area of ​​the SAR ADC is expected to be 800um * 350um = 0.28mm. 2Therefore, this invention can improve both energy efficiency and area efficiency.

[0028] In Embodiment 1 of this invention, the architecture functions normally, successfully enabling and disabling the buffer module periodically. Since its on-time is only 8 / 264, approximately 97% of the module's power consumption is saved. Optionally, if the buffer's power consumption is 400uW, the total average power consumption is only 12.12uW. Therefore, this invention reduces power consumption and improves energy efficiency.

[0029] Example 2: An embodiment of the present invention Figure 1 As shown. After each reset, the first step converts 264 clock cycles, and the second step converts 8 clock cycles. Optionally, as... Figure 4 As shown, the first step converts k cycles, and the second step converts m cycles. These settings can be adjusted according to the actual situation.

[0030] One embodiment of the present invention is as follows: Figure 1 As shown. During the first conversion step, Zoom technology is activated, which consists of a five-bit SAR ADC and a one-bit comparator. Optionally, as... Figure 4 As shown, the SAR ADC can be set to any number of bits according to the actual situation (the same applies to the DAC), and quantizer 1 can also be set to any number of bits according to the actual situation.

[0031] One embodiment of the present invention is as follows: Figure 1 As shown. In the first transformation step, the loop integrator is set to a first-order integrator; in the second transformation step, the loop integrator is reconstructed into a faster-accumulating integrator, thereby improving the SQNR more quickly. Optionally, as... Figure 4 As shown, in the first transformation, the loop integrator can be set to a higher-order integrator; in the second transformation, the loop integrator can be reconstructed into other integrators.

[0032] One embodiment of the present invention is as follows: Figure 1 As shown. Let parameters a1 = 0.75, a1ff_c = 3, x = 2.25. Optionally, as... Figure 4 As shown, these parameters (scaling factors) can be set to other reasonable values; if the structure of the loop integrator changes, these parameters may not be needed and can be set differently.

[0033] One embodiment of the present invention is as follows: Figure 1As shown, during the first conversion step, the buffer module is turned off; during the second conversion step, the same buffer is turned on and performs loop conversion together with the reconstructed loop integrator. This results in the buffer module being periodically turned on and off. Optionally, this buffer may not be needed in some other two-step structures. Furthermore, other modules used only in the first or second step may also exist in the two-step structure, and these can also be periodically turned on and off to save power and improve energy efficiency.

[0034] One embodiment of the present invention is as follows: Figure 3 As indicated by the label, the signal bandwidth is set to 24kHz. Optionally, the signal bandwidth can be set to other values ​​according to the application scenario and architecture requirements, and together with the optional OSR, constitute other sampling frequencies.

[0035] Example 3: The loop integrator uses an amplifier such as Figure 5 As shown, the amplifier is a sleeve operational amplifier with gain boosting technology and chopping technology to eliminate low-frequency noise. This amplifier has a small swing but high energy efficiency. Benefiting from the reduction in swing using zoom technology, this amplifier can be used in this embodiment.

Claims

1. A Sigma-Delta analog-to-digital converter with high energy efficiency and high area efficiency, characterized in that... include: The system includes a loop integrator, quantizer, comparator, buffer, capacitor DAC (CDAC) module, and clock generation module. The quantizer is a SAR ADC, described by the signal flow path, where: In the first conversion step, the input signal is connected to the input terminal of the SAR ADC and the input terminal of the CDAC module respectively; the output terminal of the SAR ADC is connected to the input terminal of the CDAC module; the output terminal of the CDAC module is connected to the input terminal of the loop integrator; the output terminal of the loop integrator is connected to the input terminal of the comparator; and the output terminal of the comparator is connected to the input terminal of the CDAC module, thus forming a Sigma-Delta loop. In the second conversion step, no input signal is received, the comparator is turned off, and the buffer is turned on. After the loop integrator is reconstructed, the output of the loop integrator is connected to the input of the buffer, the output of the buffer is connected to the input of the SAR ADC, the output of the SAR ADC is connected to the input of the CDAC module, and the output of the CDAC module is connected to the input of the loop integrator, thus forming a Sigma-Delta loop.

2. The Sigma-Delta analog-to-digital converter with high energy efficiency and high area efficiency according to claim 1, characterized in that... The operation method of the analog-to-digital converter is as follows: In the first conversion step, the SAR ADC first quantizes the input signal, and its conversion result is combined with the comparison result of the comparator to generate the reference level of the CDAC module. Then, the input signal and the CDAC module generate the input value of the loop integrator. At this point, the buffer is closed; In the second conversion step, no input signal is received, the comparator is turned off, the SAR ADC is used as a quantizer in the Sigma-Delta loop, the buffer is turned on, and a new loop is formed; the final output result is generated by the SAR ADC conversion results of the first and second conversion steps.

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