Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure manufacturing method comprises the following steps: providing a target layer; forming a plurality of first mask patterns on the top surface of the target layer; forming a plurality of second mask patterns above the target layer, each second mask pattern covering at least part of the top surface of each first mask pattern and part of the top surface of the target layer in the extension direction of the second mask pattern; performing first etching on the target layer based on the second mask pattern; removing the second mask pattern; and performing second etching on the target layer based on the first mask pattern. In the present disclosure, the target layer is etched twice by the second mask pattern and the first mask pattern respectively, and a more complex and high-density repeated structure is formed by etching, which reduces the difficulty of forming the repeated structure and is conducive to forming an integrated circuit with high integration.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the continuous advancement of integrated circuit (IC) development, the feature size of electronic components in ICs is constantly decreasing and the integration density is continuously increasing, enabling ICs to achieve higher integration levels. However, the feature size of electronic components has now been reduced to the physical limit achievable by mainstream photolithography technology. The resolution of photolithography technology is insufficient to meet the manufacturing requirements of ICs, posing a significant challenge to IC manufacturing processes. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] Provide the target layer;

[0007] Multiple first mask patterns are formed on the top surface of the target layer, and any two adjacent first mask patterns in the first direction are spaced apart.

[0008] A plurality of second mask patterns are formed above the target layer, each second mask pattern extending along the first direction and spaced apart from each other, each second mask pattern at least covering a portion of the top surface of each first mask pattern located in its extending direction and a portion of the top surface of the target layer;

[0009] The target layer is etched based on the second mask pattern;

[0010] The target layer is etched a second time based on the first mask pattern.

[0011] According to some embodiments of this disclosure, a plurality of first mask patterns are formed on the top surface of the target layer, including:

[0012] A cross structure is formed on the target layer, the cross structure including an overlapping region;

[0013] Remove part of the intersecting structure and retain part of the overlapping area; the retained overlapping area forms multiple initial mask patterns.

[0014] Remove a portion of the structure from each initial mask pattern, and the remaining portion of the structure of each initial mask pattern forms the first mask pattern.

[0015] According to some embodiments of this disclosure, a cross structure is formed on the target layer, including:

[0016] Multiple first line structures are formed, each of which extends along a second direction. In a direction perpendicular to the second direction, the multiple first line structures are spaced apart, and the first direction and the second direction intersect at an angle.

[0017] Multiple second line structures are formed, with multiple second line structures located above the first line structure. The second line structures extend along a third direction. In a direction perpendicular to the third direction, multiple second line structures are spaced apart. The first direction intersects the third direction at an angle.

[0018] Multiple first line structures and multiple second line structures together form the intersection structure, and the overlapping portions of the multiple first line structures and multiple second line structures form the overlapping region.

[0019] According to some embodiments of this disclosure, a plurality of second mask patterns are formed above the target layer, including:

[0020] A second mask material layer is formed, which covers the initial mask pattern and the exposed top surface of the target layer;

[0021] A portion of the second mask material layer is removed to form a plurality of second mask patterns extending along the first direction. In a direction perpendicular to the first direction, any two adjacent second mask patterns are separated by a first trench.

[0022] According to some embodiments of this disclosure, the projection of each second mask pattern onto the target layer is divided into multiple independently configured sub-patterns by the projection of the first mask pattern onto the target layer located in its extension direction.

[0023] According to some embodiments of this disclosure, the target layer is first etched based on the second mask pattern, including:

[0024] The portion of the target layer exposed by the second mask pattern is removed, and the remaining portion of the target layer is etched to form multiple active strips extending along the first direction. In a direction perpendicular to the first direction, two adjacent active strips are separated by a first shallow trench.

[0025] According to some embodiments of this disclosure, the method further includes:

[0026] A first isolation material is deposited to form a first isolation layer, which fills the first shallow trench and covers the first mask pattern and the top surface of the active strip exposed by the first mask pattern.

[0027] According to some embodiments of this disclosure, the method further includes:

[0028] The top surface of the first isolation layer is planarized to expose the top surfaces of multiple first mask patterns.

[0029] According to some embodiments of this disclosure, a second etching is performed on the target layer based on the first mask pattern, including:

[0030] The first mask pattern and the portion of the active strips covered by the first mask pattern are removed. The remaining portion of the active strips forms a plurality of independently configured active regions. The active regions extend along the first direction. In the first direction, two adjacent active regions are separated by a second shallow trench.

[0031] According to some embodiments of this disclosure, the method further includes:

[0032] A second insulating material is filled into the second shallow trench to form a second insulating layer.

[0033] According to some embodiments of this disclosure, the method further includes:

[0034] The first isolation layer and the second isolation layer above the top surface of the target layer are removed, and the retained first isolation layer and the second isolation layer together form a shallow trench isolation structure.

[0035] According to some embodiments of this disclosure, the first insulating material and the second insulating material may comprise the same or different materials.

[0036] According to some embodiments of this disclosure, the method further includes:

[0037] Multiple word lines are formed, each word line extending along a fourth direction and penetrating multiple active regions located in its extension direction, and the multiple word lines are spaced apart from each other.

[0038] According to some embodiments of this disclosure, the second direction and the third direction intersect at a first angle, and the first direction and the fourth direction intersect at a second angle. The relationship between the first angle and the second angle is as follows:

[0039]

[0040] Wherein, the first included angle is α1, and the second included angle is α2.

[0041] A second aspect of this disclosure provides a semiconductor structure fabricated according to the semiconductor structure fabrication method described above.

[0042] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the target layer is etched twice using the second mask pattern and the first mask pattern as masks, respectively, to form a more refined, complex, and dense repeating structure. This reduces the difficulty of forming the repeating structure and facilitates the formation of highly integrated integrated circuits.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art from these drawings without inventive effort.

[0045] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0046] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0047] Figure 3 This is a schematic diagram illustrating the formation of a first line structure on a target layer according to an exemplary embodiment.

[0048] Figure 4 This is a schematic diagram illustrating the formation of a first-layer structure according to an exemplary embodiment.

[0049] Figure 5 This is a schematic diagram illustrating the formation of a second dielectric layer according to an exemplary embodiment.

[0050] Figure 6 This is a schematic diagram illustrating the formation of a second line structure according to an exemplary embodiment.

[0051] Figure 7 This is a schematic diagram illustrating a formed cross structure according to an exemplary embodiment.

[0052] Figure 8 This is a top view of the formed cross structure shown according to an exemplary embodiment.

[0053] Figure 9This is a top view illustrating the etching of a first layer structure according to a second line structure, based on an exemplary embodiment.

[0054] Figure 10 This is a schematic diagram illustrating the formation of an initial mask pattern according to an exemplary embodiment.

[0055] Figure 11 This is a schematic diagram illustrating the formation of a second mask material layer according to an exemplary embodiment.

[0056] Figure 12 This is a top view of the third photomask and the initial mask pattern according to an exemplary embodiment.

[0057] Figure 13 This is a schematic diagram illustrating the formation of a second mask pattern according to an exemplary embodiment.

[0058] Figure 14 This is a top view of the second mask pattern and the first mask pattern according to an exemplary embodiment.

[0059] Figure 15 This is a schematic diagram illustrating the first etching of a target layer according to an exemplary embodiment.

[0060] Figure 16 This is a schematic diagram illustrating the formation of a first isolation layer according to an exemplary embodiment.

[0061] Figure 17 This is a schematic diagram illustrating a second etching of a target layer according to an exemplary embodiment.

[0062] Figure 18 This is a schematic diagram illustrating the formation of a second isolation layer according to an exemplary embodiment.

[0063] Figure 19 This is a schematic diagram illustrating the formation of an isolation structure according to an exemplary embodiment.

[0064] Figure 20 This is a top view of the active region shown according to an exemplary embodiment.

[0065] Figure 21 This is a top view illustrating the formation of word lines and bit lines according to an exemplary embodiment.

[0066] Figure 22 This is a schematic diagram illustrating a constructed coordinate system according to an exemplary embodiment.

[0067] Figure label:

[0068] 100. Target layer; 110. Active stripe; 111. Active region; 120. First shallow trench; 130. Second shallow trench; 200. Cross structure; 201. First mask pattern; 210. First line structure; 211. Initial mask pattern; 220. Second line structure; 221. Second dielectric layer; 230. Auxiliary layer; 240. First layer structure; 250. Overlapping region; 260. Third photomask; 300. Second mask material layer; 310. Second mask pattern; 311. Sub-pattern; 320. First trench; 400. Shallow trench isolation structure; 410. First isolation layer; 420. Second isolation layer; 500. Word line; 600. Bit line;

[0069] D1, First direction; D2, Second direction; D3, Third direction; D4, Fourth direction; α1, First included angle; α2, Second included angle; α3, Third included angle; α4, Fourth included angle. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0071] The exemplary embodiments of this disclosure provide a method for fabricating a semiconductor structure, which involves performing two etching processes on a target layer using a second mask pattern and a first mask pattern as masks, respectively. This method can form a repeating structure with a more refined and complex shape and a higher density in the target layer. The fabrication method of this embodiment reduces the difficulty of forming repeating structures and is conducive to forming highly integrated integrated circuits.

[0072] like Figure 1 As shown, Figure 1 A flowchart is shown of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, which includes the following steps.

[0073] Step S110: Provide the target layer.

[0074] Reference Figure 13 The target layer 100 refers to the material layer to be etched that needs to be patterned. The target layer 100 can be any structure used to form a semiconductor device.

[0075] The target layer 100 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can include other materials, such as gallium arsenide or other III-V compounds. The semiconductor substrate can be doped with some impurity ions as needed, and the impurity ions can be N-type impurity ions or P-type impurity ions.

[0076] The target layer 100 can also be a material layer for forming a semiconductor device, such as a dielectric layer or a metal layer. For example, the material layer can be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., and is not limited thereto.

[0077] Step S120: Form multiple first mask patterns on the top surface of the target layer, and set any two adjacent first mask patterns in the first direction apart.

[0078] Reference Figure 13 , Figure 14 In this embodiment, multiple first mask patterns 201 are independently disposed on the top surface of the target layer 100. In the first direction D1, the multiple first mask patterns 201 are arranged in multiple rows, and any two adjacent first mask patterns 201 in the first direction D1 are separated.

[0079] Step S130: A plurality of second mask patterns are formed above the target layer. Each second mask pattern extends along a first direction and is spaced apart from each other. Each second mask pattern at least covers a portion of the top surface of each first mask pattern located in its extending direction and a portion of the top surface of the target layer.

[0080] Reference Figure 13 , Figure 14 In this embodiment, each second mask pattern 310 is disposed on a row of first mask patterns 201, and each second mask pattern 310 fills a portion of the area between two adjacent first mask patterns 201 located in the same row.

[0081] In this embodiment, the projection of each second mask pattern 310 onto the target layer 100 is divided into multiple independently arranged sub-patterns 311 by the projection of the first mask pattern 201 located in its extending direction onto the target layer 100. In other embodiments, the shape and arrangement density of the first mask pattern 201 and the second mask pattern 310 are set according to the semiconductor structure to be formed.

[0082] Step S140: Perform the first etching on the target layer based on the second mask pattern.

[0083] Reference Figure 13 , Figure 14 , Figure 15 In this embodiment, the target layer 100 is etched using the second mask pattern 310 as a mask. The portion of the target layer 100 exposed by the second mask pattern 310 is removed, and the pattern of the second mask pattern 310 is extended into the target layer 100. The retained target layer 100 forms multiple independently configured structures. The etching process for the first etching can be either dry etching or wet etching.

[0084] Step S150: Perform a second etching on the target layer based on the first mask pattern.

[0085] First, the second mask pattern 310 is removed by dry or wet etching, exposing the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310.

[0086] Then, refer to 17. Figure 20 The first mask pattern 201 and the portion of the target layer 100 covered by the first mask pattern 201 are etched away to extend the pattern of the first mask pattern 201 into the target layer 100, and the target layer 100 that is etched and retained is divided into multiple independently configured substructures.

[0087] The semiconductor structure fabrication method of this embodiment forms two mask layers, a first mask pattern and a second mask pattern, above the target layer. The target layer is then etched twice according to the second mask pattern and the first mask pattern, forming a high-density repeating structure in the target layer. Compared with the scheme of directly forming the etching mask through photolithography, the fabrication method of this embodiment has lower requirements for the resolution accuracy of the photolithography process, reducing the process difficulty and process cost.

[0088] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 3-22 This is a schematic diagram of each stage of the semiconductor structure fabrication method in this embodiment. The following is in conjunction with... Figures 3-22 The method for fabricating the semiconductor structure in this embodiment will be described.

[0089] This disclosure provides a method for fabricating a semiconductor structure in an exemplary embodiment. This embodiment does not limit the semiconductor structure. The following description uses Dynamic Random Access Memory (DRAM) as an example to illustrate the formation of an active region in the semiconductor structure. However, this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures.

[0090] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 2 As shown, the steps include the following:

[0091] Step S210: Provide the target layer.

[0092] like Figure 3 As shown, in this embodiment, the target layer 100 is a semiconductor substrate, and the material of the semiconductor substrate is the same as that of the semiconductor substrate in the above embodiment.

[0093] Step S220: Form multiple initial mask patterns on the top surface of the target layer, and set any two adjacent initial mask patterns in the first direction apart.

[0094] Multiple initial mask patterns 211 can be formed on the top surface of the target layer 100 using the following methods:

[0095] Step S221: Form a cross structure on the target layer, the cross structure including overlapping regions.

[0096] First, such as Figure 3 As shown, multiple first line structures 210 are formed on the top surface of the target layer 100. Each first line structure 210 extends along the second direction D2. The multiple first line structures 210 are spaced apart in a direction perpendicular to the second direction D2. The first direction D1 and the second direction D2 intersect at an angle.

[0097] A first dielectric layer (not shown in the figure) can be formed on the top surface of the target layer 100 by depositing a dielectric material through a chemical vapor deposition process or a physical vapor deposition process. The material of the first dielectric layer may include silicon nitride and / or silicon oxide.

[0098] Reference Figure 8 A first photomask (not shown in the figure) is formed on the top surface of the first dielectric layer. A portion of the first dielectric layer is removed by etching according to the first photomask. The retained first dielectric layer forms multiple independently arranged first line structures 210. Each first line structure 210 extends along the second direction D2. In the direction perpendicular to the second direction D2, two adjacent first line structures 210 are spaced apart.

[0099] Then, as Figure 4As shown, auxiliary materials can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to form an auxiliary layer 230. The auxiliary layer 230 covers the first line structure 210 and fills the trenches between adjacent first line structures 210. The auxiliary layer 230 and the first line structures 210 together form the first layer structure 240. Then, the first layer structure 240 is ground to make its top surface planar, so that a second line structure 220 can be subsequently formed on the top surface of the first layer structure 240. The material of the auxiliary layer 230 may include silicon nitride, silicon oxynitride, etc., but is not limited to these. In some embodiments, the auxiliary layer 230 can also be formed using other processes, such as spin-coating the auxiliary material to form the auxiliary layer 230. The material of the auxiliary layer 230 can be spin-on carbon (SOC).

[0100] Next, as Figure 5 As shown, a second dielectric layer 221 can be formed on the top surface of the target layer 100 by depositing a dielectric material through a chemical vapor deposition process or a physical vapor deposition process. The material of the second dielectric layer 221 may include silicon nitride and / or silicon oxide.

[0101] like Figure 6 , Figure 7 , Figure 8 As shown, a second photomask (not shown) is formed on the top surface of the second dielectric layer 221. Part of the second dielectric layer 221 is removed by etching according to the second photomask. The remaining second dielectric layer 221 forms a plurality of second line structures 220. The plurality of second line structures 220 are located above the first line structure 210. The plurality of second line structures 220 are independently arranged. Each second line structure 220 extends along a third direction D3. In a direction perpendicular to the third direction D3, the plurality of second line structures 220 are spaced apart. The first direction D1 intersects the third direction D3 at an angle.

[0102] like Figure 7 , Figure 8 As shown, the first line structure 210 and the second line structure 220 form a cross structure 200 in the space above the target layer 100, and the first line structure 210 and the second line structure 220 have an overlapping part in the space above the target layer 100, which is the overlapping area 250 of the cross structure 200.

[0103] Step S222: Remove some of the intersecting structures, retain some of the overlapping areas, and the retained overlapping areas form multiple initial mask patterns.

[0104] The following methods can be used to remove part of the cross structure 200:

[0105] like Figure 9 As shown, refer to Figure 6 The first layer structure 240 is etched according to the second line structure 220, the auxiliary layer 230 and the first line structure 210 exposed by the second line structure 220 are removed, and the pattern of the second line structure 220 is transferred to the first layer structure 240. The retained first layer structure 240 includes a portion of the first line structure 210 and a portion of the auxiliary layer 230, wherein the retained portion of the first line structure 210 corresponds to the overlapping area 250 of the cross structure 200.

[0106] Then, as Figure 10 As shown, refer to Figure 6 , Figure 9 The entire second-line structure 220 is etched using dry or wet etching to expose the retained first-layer structure 240. The auxiliary layer 230 in the retained first-layer structure 240 can be removed by dry or wet etching, and the retained first-line structure 210 forms multiple independent initial mask patterns 211. In this embodiment, the multiple initial mask patterns 211 formed are arranged in multiple rows along the first direction D1.

[0107] In this embodiment, a first line structure 210 and a second line structure 220 are stacked above the target layer 100. By etching a portion of the second line structure 220 and the first line structure 210, only the overlapping area of ​​the first line structure 210 and the second line structure 220 is retained, resulting in a small feature size for the initial mask pattern 211. The first mask pattern 201 formed according to the initial mask pattern 211 formed in this embodiment (see reference) Figure 14 With a smaller size, in the subsequent second etching process, the target layer 100 can be etched according to the first mask pattern 201 to form a repeating structure with a higher repeating density and a smaller size.

[0108] Step S230: Form a second mask material layer, which covers the initial mask pattern and the top surface of the target layer exposed.

[0109] like Figure 11 As shown, refer to Figure 10 The second mask material can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form a second mask material layer 300, which covers the initial mask pattern 211 and the exposed top surface of the target layer 100.

[0110] Step S240: Remove part of the second mask material layer to form multiple second mask patterns extending along the first direction, while removing part of the structure of each initial mask pattern. The remaining part of the structure of each initial mask pattern forms a first mask pattern.

[0111] like Figure 12 As shown, refer to Figure 11 A third photomask 260 is formed on the top surface of the second photomask material layer 300, and the second photomask material layer 300 and the initial photomask pattern 211 are etched according to the third photomask 260. Figure 13 , Figure 14 As shown, the retained second mask material layer 300 forms a plurality of second mask patterns 310 extending along the first direction D1. The retained portion of the structure of each initial mask pattern 211 forms a first mask pattern 201. In a direction perpendicular to the first direction D1, any two adjacent second mask patterns 310 are separated by a first trench 320, and the first trench 320 exposes a portion of the top surface of the target layer 100.

[0112] like Figure 14 As shown, the projection of each second mask pattern 310 onto the target layer 100 is divided into multiple independently configured sub-patterns 311 by the projection of the first mask pattern 201 located in its extension direction onto the target layer 100. This is so that the target layer 100 can be etched according to the first mask pattern 201 and the second mask pattern 310 to form multiple independently configured active regions 111.

[0113] In this embodiment, multiple first mask patterns 201 and multiple second mask patterns 310 are formed simultaneously. The projection of each second mask pattern 310 onto the target layer 100 is divided into multiple independently arranged sub-patterns 311 by the projection of the first mask pattern 201 onto the target layer 100 located in its extending direction. Furthermore, the projection of the first mask pattern 201 onto the target layer 100 is located within the projection of the second mask pattern 310 onto the target layer 100. The arrangement and distribution of the first mask patterns 201 and second mask patterns 310 formed in this embodiment ensure that the target layer 100 is subsequently etched into multiple active regions 111 based on the first mask patterns 201 and second mask patterns 310.

[0114] Step S250: Perform the first etching on the target layer based on the second mask pattern.

[0115] like Figure 15 , refer to Figure 13In this embodiment, the target layer 100 is etched using the second mask pattern 310 as a mask. The portion of the target layer 100 exposed by the second mask pattern 310 is removed, and the remaining portion of the target layer 100 is etched to form multiple active strips 110 extending along the first direction D1. In a direction perpendicular to the first direction D1, adjacent active strips 110 are separated by a first shallow trench 120. The etching process for the first etching can be either dry etching or wet etching.

[0116] Step S260: Form a first isolation layer, the first isolation layer filling the first shallow trench.

[0117] Reference Figure 15 The second mask pattern 310 is removed by dry or wet etching, exposing the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310.

[0118] like Figure 16 As shown, in this embodiment, a first isolation layer 410 is formed by depositing a first isolation material using any one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The first isolation layer 410 fills the first shallow trench 120 and covers the first mask pattern 201 and the top surface of the active strip 110 exposed by the first mask pattern 201. The first isolation material may include silicon oxide, silicon nitride, or silicon oxynitride. Then, the top surface of the first isolation layer 410 is planarized by a chemical mechanical polishing (CMP) process, exposing the top surfaces of multiple first mask patterns 201, so that the active strip 110 can be etched secondly according to the first mask pattern 201.

[0119] Step S270: Perform a second etching on the target layer based on the first mask pattern.

[0120] like Figure 17 As shown, refer to Figure 16 The target layer 100 is etched a second time based on the first mask pattern 201. The following method can be used: remove the first mask pattern 201 and the part of the active strip 110 covered by the first mask pattern 201. The part of the active strip 110 that is retained forms a plurality of independently set active regions 111. The active regions 111 extend along the first direction D1. In the first direction D1, two adjacent active regions 111 are separated by a second shallow trench 130. The second shallow trench 130 extends the pattern of the first mask pattern 201 into the active strip 110.

[0121] Step S280: Fill the second shallow trench with the second insulating material to form the second insulating layer.

[0122] like Figure 18 As shown, refer to Figure 17 A second isolation layer 420 is formed by depositing a second isolation material using any one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The second isolation layer 420 fills the second shallow trench 130 and covers the first isolation layer 410. The second isolation material may include one of silicon oxide, silicon nitride, or silicon oxynitride, and the first isolation material and the second isolation material may be the same or different materials.

[0123] Then, as Figure 19 As shown, refer to Figure 18 The first isolation layer 410 and the second isolation layer 420 located above the top surface of the target layer 100 are etched away. The retained first isolation layer 410 and the second isolation layer 420 together form a shallow trench isolation structure 400. The top surface of the shallow trench isolation structure 400 is flush with the top surface of the active region 111.

[0124] In this embodiment, the target layer is etched into multiple independently set active regions, which reduces the difficulty of forming active regions and enables the formation of smaller active regions. This embodiment has lower requirements for the resolution accuracy of the photolithography process, reduces the process difficulty and process cost, and is suitable for forming highly integrated integrated circuits.

[0125] In this embodiment, the shallow trench isolation structure is formed through two different deposition processes. Different materials can be selected for filling the two depositions according to the depth-to-width ratio of the first and second shallow trenches, ensuring that both the first and second shallow trenches are filled with isolation material. This ensures that the formed shallow trench isolation structure has high density, structural stability, and good electrical isolation effect, which can better avoid short circuits in the active region and ensure that the semiconductor structure has good electrical performance. It also avoids the problem that complex trench shapes between active regions lead to filling difficulties, resulting in incomplete filling of some areas of the trench and reducing the isolation effect of the shallow trench isolation structure.

[0126] According to an exemplary embodiment, such as Figure 2 As shown, this embodiment adds the following steps compared to the above embodiment:

[0127] Step S290: Form multiple word lines, each word line extending along the fourth direction and passing through multiple active areas located in its extension direction, and the multiple word lines are set apart from each other.

[0128] The second direction D2 and the third direction D3 intersect at a first angle α1, and the first direction D1 and the fourth direction D4 intersect at a second angle α2. The relationship between the first angle α1 and the second angle α2 is as follows:

[0129]

[0130] The first included angle is α1, and the second included angle is α2.

[0131] like Figure 21 As shown, refer to Figure 20 When forming the word line 500, a word line mask is first formed, covering part of the active region 111 and part of the top surface of the shallow trench isolation structure 400. The word line mask extends along the fourth direction D4. The active region 111 and the shallow trench isolation structure 400 are etched according to the word line mask to form word line trenches. The word line trenches penetrate the active region 111 along the fourth direction D4, and each active region 111 is penetrated by two word line trenches. Then, the word line 500 is formed in the word line trenches.

[0132] Step S300: Form a bit line that covers the top surface of part of the active region and the top surface of part of the isolation structure. The bit line extends along the fifth direction, which is perpendicular to the fourth direction.

[0133] like Figure 21 As shown, refer to Figure 20 Multiple bit lines 600 are formed on the top surface of the active region 111 and the shallow trench isolation structure 400. Each bit line 600 extends along the fifth direction D5, and the multiple bit lines 600 are equally spaced on the fourth direction D4.

[0134] The length and arrangement of the active region formed in this embodiment can meet the process requirements of other electronic components. The word lines and bit lines formed in the patterned target layer in this embodiment, and the setting of word lines, bit lines and active regions meet the process requirements of DRAM memory.

[0135] According to an exemplary embodiment, this embodiment describes the implementation of step S220 above. During implementation, multiple initial mask patterns are formed on the top surface of the target layer, and the following steps are also included:

[0136] The setting directions of the first line structure 210 and the second line structure 220 to be formed are defined according to the target layer 100. This step is performed before the cross structure 200 is formed on the target layer 100.

[0137] Since this exemplary embodiment is described with respect to the process of forming an active region 111, in the semiconductor field, the process of manufacturing a DRAM memory typically includes forming a word line 500 that runs through the active region 111 after the formation of the active region 111.

[0138] In this embodiment, refer to Figure 21The subsequently formed character line 500 extends along the fourth direction D4. In a plane parallel to the top surface of the target layer 100, the first direction D1 and the fourth direction D4 intersect at a second included angle α2. In this embodiment, the second included angle α2 is an acute angle. For example, the second included angle α2 can be 50° to 85°. For instance, the second included angle α2 can be 50°, 53°, 56°, 59°, 63°, 66°, 69°, 74°, 75°, 77°, 79°, 81°, 83°, or 85°.

[0139] In this step, a coordinate system XOY is established with the fourth direction D4 of the character line 500 in the subsequent process as the X-axis and the first direction D1 of the active region 111 as the Y-axis. The coordinate system XOY established in this embodiment is an oblique coordinate system. Then, the extension direction of the first line structure 210 and the extension direction of the second line structure 220 to be formed are determined according to the coordinate system XOY.

[0140] In this embodiment, the extension direction of the first line structure 210 to be formed is defined as the second direction D2, and the extension direction of the second line structure 220 to be formed is defined as the third direction D3. The second direction D2 and the third direction D3 intersect at a first included angle α1. In this embodiment, the first included angle α1 is 70° to 95°. For example, the first included angle can be 70°, 72°, 75°, 77°, 79°, 82°, 85°, 88°, 90°, 92°, or 95°. Figure 22 As shown, the second direction D2 intersects the first direction D1 at an angle, and the second direction D2 also intersects the fourth direction D4 at an angle. The included angle between the second direction D2 and the fourth direction D4 is the third included angle α3, which is between 30° and 50°. For example, the third included angle α3 can be 30°, 32°, 34°, 36°, 37°, 39°, 41°, 45°, or 50°. Figure 22 As shown, the third direction D3 and the first direction D1 intersect at an angle, and the third direction D3 intersects at an angle with the fourth direction D4. The included angle between the third direction D3 and the fourth direction D4 is the fourth included angle α4, which is 30° to 50°. For example, the fourth included angle α4 can be 30°, 32°, 34°, 36°, 37°, 39°, 41°, 45°, or 50°.

[0141] The first included angle α1 is equal to the sum of the third included angle α3 and the fourth included angle α4. For example, if the first included angle α1 is 80 degrees and the third included angle α3 is 30°, then the fourth included angle α4 is 50°. In this embodiment, the third included angle α3 and the fourth included angle α4 are equal. For example, if the first included angle α1 is 82 degrees, the third included angle α3 is 41°, and the fourth included angle α4 is also 41°. Meanwhile, the relationship between the first included angle α1 and the second included angle α2 is as follows:

[0142]

[0143] In this embodiment, based on the extension direction of the active region to be formed and the extension direction of the word line in the subsequent word line process, the extension direction of the first line structure to be formed and the setting direction and angle of the second line structure are defined so that multiple initial mask patterns are arranged in multiple rows along the first direction, ensuring that the projection of the second mask pattern formed subsequently on the target layer can be divided into multiple independently set sub-patterns by the projection of the first mask pattern located in its extension direction on the target layer. The arrangement of the active regions formed by the first mask pattern and the second mask pattern meets the process requirements of DRAM memory.

[0144] According to an exemplary embodiment, this embodiment provides a semiconductor structure formed according to the fabrication method of the semiconductor structure in the above embodiments. The semiconductor structure of this embodiment can be a memory chip, which can be used in Dynamic Random Access Memory (DRAM). However, it can also be applied to Static Random-Access Memory (SRAM), flash EPROM, ferroelectric Random-Access Memory (FRAM), magnetic Random-Access Memory (MRAM), phase-change Random-Access Memory (PRAM), etc.

[0145] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0146] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0147] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0148] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0149] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0150] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide the target layer; Multiple first mask patterns are formed on the top surface of the target layer, and any two adjacent first mask patterns in the first direction are spaced apart. A plurality of second mask patterns are formed above the target layer, each second mask pattern extending along the first direction and spaced apart from each other, each second mask pattern at least covering a portion of the top surface of each first mask pattern located in its extending direction and a portion of the top surface of the target layer; The target layer is etched based on the second mask pattern; The target layer is etched a second time based on the first mask pattern.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Multiple first mask patterns are formed on the top surface of the target layer, including: A cross structure is formed on the target layer, the cross structure including an overlapping region; Remove part of the intersecting structure and retain part of the overlapping area; the retained overlapping area forms multiple initial mask patterns. Remove a portion of the structure from each initial mask pattern, and the remaining portion of the structure of each initial mask pattern forms the first mask pattern.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Forming a cross structure on the target layer includes: Multiple first line structures are formed, each of which extends along a second direction. In a direction perpendicular to the second direction, the multiple first line structures are spaced apart, and the first direction and the second direction intersect at an angle. Multiple second line structures are formed, with multiple second line structures located above the first line structure. The second line structures extend along a third direction. In a direction perpendicular to the third direction, multiple second line structures are spaced apart. The first direction intersects the third direction at an angle. Multiple first line structures and multiple second line structures together form the intersection structure, and the overlapping portions of the multiple first line structures and multiple second line structures form the overlapping region.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Multiple second mask patterns are formed above the target layer, including: A second mask material layer is formed, which covers the initial mask pattern and the exposed top surface of the target layer; A portion of the second mask material layer is removed to form a plurality of second mask patterns extending along the first direction. In a direction perpendicular to the first direction, any two adjacent second mask patterns are separated by a first trench.

5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The projection of each second mask pattern onto the target layer is divided into multiple independently configured sub-patterns by the projection of the first mask pattern onto the target layer located in its extension direction.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The target layer is etched based on the second mask pattern, including: The portion of the target layer exposed by the second mask pattern is removed, and the remaining portion of the target layer is etched to form multiple active strips extending along the first direction. In a direction perpendicular to the first direction, two adjacent active strips are separated by a first shallow trench.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The method further includes: A first isolation material is deposited to form a first isolation layer, which fills the first shallow trench and covers the first mask pattern and the top surface of the active strip exposed by the first mask pattern.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method further includes: The top surface of the first isolation layer is planarized to expose the top surfaces of multiple first mask patterns.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, A second etching is performed on the target layer based on the first mask pattern, including: The first mask pattern and the portion of the active strips covered by the first mask pattern are removed. The remaining portion of the active strips forms a plurality of independently configured active regions. The active regions extend along the first direction. In the first direction, two adjacent active regions are separated by a second shallow trench.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The method further includes: A second insulating material is filled into the second shallow trench to form a second insulating layer.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The method further includes: The first isolation layer and the second isolation layer above the top surface of the target layer are removed, and the retained first isolation layer and the second isolation layer together form a shallow trench isolation structure.

12. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The first insulating material and the second insulating material may be the same or different materials.

13. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The method further includes: Multiple word lines are formed, each word line extending along a fourth direction and penetrating multiple active regions located in its extension direction, and the multiple word lines are spaced apart from each other.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The second direction and the third direction intersect at a first angle, and the first direction and the fourth direction intersect at a second angle. The relationship between the first angle and the second angle is as follows: Wherein, the first included angle is α1, and the second included angle is α2.

15. A semiconductor structure, characterized in that, The semiconductor structure is fabricated according to the semiconductor structure fabrication method according to any one of claims 1 to 14.

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