A time-to-digital converter and time measurement method based on high-speed sequencing

Abstract

The application belongs to the technical field of circuit design, and discloses a time-to-digital converter based on high-speed sequencing and a time measurement method, which comprises a time measurement unit, a high-speed sequencing unit, a CPU control unit and a communication unit; the time measurement unit comprises a delay chain module, a decoding module, a coarse count correction module and a timestamp alignment module; the high-speed sequencing unit is used for receiving a calibration signal sent by the delay chain module to perform delay calibration; the CPU control unit is used for calibrating a fine timestamp range of a metastable state region in a coarse time count result extracted by the coarse count correction module, the decoding module decodes a to-be-measured pulse signal to obtain a calibration fine timestamp, the timestamp alignment module aligns the calibration fine timestamp with a center point of the fine timestamp range, and latches the coarse time count result, so that the time measurement of the to-be-measured pulse signal is completed; and the communication unit is used for receiving a time measurement result and transmitting the time measurement result to an upper computer. The application significantly shortens the power-on waiting time of the time-to-digital converter, and improves the time resolution of the converter.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of circuit design, and more particularly, to a time-to-digital converter based on high-speed sequencing and a time measurement method. BACKGROUND

[0002] The time-to-digital converter (TDC) for high-precision time measurement is widely used in high-end medical instruments, laser radars, quantum communications, high-energy physics experiments, aerospace, and other cutting-edge scientific research fields. In particular, in the field of high-end medical instruments, the positron emission tomography system (PET), the time precision plays a decisive role in the performance of the system. When the time resolution reaches 100 ps, the image signal-to-noise ratio of the TOF-PET system based on time-of-flight measurement can be improved by at least 5 times. With the continuous advancement of semiconductor technology, modern FPGAs have a large number of logic units to provide users with function customization. The way of implementing a time-to-digital converter based on FPGA has become the mainstream. The traditional time-to-digital converter based on unordered multiphase method uses a soft core MCU to allow the phase calibration of the delay unit to be implemented in a software language. Although it can achieve picosecond-level time precision, it is slow and can only be performed in series. In particular, in order to further improve the time precision of the system, the actual high-precision time-to-digital converter design often requires multiple time measurement channels to improve performance. The long phase calibration time of a single channel will lead to poor stability of the sequencing result. At the same time, in small portable medical devices such as wearable brain PET, if the system needs to go through a long initialization time after power-on, the patient or test subject will have to wait for a long time before they can use it, resulting in a poor user experience. SUMMARY

[0003] In view of the above defects or improvement needs of the prior art, the present application provides a time-to-digital converter based on high-speed sequencing and a time measurement method, which significantly shortens the power-on waiting time of the time-to-digital converter and improves the time resolution of the converter.

[0004] To achieve the above object, according to one aspect of the present application, a time-to-digital converter based on high-speed sequencing is provided, which comprises a high-speed sequencing unit, a time measurement unit, a CPU control unit and a communication unit, wherein: the time measurement unit comprises a delay chain module, a decoding module, a coarse count correction module and a time stamp alignment module; the high-speed sequencing unit is in information interaction with the delay chain module and the decoding module, and is used for receiving a calibration signal sent by the delay chain module, calibrating a delay unit in the delay chain module based on a phase of the calibration signal, and sending calibration information of the delay unit to the decoding module; the coarse count correction module is used for extracting a coarse time count result of a to-be-measured pulse signal, and transmitting the coarse time count result to the CPU control unit; the CPU control unit is used for calibrating a fine time stamp range of a metastable state region in the coarse time count result; the decoding module is used for decoding and calibrating a fine time of the to-be-measured pulse signal according to the calibration information of the delay unit, to obtain a calibrated fine time stamp; the time stamp alignment module is used for aligning the calibrated fine time stamp with a center point of the fine time stamp range of the metastable state region, and latching the coarse time count result, to complete time measurement of the to-be-measured pulse signal; and the communication unit is used for receiving a time measurement result and transmitting the time measurement result to an upper computer.

[0005] Preferably, the high-speed sequencing unit comprises a searching initial reference module, an initial reference statistics module, a searching alternative reference module, an alternative reference statistics module, a type calibration module, a phase calibration module and an access control module, wherein: the access control module is in communication connection with the searching initial reference module, the initial reference statistics module, the searching alternative reference module, the alternative reference statistics module, the type calibration module and the phase calibration module, to realize calculation and data sharing; the searching initial reference module is used for selecting a judgment delay reference in a calibration signal; the searching alternative reference module is used for selecting at least one judgment delay alternative reference in the calibration signal; the type calibration module is used for calibrating a type of the calibration signal; and the phase calibration module is used for judging a calibration result of the type calibration module and correcting an incorrect calibration result.

[0006] Preferably, the initial reference module, the initial reference statistics module, the searching alternative reference module and the alternative reference statistics module are connected in series in sequence, or the initial reference module and the searching alternative reference module are connected in parallel.

[0007] Preferably, the searching initial reference module and the searching alternative reference module firstly calculate duty cycles of all delay units, and set delay units with duty cycles of 48% to 52% or 49% to 51% as references.

[0008] Preferably, the time measurement unit further comprises an interpolation module for interpolating the high-speed clock in the delay chain module so that the duty cycle of the delay unit is within 50% ± 10%.

[0009] Preferably, the phase calibration module or the CPU control unit further comprises sorting the delay information of the delay unit.

[0010] Preferably, the high-speed sequencing unit and the time measurement unit are connected in one-to-one or one-to-many communication.

[0011] Preferably, the communication unit transmits the time measurement results to the host computer using USB, UART or SPI communication protocol.

[0012] Another aspect of the present application provides a time measurement method using the above-mentioned time-to-digital converter, the method comprising: inputting a calibration signal into the time measurement unit; the high-speed sequencing unit receiving the calibration signal input by the delay chain module, calibrating the delay of the delay unit in the delay chain module, and sending the calibration information to the decoding module; inputting the pulse signal to be measured into the time measurement unit; the coarse counting correction module extracting the coarse time count result of the pulse signal to be measured and transmitting it to the CPU control unit; the CPU control unit calibrating the fine time stamp range of the metastable state region in the coarse time count result; the decoding module decoding and calibrating the fine time of the pulse signal to be measured according to the calibration information of the delay unit to obtain the calibrated fine time stamp; the time stamp alignment module aligning the calibrated fine time stamp with the center point of the fine time stamp range of the metastable state region and latching the coarse time count result, completing the time measurement of the pulse signal to be measured.

[0013] Overall, compared with the prior art, the time-to-digital converter and time measurement method based on high-speed sequencing provided by the present application mainly have the following beneficial effects:

[0014] 1. The high-speed sequencing unit of the present application first calibrates the delay of the delay unit in the time measurement unit and sends the calibration information to the time measurement unit. The decoding module in the time measurement unit can decode and calibrate the fine time of the pulse signal to be measured according to the calibration information of the delay unit, and the CPU control unit can calibrate the fine time stamp range of the metastable state region in the coarse time count result, thereby quickly realizing time measurement through fine time stamp alignment, significantly shortening the power-on waiting time, improving the robustness of the time-to-digital converter while ensuring high time resolution, reducing the window period of system power-on, and improving the system function experience.

[0015] 2. The high-speed sequencing unit and the time measurement unit in the present application can be connected in one-to-one or one-to-many mode, facilitating multi-channel time fast measurement.

[0016] 3. The high-speed sequencing unit of the present application is provided with a module for searching an initial reference and a module for searching a substitute reference, which facilitates the selection and determination of the reference, and can be connected in series or in parallel, and when connected in parallel, the sequencing time can be further shortened.

[0017] 4. The time measurement unit further comprises an interpolation module for interpolating the high-speed clock in the delay chain module, so that the duty cycle distribution of the delay unit is within 50% ± 10%, ensuring that the delay distribution of the delay unit can be more evenly distributed throughout the clock cycle. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of the time-to-digital converter based on high-speed sequencing of the embodiment of the present application.

[0019] Figure 2 is a structural schematic diagram of the high-speed sequencing unit of the embodiment of the present application.

[0020] Figure 3 is a structural schematic diagram of the TDC constructed by the high-speed sequencing unit and the time measurement unit in a one-to-many coupling manner of the embodiment of the present application.

[0021] Figure 4 is a structural schematic diagram of the TDC constructed by the high-speed sequencing unit and the time measurement unit in a one-to-one coupling manner of the embodiment of the present application.

[0022] Figure 5 is a flowchart of the type misjudgment of the phase calibration module of the embodiment of the present application.

[0023] Figure 6 is a time measurement method of the time-to-digital converter of the embodiment of the present application.

[0024] In all the drawings, the same reference signs are used to represent the same elements or structures, wherein:

[0025] 1 - high-speed sequencing unit; 2 - time measurement unit; 3 - CPU control unit; 4 - communication unit; 5 - delay chain module; 6 - decoding module; 7 - coarse count correction module; 8 - time stamp alignment module; 9 - upper computer; 10 - pulse signal to be measured; 11 - module for searching an initial reference; 12 - initial reference statistics module; 13 - module for searching a substitute reference; 14 - substitute reference statistics module; 15 - type calibration module; 16 - phase calibration module; 17 - access control module. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] This invention provides a time-to-digital converter based on high-speed sequencing, such as... Figure 1 As shown, the time-to-digital converter mainly includes a high-speed sequencing unit 1, a time measurement unit 2, a CPU control unit 3, and a communication unit 4, as detailed below.

[0028] The time measurement unit 2 includes a delay chain module 5, a decoding module 6, a coarse counting correction module 7, and a timestamp alignment module 8. The high-speed sequencing unit 1 interacts with the delay chain module 5 and the decoding module 6 to receive the calibration signal sent by the delay chain module 5. The high-speed sequencing unit 1 calibrates the delay units in the delay chain module 5 based on the phase of the calibration signal and sends the calibration information of the delay units to the decoding module 6.

[0029] Specifically, the high-speed sequencing unit 1 is used to calibrate the delay information of different delay units on one or more delay chain modules 5. For example... Figure 2 As shown, the high-speed sequencing unit 1 includes seven sub-modules: an initial reference finding module 11, an initial reference statistics module 12, an alternative reference finding module 13, an alternative reference statistics module 14, a type calibration module 15, a phase calibration module 16, and an access control module 17. The sub-module architecture can be organized to complete the delay calibration in either a serial or parallel manner. In a serial manner, the next module can only start execution after the previous module has completed its calculation to ensure the correctness of data access. In a parallel manner, the calculation of the type calibration module and the alternative reference statistics module can be performed simultaneously after the alternative reference is found. Compared with the serial manner, the parallel method can reduce the sequencing time by 1 / 3. The calibrated delay unit will be used as the benchmark for the timestamp measurement of the actual signal under test.

[0030] like Figure 2The 7 sub-modules of the high-speed sequencing unit 1 are connected in series, the access control module 17 contains a double-port RAM, and the double-port RAM provides a storage medium for the intermediate results of data calculation of the initial reference module 11, the initial reference statistics module 12, the alternative reference searching module 13, the alternative reference statistics module 14, the type calibration module 15 and the phase calibration module 16. Meanwhile, the access control module 17 monitors the working states of the remaining 6 modules in real time, enables the access control of the double-port RAM by the next module after the completion of the calculation of the current module, and ensures that the access does not conflict. The whole sequencing unit can accept the reset control of the CPU control unit, and after the completion of the sequencing of a time measurement unit and the acceptance of the reset signal of the CPU control unit, the high-speed sequencing unit enters the reset state, and the reuse of the modules can be realized by the high-speed sequencing of a new time measurement unit.

[0031] Among the 7 sub-modules of the high-speed sequencing unit, the initial reference module 11, the initial reference statistics module 12, the alternative reference searching module 13, the alternative reference statistics module 14, the type calibration module 15 and the phase calibration module 16 are connected with the access control module 17 to realize the calculation and data sharing of the statistics, reference calibration, type calibration and phase calibration information. The functions of the modules are realized by the registers and three-stage state machines.

[0032] The phase calibration module 16 contains the processing of the type misjudgment algorithm, which is used to correct the error results of the type calibration module, and can selectively configure whether to realize the sorting of the delay information in the phase calibration module. If the sorting is not selected in the phase calibration module 16, the sorting can be performed in the CPU control unit. Figure 5 It is a schematic diagram of a type misjudgment correction algorithm according to the application, as shown in Figure 5 After the completion of the edge calculation calibration, the delay values of the adjacent delay units are calculated one by one. If the calculated delay value exceeds the theoretical maximum value, the type misjudgment correction is started, and the calculation result of another type is used as the new edge value of the delay unit. Until the calculation of the delay values between all adjacent delay units is completed, the type misjudgment correction is ended.

[0033] The selection criteria of the reference in the initial reference module 11 and the alternative reference searching module 13 are the duty cycle closest to 50%. The duty cycle of all delay units can be calculated to find the delay unit with the duty cycle closest to 50% as the reference. Alternatively, the delay unit with the duty cycle in the acceptable error range of 49%-51% or 48%-52% can be determined as the reference. The latter method can further save the time of high-speed sequencing.

[0034] The time measurement unit 2 is used to provide a time delay chain input for the high-speed sequencing unit 1, and the time delay calibration information obtained is used as a time delay lookup table of the decoding module 6. Meanwhile, the fine time stamp in the metastable state interval of the coarse count is calibrated and corrected, and when the actual pulse signal 10 arrives, the final time measurement result is transmitted to the communication unit through fine count decoding, coarse time correction and time stamp alignment. Specifically, the coarse count correction module 7 is used to extract the coarse time count result of the pulse signal to be measured and transmit it to the CPU control unit; the CPU control unit 3 is used to calibrate the fine time stamp range of the metastable state interval in the coarse time count result; the decoding module 6 is used to decode and calibrate the fine time of the pulse signal to be measured according to the calibration information of the time delay unit, and obtain the calibrated fine time stamp; and the time stamp alignment module 8 is used to align the calibrated fine time stamp with the center point of the fine time stamp range of the metastable state interval, and latch the coarse time count result, thereby completing the time measurement of the pulse signal to be measured.

[0035] The high-speed sequencing unit 1 and the time measurement unit 2 are coupled in a one-to-one or one-to-many manner to realize the construction of the TDC. As shown in FIG. 2, Figure 3 The high-speed sequencing unit 1 and the time measurement unit 2 are coupled in a one-to-many manner to realize the construction of the TDC, and the high-speed sequencing unit completes the high-speed sequencing task of each time measurement unit under the control of the CPU control unit 3. As shown in FIG. 3, Figure 4 The high-speed sequencing unit 1 and the time measurement unit 2 are coupled in a one-to-one manner to realize the construction of the TDC, and each coupled unit can perform high-speed sequencing at the same time when the system is powered on. This method occupies a large amount of resources, but can further reduce the sequencing time of multiple channels. This method can be used when the hardware resources are sufficient or the number of channels is small.

[0036] The time measurement unit 2 further comprises an interpolation module (not shown in the figure) for interpolating the high-speed clock in the time delay chain module 5, so that the standard used is that the duty cycle distribution of the time delay unit is within 50%±10%.

[0037] The CPU control unit 3 is used to control the switching and interaction of the working states of each unit to ensure the stable and correct operation of the time-to-digital converter system. After the sampling signal data of the time measurement unit is sorted and corrected, the result is written into the corresponding module in the time measurement unit. The CPU control unit is composed of a customized MCU and a customized peripheral, which is interconnected with the high-speed sequencing unit and the time measurement unit to realize signal and process control management and data transmission, and at the same time, the algorithm calculation and output of the coarse count correction are completed.

[0038] The communication unit 4 is configured to package and synchronously upload the time measurement results of each time measurement unit to the host computer 9. Specifically, the communication unit can use USB, UART or SPI communication protocol to transmit the time measurement results to the host computer.

[0039] Another aspect of the present application provides a time measurement method of the time-to-digital converter as described above, which comprises the following steps: Figure 6 as shown in the drawings, the method comprises:

[0040] S1: input a calibration signal into the time measurement unit;

[0041] S2: the high-speed sequencing unit receives the calibration signal input by the delay chain module, realizes the delay calibration of the delay units in the delay chain module, and sends the calibration information to the decoding module; specifically, the high-speed sequencing unit calibrates different delay units on the delay chain module according to the latching result of the delay chain module, and sends the calibrated result to the decoding module of the time measurement unit.

[0042] S3: input the to-be-measured pulse signal into the time measurement unit;

[0043] S4: the coarse counting correction module extracts the coarse time counting result of the to-be-measured pulse signal, and transmits it to the CPU control unit;

[0044] S5: the CPU control unit calibrates the fine time stamp range of the metastable state region in the coarse time counting result;

[0045] S6: the decoding module decodes and calibrates the fine time of the to-be-measured pulse signal according to the calibration information of the delay units, and obtains the calibrated fine time stamp;

[0046] S7: the time stamp alignment module aligns the calibrated fine time stamp with the center point of the fine time stamp range of the metastable state region, and latches the coarse time counting result, thereby completing the time measurement of the to-be-measured pulse signal.

[0047] Those skilled in the art will readily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A time-to-digital converter based on high-speed sequencing, characterized in that, The time-to-digital converter comprises a high-speed sequencing unit, a time measurement unit, a CPU control unit and a communication unit, wherein: The time measurement unit comprises a delay chain module, a decoding module, a coarse count correction module and a timestamp alignment module. The high-speed sequencing unit exchanges information with the delay chain module and the decoding module, receives a calibration signal sent by the delay chain module, calibrates the delay units in the delay chain module based on the phase of the calibration signal, and sends the calibration information of the delay units to the decoding module. The coarse count correction module is used to extract the coarse time count result of the pulse signal to be measured and transmit it to the CPU control unit. The CPU control unit is used to calibrate the fine timestamp range of the metastable state region in the coarse time count result. The decoding module is used to decode and calibrate the fine time of the pulse signal to be measured according to the calibration information of the delay units to obtain a calibrated fine timestamp. The timestamp alignment module is used to align the calibrated fine timestamp with the center point of the fine timestamp range of the metastable state region, latch the coarse time count result, and complete the time measurement of the pulse signal to be measured. The communication unit is used to receive the time measurement result and transmit it to the upper computer.

2. The time-to-digital converter of claim 1, wherein, The high-speed sequencing unit comprises a search initial reference module, an initial reference statistics module, a search alternative reference module, an alternative reference statistics module, a type calibration module, a phase calibration module and an access control module, wherein: The access control module is in communication connection with the search initial reference module, the initial reference statistics module, the search alternative reference module, the alternative reference statistics module, the type calibration module and the phase calibration module to realize calculation and data sharing; the search initial reference module is used to select a judgment delay reference in the calibration signal; the search alternative reference module is used to select at least one judgment delay alternative reference in the calibration signal; the type calibration module is used to calibrate the type of the calibration signal; and the phase calibration module is used to judge the calibration result of the type calibration module and correct the wrong calibration result.

3. Time-to-digital converter according to claim 1 or 2, characterized in that, The initial reference module, the initial reference statistics module, the search alternative reference module and the alternative reference statistics module are connected in series, or the initial reference module and the search alternative reference module are connected in parallel.

4. The time-to-digital converter of claim 3, wherein, The search initial reference module and the search alternative reference module first calculate the duty cycle of all delay units, and set the delay units with a duty cycle of 48% to 52% as the reference.

5. The time-to-digital converter of claim 4, wherein, The search initial reference module and the search alternative reference module first calculate the duty cycle of all delay units, and set the delay units with a duty cycle of 49% to 51% as the reference.

6. The time-to-digital converter of claim 1, wherein, The time measurement unit further comprises an interpolation module for interpolating the high-speed clock in the delay chain module, so that the duty cycle of the delay units is distributed within 50%±10%.

7. The time-to-digital converter of claim 2, wherein, The phase calibration module or the CPU control unit further comprises sorting the delay information of the delay units.

8. The time-to-digital converter of claim 1, wherein, The high-speed sequencing unit and the time measurement unit are in one-to-one or one-to-many communication connection.

9. The time-to-digital converter of claim 1, wherein, The communication unit transmits the time measurement result to a host computer using a USB, UART or SPI communication protocol.

10. A time measurement method using the time-to-digital converter according to any one of claims 1 to 9, characterized by, The method comprises inputting a calibration signal into the time measurement unit; The high-speed sequencing unit receives the calibration signal input by the delay chain module, calibrates the delay of the delay unit in the delay chain module, and sends the calibration information to the decoding module; The to-be-measured pulse signal is input into the time measurement unit; The coarse counting correction module extracts the coarse time counting result of the to-be-measured pulse signal and transmits it to the CPU control unit; The CPU control unit calibrates the fine time stamp range of the metastable state region in the coarse time counting result; The decoding module decodes and calibrates the fine time of the to-be-measured pulse signal according to the calibration information of the delay unit to obtain a calibrated fine time stamp; The time stamp alignment module aligns the calibrated fine time stamp with the center point of the fine time stamp range of the metastable state region, and latches the coarse time counting result, thereby completing the time measurement of the to-be-measured pulse signal.

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