Electronic device and method of manufacturing the same

Abstract

The present disclosure provides an electronic device, comprising: a substrate; a first gate line disposed on the substrate; a first insulating layer disposed on the first gate line; a second insulating layer disposed on the first insulating layer; an oxide semiconductor layer disposed between the first insulating layer and the second insulating layer; a second gate line disposed on the second insulating layer; a third insulating layer disposed on the second gate line; and a first conductive component disposed on the third insulating layer, wherein the first conductive component electrically connects the first gate line through the first insulating layer, the second insulating layer and the third insulating layer, and electrically connects the second gate line through the third insulating layer. The present disclosure also provides a manufacturing method of an electronic device.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device in which the gate line of a dual-gate transistor is connected by a conductive component. Background Technology

[0002] LTPO circuits include LTPS transistors and IGZO transistors. Since the indium gallium zinc oxide (IGZO) transistors in LTPO circuits have low leakage current characteristics, replacing the transistors that need to be kept on for a long time with IGZO transistors can improve the power saving effect of LTPO circuits.

[0003] However, since the electron mobility of IGZO transistors is lower than that of low-temperature polysilicon (LTPS) transistors, improving the driving speed of IGZO transistors plays an important role in the overall performance of LTPO circuits. Summary of the Invention

[0004] According to one embodiment of this disclosure, an electronic device is provided, comprising: a substrate; a first gate line disposed on the substrate; a first insulating layer disposed on the first gate line; a second insulating layer disposed on the first insulating layer; an oxide semiconductor layer disposed between the first insulating layer and the second insulating layer; a second gate line disposed on the second insulating layer; a third insulating layer disposed on the second gate line; and a first conductive component disposed on the third insulating layer, wherein the first conductive component passes through the first insulating layer, the second insulating layer and the third insulating layer and is electrically connected to the first gate line, and passes through the third insulating layer and is electrically connected to the second gate line.

[0005] According to an embodiment of this disclosure, a method for manufacturing an electronic device is provided, comprising: providing a substrate; forming a first gate line on the substrate; forming a first insulating layer on the first gate line; forming an oxide semiconductor layer on the first insulating layer; forming a second insulating layer on the oxide semiconductor layer; forming a second gate line on the second insulating layer; forming a third insulating layer on the second gate line; penetrating the third insulating layer to expose a portion of the second gate line; penetrating the first insulating layer, the second insulating layer, and the third insulating layer to expose a portion of the first gate line; and forming a first conductive component on the third insulating layer, the portion of the first gate line, and the portion of the second gate line, such that the first conductive component electrically connects the first gate line and the second gate line. Attached Figure Description

[0006] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of this disclosure.

[0007] Figure 1 This is a top view of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 This is a rear view of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 3 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 4 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 5 This is a top view of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 6 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 7 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure;

[0014] Figure 8 This is a top view of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 9 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure;

[0016] Figure 10 This is a circuit diagram of an electronic device according to an embodiment of the present disclosure;

[0017] Figure 11 This is a circuit diagram of an electronic device according to an embodiment of the present disclosure;

[0018] Figures 12-14 This is a cross-sectional view of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0019] [Symbol Explanation]

[0020] 10: Electronic devices

[0021] 12:Substrate

[0022] 12a: Active region

[0023] 12b: Surrounding Area

[0024] 14: First insulating layer

[0025] 16: First semiconductor layer

[0026] 18: Second insulating layer

[0027] 20: Gate

[0028] 22: Third insulation layer

[0029] 24: First metal layer

[0030] 24a, 24a': The first portion of the first metal layer

[0031] 24b, 24b': The second part of the first metal layer

[0032] 24c: The third part of the first metal layer

[0033] GL1: First gate line

[0034] GL1b, GL1d: Ends of the first gate line

[0035] 26: Fourth Insulation Layer

[0036] 28: Oxide semiconductor layer

[0037] 30: Fifth Insulation Layer

[0038] 32: Second metal layer

[0039] 32a, 32a': The first part of the second metal layer

[0040] 32b, 32b': The second part of the second metal layer

[0041] 32c, 32c': The third part of the second metal layer

[0042] GL2: Second gate line

[0043] GL2b, GL2d: Ends of the second gate line

[0044] 34: Sixth Insulation Layer

[0045] 36: Third metal layer

[0046] 36a, 36a': The first part of the third metal layer

[0047] 36b, 36b': The second part of the third metal layer

[0048] 36c: The third part of the third metal layer

[0049] CE, CE': Conductive component

[0050] 38: Seventh Insulation Layer

[0051] CL: Connecting cable

[0052] 40: Fourth metal layer

[0053] 42: Transistor

[0054] 44: Transistor

[0055] 44a: Transistor

[0056] 46,48,50,52: Opening

[0057] 54: Drive Circuit

[0058] 60: Signal

[0059] 62: Adapter impedance

[0060] 64: Photoresist layer

[0061] 66: Patterned photoresist layer

[0062] 68: First Opening

[0063] 70: Second opening

[0064] 72: Third opening

[0065] 74: Fourth opening

[0066] S1: Spacing of the third opening

[0067] S2: Spacing of the fourth opening

[0068] S3: Spacing between the third and fourth openings

[0069] T1: Thickness of the first gate line

[0070] T2: Thickness of the second gate line

[0071] T3: Thickness of the connecting wire

[0072] W1: Width of the first opening

[0073] W2: Width of the second opening

[0074] W3: Width of the third opening

[0075] W4: Width of the fourth opening

[0076] Wa: Width of the first gate line

[0077] Wb: Width of the second gate line

[0078] Wc: Width of the connecting line Detailed Implementation

[0079] The following disclosure provides many different embodiments to implement the various features of this invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if the embodiments of this disclosure describe a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or it may include embodiments where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact.

[0080] It should be understood that additional operational steps may be performed before, between, or after the method, and in other embodiments of the method, some operational steps may be replaced or omitted.

[0081] Furthermore, spatially related terms may be used, such as "below," "lower," "above," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more components or features in the illustrations and another component or feature(s). These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 45 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn. In some embodiments of this disclosure, terms related to engagement or connection, such as "connection" or "interconnection," unless specifically defined, may refer to two structures being in direct contact, or they may refer to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms related to engagement or connection may also include cases where both structures are movable or both structures are fixed.

[0082] In the specification, the terms "about", "approximately", "roughly", "generally", and "substantially" usually indicate a range of a characteristic value within ±15%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a given value.

[0083] It should be understood that although the terms "first," "second," "third," etc., are used herein to describe different components, parts, regions, layers, and / or sections, these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the technology of this disclosure, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section.

[0084] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art in connection with this disclosure. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.

[0085] Please see Figures 1-3 According to one embodiment of the present disclosure, an electronic device 10 is provided. Figure 1 This is a top view of the electronic device 10. Figure 2 This is a rear view of the electronic device 10. Figure 3 This is a cross-sectional view of electronic device 10.

[0086] like Figure 3 As shown, the electronic device 10 includes a substrate 12, a first insulating layer 14, a first semiconductor layer 16, a second insulating layer 18, a gate 20, a third insulating layer 22, a first metal layer 24, a fourth insulating layer 26, an oxide semiconductor layer 28, a fifth insulating layer 30, a second metal layer 32, a sixth insulating layer 34, a third metal layer 36, a seventh insulating layer 38, and a fourth metal layer 40. The substrate 12 includes an active region 12a and a peripheral region 12b adjacent to the active region 12a. The first insulating layer 14 is disposed on the substrate 12. The first semiconductor layer 16 is disposed on the first insulating layer 14 and located in the peripheral region 12b of the substrate 12. The second insulating layer 18 is disposed on the first insulating layer 14 and covers the first semiconductor layer 16. Figure 3In this structure, transistor 42 is located in the peripheral region 12b of substrate 12. Transistor 42 may include a first semiconductor layer 16 (active layer) and a gate 20. The gate 20 is disposed on a second insulating layer 18, relative to the first semiconductor layer 16. A third insulating layer 22 is disposed on the second insulating layer 18 and covers the gate 20. A first metal layer 24 is disposed on the third insulating layer 22. The first metal layer 24 includes a first portion 24a, a second portion 24b, and a third portion 24c. The first portion 24a is located in the active region 12a of substrate 12, the second portion 24b is located in the peripheral region of substrate 12 and connected to the first portion 24a, and the third portion 24c is located in the peripheral region 12b of substrate 12 and separated from the second portion 24b. A fourth insulating layer 26 is disposed on the third insulating layer 22 and covers the first metal layer 24. The fourth insulating layer 26 has an opening 46. Figure 3 In this embodiment, there are two openings 46. In some embodiments, the number of openings 46 may include other numbers, such as one or more. An oxide semiconductor layer 28 is located in the active region 12a of the substrate 12 and is disposed on the fourth insulating layer 26. A fifth insulating layer 30 is disposed on the fourth insulating layer 26 and covers the oxide semiconductor layer 28. The fifth insulating layer 30 has openings 48. Figure 3 In this embodiment, there are two openings 48. In some embodiments, the number of openings 48 may include other numbers, such as one or more. A second metal layer 32 is disposed on the fifth insulating layer 30. The second metal layer 32 includes a first portion 32a and a second portion 32b, wherein the first portion 32a is located in the active region 12a of the substrate 12, and the second portion 32b is located in the peripheral region 12b of the substrate 12 and is connected to the first portion 32a. Figure 3 In this embodiment, transistor 44 is disposed on the active region 12a of substrate 12. In some embodiments, transistor 44 may be a dual-gate transistor. Transistor 44 may include an oxide semiconductor layer 28, which may include indium gallium zinc oxide (IGZO). A first gate line GL1 may include a first portion 24a and a second portion 24b of a first metal layer 24, and a second gate line GL2 may include a first portion 32a and a second portion 32b of a second metal layer 32. The first gate line GL1 and the second gate line GL2 can be used to provide a gate signal to transistor 44. Furthermore, the first gate line GL1 may serve as the bottom gate of transistor 44, and the second gate line GL2 may serve as the top gate of transistor 44, but this is not a limitation. A sixth insulating layer 34 is disposed on the fifth insulating layer 30 and covers the second metal layer 32. The sixth insulating layer 34 has an opening 50. Figure 3 In this embodiment, the number of openings 50 is two. In some embodiments, the number of openings 50 may include other numbers, such as one or more than two. Figure 3In the middle, opening 50 overlaps with opening 46 and opening 48. The sixth insulating layer 34 further includes an opening 52 adjacent to opening 50. Figure 3 In this embodiment, there are two openings 52. In some embodiments, the number of openings 52 may include other numbers, such as one or more. A third metal layer 36 is disposed on the sixth insulating layer 34. The third metal layer 36 includes a first portion 36a, a second portion 36b, and a third portion 36c. In some embodiments, the conductive component CE may be the first portion 36a of the third metal layer 36, and the conductive component CE may pass through the fourth insulating layer 26, the fifth insulating layer 30, and the sixth insulating layer 34 to be electrically connected to the second portion 24b of the first metal layer 24, and pass through the sixth insulating layer 34 to be electrically connected to the second portion 32b of the second metal layer 32. More specifically, in Figure 3 In this embodiment, the conductive component CE is electrically connected to the first gate line GL1 via openings 46, 48, and 50, and electrically connected to the second gate line GL2 via opening 52. The connecting line CL is connected to the first portion 36a of the third metal layer 36, and is also electrically connected to the third portion 24c of the first metal layer 24. In this embodiment, the connecting line CL can be the second portion 36b of the third metal layer 36, but is not limited thereto. The third portion 36c of the third metal layer 36 serves as the drain / source of the transistor 42, electrically connecting the first semiconductor layer 16 and the third portion 24c of the first metal layer 24. A seventh insulating layer 38 is disposed on the sixth insulating layer 34 and covers the third metal layer 36. A fourth metal layer 40 is disposed on the seventh insulating layer 38, located in the peripheral region 12b of the substrate 12, relative to the position of the third portion 24c of the first metal layer 24. The driving circuit 54 is disposed in the peripheral region 12b of the substrate 12. The driving circuit 54 may be, for example, a gate on panel (GOP). Figure 3 In this circuit, the driving circuit 54 may include a transistor 42. A connecting line CL may electrically connect the driving circuit 54 to the conductive component CE.

[0087] It should be noted that the third metal layer 36 referred to here refers to the layer position relationship or formation sequence, and is not limited to being formed in the same process or using the same material. That is to say, the third metal layer 36 is located above the first metal layer 24 and the second metal layer 32, or the third metal layer 36 is formed after the first metal layer 24 and the second metal layer 32. Different parts of the third metal layer 36 can be formed through different processes or with different materials. For example, the material of the first part 36a of the third metal layer 36 can be different from that of the second part 36b of the third metal layer 36, or the first part 36a and the second part 36b of the third metal layer 36 can be formed in different processes.

[0088] In some embodiments, substrate 12 may include a rigid substrate, such as a glass substrate, but this disclosure is not limited thereto, and other suitable rigid substrate materials are also applicable to this disclosure. In some embodiments, substrate 12 may include a flexible substrate, such as a polyimide (PI) substrate, but this disclosure is not limited thereto, and other suitable flexible substrate materials are also applicable to this disclosure.

[0089] In some embodiments, the first insulating layer 14, the second insulating layer 18, the third insulating layer 22, the fourth insulating layer 26, the fifth insulating layer 30, the sixth insulating layer 34, and the seventh insulating layer 38 may include organic insulating materials or inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but this disclosure is not limited thereto, and other suitable organic or inorganic insulating materials are also applicable to this disclosure.

[0090] In some embodiments, the first semiconductor layer 16 may include low-temperature polycrystalline silicon (LTPS), but this disclosure is not limited thereto, and other suitable semiconductor materials are also applicable. In some embodiments, when the material selected for the first semiconductor layer 16 is low-temperature polycrystalline silicon, the transistor 42 is a low-temperature polycrystalline silicon (LTPS) transistor. In some embodiments, the gate 20, the first metal layer 24, the second metal layer 32, and the fourth metal layer 40 may include molybdenum, aluminum, copper, or titanium, but this disclosure is not limited thereto, and other suitable conductive materials are also applicable. In some embodiments, the oxide semiconductor layer 28 may include indium gallium zinc oxide (IGZO), but this disclosure is not limited thereto, and other suitable semiconductor or oxide semiconductor materials are also applicable. In some embodiments, when the material selected for the oxide semiconductor layer 28 is indium gallium zinc oxide, the transistor 44 is an indium gallium zinc oxide (IGZO) dual-gate transistor. In some embodiments, the third metal layer 36 may include molybdenum, aluminum, copper, titanium or combinations thereof, such as molybdenum / aluminum / molybdenum, titanium / aluminum / titanium or titanium / aluminum / molybdenum, but this disclosure is not limited thereto, and other suitable conductive materials are also applicable to this disclosure.

[0091] In some embodiments, the conductivity of the material of the connecting line CL may be greater than the conductivity of the material of the first gate line GL1 and / or the material of the second gate line GL2. For example, in the selection of materials, the first metal layer 24 and the second metal layer 32 may be made of molybdenum, and the third metal layer 36 may be made of aluminum, which has better conductivity. Therefore, the signal conduction effect can be improved by adjusting the material of the connecting line CL.

[0092] Please see Figure 1 , Figure 2 , Figure 4This describes the configuration of another transistor 44a in electronic device 10 and its electrical connections with various components. Figure 4 In, similar to Figure 3 The disclosed portions will not be repeated here. The first metal layer 24 includes a first portion 24a' and a second portion 24b', wherein the first portion 24a' is located in the active region 12a of the substrate 12, and the second portion 24b' is located in the peripheral region 12b of the substrate 12 and is connected to the first portion 24a'. The oxide semiconductor layer 28 is located in the active region 12a of the substrate 12. The second metal layer 32 includes a first portion 32a', a second portion 32b', and a third portion 32c', wherein the first portion 32a' is located in the active region 12a of the substrate 12, the second portion 32b' is located in the peripheral region 12b of the substrate 12 and is connected to the first portion 32a', and the third portion 32c' is located in the peripheral region 12b of the substrate 12 and is separated from the second portion 32b'. Figure 4 In this embodiment, transistor 44a may be disposed in the active region 12a of substrate 12. In some embodiments, transistor 44a may be a dual-gate transistor. Transistor 44a may include an oxide semiconductor layer 28, which may include indium gallium zinc oxide (IGZO). The first gate line GL1 may include a first portion 24a' and a second portion 24b' of the first metal layer 24, and the second gate line GL2 may include a first portion 32a' and a second portion 32b' of the second metal layer 32. Opening 46 may include other numbers, such as two or more. The fifth insulating layer 30 has an opening 48, the number of which is one. In some embodiments, opening 48 may include other numbers, such as two or more. The sixth insulating layer 34 has an opening 50, the number of which is one. In some embodiments, opening 50 may include other numbers, such as two or more. Figure 4 In the middle, opening 50 overlaps with opening 46 and opening 48. The sixth insulating layer 34 further includes one opening 52 adjacent to opening 50. In some embodiments, opening 52 may include other numbers, such as two or more. The third metal layer 36 is located in the peripheral region 12b of the substrate 12. The third metal layer 36 includes a first portion 36a' and a second portion 36b'. In some embodiments, the conductive component CE may be the first portion 36a' of the third metal layer 36, and the conductive component CE may be electrically connected to the second portion 24b' of the first metal layer 24 through the fourth insulating layer 26, the fifth insulating layer 30, and the sixth insulating layer 34, and electrically connected to the second portion 32b' of the second metal layer 32 through the sixth insulating layer 34. More specifically, in Figure 4 In the middle, the conductive component CE is electrically connected to the first gate line GL1 through openings 46, 48 and 50, and electrically connected to the second gate line GL2 through opening 52. The connecting line CL is connected to the third portion 32c' of the second metal layer 32, and the connecting line CL is electrically connected to the conductive component CE.

[0093] Please see Figure 5 , Figure 6 According to one embodiment of the present disclosure, an electronic device 10 is provided. Figure 5 This is a top view of the electronic device 10. Figure 6 This is a cross-sectional view of electronic device 10.

[0094] exist Figure 6 In, similar to Figure 3 The disclosed portions will not be repeated here. The fourth insulating layer 26 has one opening 46. In some embodiments, the opening 46 may include other numbers, such as two or more. The fifth insulating layer 30 has one opening 48. In some embodiments, the opening 48 may include other numbers, such as two or more. The sixth insulating layer 34 has one opening 50. In some embodiments, the opening 50 may include other numbers, such as two or more. Figure 6 In the middle, opening 50 overlaps with opening 46 and opening 48. The sixth insulating layer 34 further includes one opening 52 adjacent to opening 50. In some embodiments, opening 52 may include other numbers, such as two or more. The third metal layer 36 is located in the peripheral region 12b of the substrate 12. The third metal layer 36 includes a first portion 36a, a second portion 36b, and a third portion 36c. In some embodiments, the conductive component CE may be the first portion 36a of the third metal layer 36, and the conductive component CE may be electrically connected to the second portion 24b of the first metal layer 24 through the fourth insulating layer 26, the fifth insulating layer 30, and the sixth insulating layer 34, and electrically connected to the second portion 32b of the second metal layer 32 through the sixth insulating layer 34. More specifically, in Figure 6 In this configuration, the conductive component CE is electrically connected to the first gate line GL1 via openings 46, 48, and 50, and electrically connected to the second gate line GL2 via opening 52. The second portion 36b of the third metal layer 36 is separated from the first portion 36a. The third portion 36c of the third metal layer 36 serves as the source / drain of the transistor 42, electrically connecting the first semiconductor layer 16 and the third portion 24c of the first metal layer 24. Notably, the connecting line CL electrically connects the third portion 24c of the first metal layer 24 and the second portion 24b of the first metal layer 24. In some embodiments, the thickness T3 of the connecting line CL is greater than the thickness T1 of the first gate line GL1 or the thickness T2 of the second gate line GL2. In some embodiments, such as... Figure 5 As shown, the width Wc of the connecting line CL is greater than the width Wa of the first gate line GL1 or the width Wb of the second gate line GL2. This disclosure allows for improved signal conduction by adjusting the thickness or width of the connecting line CL. Figure 6In this embodiment, a driving circuit 54 is disposed in the peripheral region 12b of the substrate 12. The driving circuit 54 may be, for example, a gate on panel (GOP), and may include a transistor 42. A connecting line CL may electrically connect the driving circuit 54 to the conductive component CE.

[0095] According to the top view of electronic device 10 ( Figure 5 This section describes the electrical connections between transistor 44 and various components in electronic device 10. The conductive component CE (the first portion 36a of the third metal layer 36) is electrically connected to the first gate line GL1 and the second gate line GL2. The connecting line CL is electrically connected to the third portion 24c of the first metal layer 24 and the second portion 24b of the first metal layer 24. The third portion 36c of the third metal layer 36 is electrically connected to the first semiconductor layer 16 of transistor 42 and the third portion 24c of the first metal layer 24.

[0096] Please see Figure 7 According to one embodiment of the present disclosure, an electronic device 10 is provided. Figure 7 This is a cross-sectional view of electronic device 10.

[0097] exist Figure 7 In, similar to Figure 6 The publicly disclosed details will not be repeated here. Its relation to... Figure 6 The main difference is that, Figure 7The disclosed electronic device 10 further includes a second conductive component at the other end of transistor 44, electrically connected to the gate line of transistor 44. Detailed description follows: the first gate line GL1 has two ends (GL1b, GL1d). The second gate line GL2 has two ends (GL2b, GL2d). The first conductive component CE is disposed in the peripheral region 12b of substrate 12. In some embodiments, the first conductive component CE may be a first portion 36a of the third metal layer 36, electrically connected to one of the two ends (GL1b, GL1d) of the first gate line GL1 (e.g., end GL1b) and electrically connected to one of the two ends (GL2b, GL2d) of the second gate line GL2 (e.g., end GL2b). The second conductive component CE' may be disposed in the peripheral region 12b of the substrate 12. In some embodiments, the second conductive component CE' may be electrically connected to one of the two ends (GL1b, GL1d) of the first gate line GL1 (e.g., end GL1d) and electrically connected to one of the two ends (GL2b, GL2d) of the second gate line GL2 (e.g., end GL2d). One of the two ends (GL1b, GL1d) of the first gate line GL1 is adjacent to one of the two ends (GL2b, GL2d) of the second gate line GL2. For example, the end GL1b of the first gate line GL1 is adjacent to the end GL2b of the second gate line GL2, and the end GL1d of the first gate line GL1 is adjacent to the end GL2d of the second gate line GL2.

[0098] Please see Figure 8 , Figure 9 According to one embodiment of the present disclosure, an electronic device 10 is provided. Figure 8 This is a top view of the electronic device 10. Figure 9 This is a cross-sectional view of electronic device 10.

[0099] exist Figure 9 In, similar to Figure 3The disclosed portions will not be repeated here. The first metal layer 24 includes a first portion 24a and a second portion 24b, wherein the first portion 24a is located in the active region 12a of the substrate 12, and the second portion 24b is connected to the first portion 24a and located in the peripheral region 12b of the substrate 12. The second metal layer 32 includes a first portion 32a, a second portion 32b, and a third portion 32c, wherein the first portion 32a is located in the active region 12a of the substrate 12, the second portion 32b is connected to the first portion 32a and located in the peripheral region 12b of the substrate 12, and the third portion 32c is separated from the second portion 32b and located in the peripheral region 12b of the substrate 12. The third metal layer 36 includes a first portion 36a and a second portion 36b, located in the peripheral region 12b of the substrate 12. It is worth noting that the connecting line CL can be the second portion 36b of the third metal layer 36 connected to the conductive component CE, and electrically connected to the third portion 32c of the second metal layer 32. The third portion 36c of the third metal layer 36 serves as the source / drain of the transistor 42, electrically connecting the first semiconductor layer 16 and the third portion 32c of the second metal layer 32.

[0100] According to the top view of electronic device 10 ( Figure 8 This describes the electrical connections between the components in electronic device 10. The conductive component CE is electrically connected to the first gate line GL1 and the second gate line GL2, and the connecting line CL is connected to an external circuit (not shown).

[0101] Please see Figure 10 , Figure 11 ,by Figure 7 Taking the electronic device 10 shown as an example, the effect of adding a second conductive component to the other end of the transistor 44 and electrically connecting it to the gate line of the transistor 44 on signal transmission when the switching impedance in the device is too large is explained.

[0102] Excessive switching impedance in the device can be caused by several factors, including an insufficient contact area for the metal layer's power supply connection due to an excessively small etched opening, or damage to the metal layer surface caused by etching gas during the etch process. Figure 10 This is a circuit diagram of an electronic device. In this circuit design, no conductive component is placed at the other end of the dual-gate transistor, that is, one end of the gate lines of the dual-gate transistor is not electrically connected to each other. Figure 11 This is a circuit diagram of an electronic device. The circuit design adds a conductive component to the other end of a dual-gate transistor, meaning that both ends of the gate lines of the dual-gate transistor are electrically connected to each other. Figure 10In the process of transmitting the signal 60 provided by the external circuit, a transfer impedance 62 is generated. Because one end of the gate lines of the dual-gate transistor is not electrically connected to each other (for example, the end GL1d of the first gate line GL1 and the end GL2d of the second gate line GL2 are not electrically connected), this causes an abnormal signal on one of the gate lines. Conversely, in Figure 11 In the process of transmitting the signal 60 provided by the external circuit, a switching impedance 62 is generated. Since the two ends of the gate lines of the dual-gate transistor are electrically connected to each other (the end GL1d of the first gate line GL1 and the end GL2d of the second gate line GL2 are electrically connected by the conductive component CE'), the two gate lines of the dual-gate transistor obtain the same potential, thereby achieving the effect of stable signal transmission.

[0103] Please see Figures 12-14 According to one embodiment of the present disclosure, a method for manufacturing an electronic device is provided. Figures 12-14 This is a cross-sectional view of an electronic device manufacturing process. Some components of the electronic device are omitted from the figure for ease of explanation.

[0104] First, such as Figure 12 As shown, a substrate 12 is provided, on which a first insulating layer 14, a second insulating layer 18, a third insulating layer 22, a first metal layer 24, a fourth insulating layer 26, an oxide semiconductor layer 28, a fifth insulating layer 30, a second metal layer 32, a sixth insulating layer 34, and a photoresist layer 64 are sequentially formed.

[0105] Next, as Figure 13 As shown, the photoresist layer 64 is patterned to form a patterned photoresist layer 66. The patterned photoresist layer 66 includes a first opening 68 and a second opening 70. Figure 13 In this embodiment, there are two first openings 68 and two second openings 70. In some embodiments, the number of first openings 68 and second openings 70 may include other numbers, such as one or more. Next, using the patterned photoresist layer 66 as an etching shield, the insulating layer below the patterned photoresist layer 66 is etched to form a third opening 72 and a fourth opening 74, respectively exposing a portion of the first metal layer 24 and a portion of the second metal layer 32. There are two third openings 72, which pass through the fourth insulating layer 26, the fifth insulating layer 30, and the sixth insulating layer 34, exposing a portion of the first metal layer 24. There are two fourth openings 74, which pass through the sixth insulating layer 34, exposing a portion of the second metal layer 32.

[0106] Next, as Figure 14As shown, a third metal 36 is formed on the sixth insulating layer 34, and the third opening 72 and the fourth opening 74 are filled in, forming on the exposed first metal layer 24 and second metal layer 32, so that the third metal 36 is electrically connected to the first metal layer 24 and the second metal layer 32. This completes the fabrication of the conductive component in the electronic device. It is worth noting that in some embodiments, the step of etching through the sixth insulating layer 34 and the step of etching through the fourth insulating layer 26, the fifth insulating layer 30, and the sixth insulating layer 34 are performed in the same process.

[0107] Please see Figure 13 This further clarifies the dimensional relationships of the openings in the electronic device structure.

[0108] like Figure 13 As shown, the width of the first opening 68 is W1, the width of the second opening 70 is W2, the width of the third opening 72 is W3, the width of the fourth opening 74 is W4, the spacing between the third openings 72 is S1, the spacing between the fourth openings 74 is S2, and the spacing between the third opening 72 and the fourth opening 74 is S3. Figure 13 In this embodiment, the width W1 of the first opening 68 is greater than the width W2 of the second opening 70, the width W3 of the third opening 72 is greater than the width W4 of the fourth opening 74, the spacing S1 of the third opening 72 is less than the spacing S3 between the third opening 72 and the fourth opening 74, and the spacing S2 of the fourth opening 74 is less than the spacing S3 between the third opening 72 and the fourth opening 74. In some embodiments, the widths W3 of the third opening 72 and W4 of the fourth opening 74 are approximately between 2 micrometers and 4 micrometers. In some embodiments, the spacing S1 of the first opening 68 and S2 of the second opening 70 are approximately between 0.5 micrometers and 2 micrometers. In some embodiments, the spacing S3 of the first opening 68 and the second opening 70 is approximately between 3 micrometers and 5 micrometers. It is worth noting that the widths W3 of the third opening 72 and W4 of the fourth opening 74 (the width at the bottom of the opening) should not be too small to reduce the chance of poor electrical contact. However, an excessively large size will also occupy more space. The spacing S1 between the first opening 68 and the spacing S2 between the second opening 70 should not be too small to reduce the possibility of the opening structure collapsing, but it should not be too large to reduce the area occupied. In addition, the spacing S3 between the first opening 68 and the second opening 70 can be selected to be a suitable size to reduce the connection between the third opening 72 and the fourth opening 74, which would cause excessive impedance and lead to the simultaneous failure of the upper and lower gate lines.

[0109] This disclosure utilizes a metal conductive component to simultaneously connect the top and bottom gates of a dual-gate transistor. This circuit design creates a channel on the upper and lower surfaces of the conductive layer, effectively improving the transistor's drive speed (I0). ONThe electrical signals provided by external circuitry (e.g., flexible printed circuit boards (FPCs) or chip-on-film (COF) films) can be transmitted via upper-layer interconnects to a metal conductive component to drive the top and bottom gates of a dual-gate transistor, or via lower-layer interconnects to the bottom gate of the dual-gate transistor and then via a metal conductive component to the top gate. Directly connecting the top and bottom gates requires more photolithography steps and increases the line impedance of the bottom gate, resulting in a higher RC load on the bottom gate than the top gate, leading to a potential difference between the top and bottom gates. The method of fabricating a metal conductive component that simultaneously connects the top and bottom gates (i.e., forming openings of different depths simultaneously in the same process) in this disclosure requires fewer photolithography steps. Increasing the number of transition openings in this disclosure reduces the risk of overall signal transfer failure due to excessive impedance at a single opening. This disclosure can improve signal conduction by adjusting the material (selecting one with better conductivity), thickness, or width of the interconnects. Furthermore, the metal conductive component disclosed herein increases the contact area for power connection between the top gate and the bottom gate by electrically connecting the top gate and the bottom gate through openings corresponding to the top gate and the bottom gate respectively, thereby reducing the switching impedance.

[0110] The components of some of the embodiments described above are provided to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the appended claims. Furthermore, although this disclosure has been described above with reference to several embodiments, it is not intended to limit this disclosure.

[0111] References to features, advantages, or similar language throughout this specification are not intended to imply that all features and advantages achievable using this disclosure should or may be implemented in any single embodiment of this disclosure. Rather, language relating to features and advantages is to be understood as meaning that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Thus, the discussion of features and advantages, as well as similar language, throughout this specification may, but does not necessarily, represent the same embodiments.

[0112] Furthermore, in one or more embodiments, the features, advantages, and characteristics described in this disclosure may be combined in any suitable manner. Based on the description herein, those skilled in the art will recognize that this disclosure may be implemented without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of this disclosure.

Claims

1. An electronic device, characterized in that, include: One substrate; A first gate line is disposed on the substrate; A first insulating layer is disposed on the first gate line; A second insulating layer is disposed on the first insulating layer; An oxide semiconductor layer is disposed between the first insulating layer and the second insulating layer; A second gate line is disposed on the second insulating layer; A third insulating layer is disposed on the second gate line; A first conductive component is disposed on the third insulating layer; A driving circuit; and One connecting line; The first conductive component passes through the first insulating layer, the second insulating layer, and the third insulating layer to electrically connect to the first gate line, and passes through the third insulating layer to electrically connect to the second gate line. The connecting line electrically connects the driving circuit and the first conductive component. The substrate includes an active region and a peripheral region, the peripheral region being adjacent to the active region. The driving circuit is disposed in the peripheral region, and the oxide semiconductor layer is disposed in the active region.

2. The electronic device of claim 1, further comprising a second conductive component, wherein the first gate line has a plurality of two ends, the second gate line has a plurality of two ends, the first conductive component is electrically connected to one of the plurality of two ends of the first gate line and one of the plurality of two ends of the second gate line, the second conductive component is electrically connected to another of the plurality of two ends of the first gate line and another of the plurality of two ends of the second gate line, and one of the plurality of two ends of the first gate line is adjacent to one of the plurality of two ends of the second gate line.

3. The electronic device as claimed in claim 1, characterized in that, The first insulating layer has a first opening, the second insulating layer has a second opening, and the third insulating layer has a third opening. In a cross-sectional view of the electronic device, the third opening overlaps with the first opening and the second opening, and the first conductive component is electrically connected to the first gate line through the first opening, the second opening, and the third opening.

4. The electronic device as claimed in claim 3, characterized in that, The number of the first opening exceeds one, the number of the second opening exceeds one, and the number of the third opening exceeds one.

5. The electronic device as claimed in claim 1, characterized in that, The third insulating layer has a fourth opening, and the first conductive component is electrically connected to the second gate line through the fourth opening.

6. The electronic device as claimed in claim 5, characterized in that, The number of the fourth opening exceeds one.

7. The electronic device as claimed in claim 1, characterized in that, The conductivity of the material of the connecting wire is greater than that of the material of the first gate wire or the material of the second gate wire.

8. The electronic device as claimed in claim 1, characterized in that, In a top view of the electronic device, the width of the connecting line is greater than the width of the first gate line or the width of the second gate line.

9. The electronic device as claimed in claim 1, characterized in that, In a cross-sectional view of the electronic device, the thickness of the connecting line is greater than the thickness of the first gate line or the thickness of the second gate line.

10. A method for manufacturing an electronic device, characterized in that, include: A substrate is provided, wherein the substrate includes an active region and a peripheral region, the peripheral region being adjacent to the active region; A first gate line is formed on the substrate; A first insulating layer is formed on the first gate line; An oxide semiconductor layer is formed on the first insulating layer and disposed in the active region; A second insulating layer is formed on the oxide semiconductor layer; A second gate line is formed on the second insulating layer; A third insulating layer is formed on the second gate line; The third insulating layer is penetrated to expose a portion of the second gate line; The first insulating layer, the second insulating layer, and the third insulating layer are penetrated to expose a portion of the first gate line; A first conductive component is formed on the third insulating layer, the portion of the first gate line, and the portion of the second gate line, such that the first conductive component is electrically connected to the first gate line and the second gate line; A driving circuit is formed in the surrounding area; and A connection line is formed, wherein the connection line electrically connects the drive circuit and the first conductive component.

11. The method of manufacturing an electronic device as claimed in claim 10, characterized in that, The steps of penetrating the third insulating layer and penetrating the first, second and third insulating layers are performed in the same process.

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