field effect transistor

Abstract

A field effect transistor (10) has a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37). Each of the p-type deep layers projects downward from a body layer, extends in a first direction that intersects a trench when the semiconductor substrate is viewed from the top side, and is arranged with a spacing portion in a second direction that is orthogonal to the first direction when the semiconductor substrate is viewed from the top side. Each of the n-type deep layers is arranged in the corresponding spacing portion. A drift layer has a lower n-type impurity concentration than each of the n-type deep layers. A dimension of the n-type deep layer in the thickness direction of the semiconductor substrate is larger than a dimension of the n-type deep layer in the second direction.

Description

Technical Field

[0001] (Mutual references between related applications)

[0002] This application is a related application to Japanese Patent Application No. 2021-039306, filed on March 11, 2021, and claims priority based on that Japanese patent application. The entire contents of that Japanese patent application are incorporated herein by reference.

[0003] The technology disclosed in this specification relates to field-effect transistors. Background Technology

[0004] Japanese Patent Application Publication No. 2009-194065 (hereinafter referred to as Patent Document 1) discloses a trench-gate field-effect transistor. This field-effect transistor has multiple p-type deep layers protruding downwards from the body layer. Each p-type deep layer extends in a manner that intersects with the trench when viewed from above. The multiple p-type deep layers are arranged with spacing between them in their width direction. Each p-type deep layer extends from the body layer to a position lower than the bottom surface of the trench. In one example of the field-effect transistor disclosed in Patent Document 1, each p-type deep layer is in contact with the gate insulating film at the side surface and bottom surface of the trench located below the body layer. Furthermore, the field-effect transistor has an n-type drift layer in contact with the body layer and each p-type deep layer. When the field-effect transistor is turned off, a depletion layer extends from the body layer into the drift layer. The source-drain voltage is maintained by the depletion layer extending into the drift layer. Furthermore, when the field-effect transistor is off, the depletion layer extends from each deep p-layer into the drift layer. Since each deep p-layer is in contact with the gate insulating film at the bottom surface of the trench, the drift layer around the bottom surface of the trench is depleted by the depletion layer extending from each deep p-layer. Thus, by extending the depletion layer from each deep p-layer to the periphery of the bottom surface of the trench, electric field concentration in the gate insulating film and drift layer around the bottom surface of the trench is suppressed. Therefore, this field-effect transistor has a high breakdown voltage. Summary of the Invention

[0005] In the field-effect transistor of Patent Document 1, when the transistor is turned on, a channel is formed in the body layer. Electrons then flow from the source layer to the channel. Since multiple p-type deep layers exist below the body layer, electrons that have passed through the channel flow into the drift layers located in the spacers between the p-type deep layers. Electrons that have passed through the spacers flow into the drift layers below the spacers. Thus, electrons flow from the source layer through the channel and the drift layers in the spacers to the drift layers below the spacers. The drift layers in the spacers are sandwiched between the p-type deep layers. When the field-effect transistor is turned on, depletion layers extend from each p-type deep layer into the drift layers in the spacers. Through these extended depletion layers, the path for electron flow within the drift layers in the spacers narrows. As a result, the resistance of the spacers increases. Therefore, the field-effect transistor of Patent Document 1 has a high on-resistance. In this specification, a technique for achieving low on-resistance in a field-effect transistor having multiple p-type deep layers is proposed.

[0006] The field-effect transistor disclosed in this specification includes: a semiconductor substrate having trenches on its upper surface; a gate insulating film covering the inner surface of the trenches; and a gate electrode disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes: an n-type source layer in contact with the gate insulating film on a side of the trench; a p-type body layer in contact with the gate insulating film on the side of the trench located below the source layer; a plurality of p-type deep layers; a plurality of n-type deep layers; and a drift layer. Each p-type deep layer protrudes downward from the body layer, extends from the body layer to a position lower than the bottom surface of the trench, extends along a first direction intersecting the trenches when viewed from above, and is spaced apart in a second direction orthogonal to the first direction when viewed from above. It is in contact with the gate insulating film on the side and bottom surface of the trench located below the body layer. Each of the aforementioned n-type deep layers is disposed within a corresponding spacer portion and is in contact with the gate insulating film on the side surface of the trench located below the body layer. The drift layer is an n-type layer with a lower n-type impurity concentration compared to each of the aforementioned n-type deep layers and is in contact with the lower surface of the plurality of n-type deep layers. Each of the aforementioned p-type deep layers has a shape in which the dimension in the thickness direction of the semiconductor substrate is larger than the dimension in the second direction. Each of the aforementioned n-type deep layers has a shape in which the dimension in the thickness direction of the semiconductor substrate is larger than the dimension in the second direction.

[0007] Furthermore, the "dimension in the second direction" of the p-type deep layer refers to the distance between the two side surfaces of the p-type deep layer in the second direction. Additionally, the "dimension in the thickness direction of the semiconductor substrate" of the p-type deep layer refers to the distance in the thickness direction of the semiconductor substrate from the lower surface of the body layer (i.e., the upper surface of the p-type deep layer) to the lower surface of the p-type deep layer. Similarly, the "dimension in the second direction" of the n-type deep layer refers to the distance between the two side surfaces of the n-type deep layer in the second direction. Furthermore, the "dimension in the thickness direction of the semiconductor substrate" of the n-type deep layer refers to the distance in the thickness direction of the semiconductor substrate from the lower surface of the body layer (i.e., the upper surface of the n-type deep layer) to the lower surface of the n-type deep layer.

[0008] Because this field-effect transistor has multiple p-type deep layers, electric field concentration around the bottom surface of the trench can be suppressed when the transistor is turned off. Therefore, this field-effect transistor has a high breakdown voltage. Furthermore, in this field-effect transistor, an n-type deep layer with a higher n-type impurity concentration than the drift layer is provided in the spacer between the multiple p-type deep layers. Moreover, the size of the n-type deep layer in the thickness direction of the semiconductor substrate is larger than the size of the n-type deep layer in the second direction. That is, the n-type deep layer has a longer shape in the longitudinal direction (i.e., the thickness direction of the semiconductor substrate). Therefore, a larger area in the spacer is constituted by the n-type deep layer. When the field-effect transistor is turned on, electrons flow from the source layer through the channel and the n-type deep layers to the drift layer. Because the n-type deep layers are disposed within the spacer, the depletion layer extends from the p-type deep layers on both sides of the n-type deep layer. However, because the n-type impurity concentration in the n-type deep layers is high, the width of the depletion layer extending from the p-type deep layers to the n-type deep layers is narrow. Therefore, a wider electron flow path is ensured within the n-type deep layers. Therefore, the resistance of the spacer portion can be lower than before. Consequently, based on the structure of this field-effect transistor, low on-resistance can be achieved. Attached Figure Description

[0009] Figure 1 This is a cross-sectional perspective view of MOSFET10 (showing the XZ cross-section excluding the p-type deep layer 36).

[0010] Figure 2 This is a cross-sectional perspective view of the MOSFET 10 with the source electrode 22 and interlayer insulating film 20 omitted.

[0011] Figure 3 This is a top view showing the configuration of the trench 14 and p-type depth 36 when viewed from above on the semiconductor substrate 12.

[0012] Figure 4 These are enlarged sectional views of p-type deep layer 36 and n-type deep layer 37.

[0013] Figure 5This is a cross-sectional perspective view of MOSFET10 (showing an xz cross-section including the p-type deep layer 36).

[0014] Figure 6 This is an illustrative diagram illustrating the manufacturing process of MOSFET10.

[0015] Figure 7 This is an illustrative diagram illustrating the manufacturing process of MOSFET10.

[0016] Figure 8 This is an illustrative diagram illustrating the manufacturing process of MOSFET10.

[0017] Figure 9 This is a diagram showing the distribution of the depletion layer within the n-type deep layer 37 when MOSFET10 is turned on.

[0018] Figure 10 This is a graph showing the relationship between the specification value Dn / Dp and the characteristics of MOSFET10.

[0019] Figure 11 This is an enlarged cross-sectional view of the p-type deep layer 36 and n-type deep layer 37 of the MOSFET in the first modified example.

[0020] Figure 12 This is an enlarged cross-sectional view of the p-type deep layer 36 and n-type deep layer 37 of the MOSFET in the second variation.

[0021] Figure 13 This is an enlarged cross-sectional view of the p-type deep layer 36 and n-type deep layer 37 of the MOSFET in the third variation. Detailed Implementation

[0022] In one example of the field-effect transistor disclosed in this specification, the plurality of n-type deep layers may extend from the lower surface of the body layer to a depth equal to the lower surface of the plurality of p-type deep layers. In this case, the plurality of n-type deep layers may also extend from the lower surface of the body layer to a depth lower than the lower surface of the plurality of p-type deep layers.

[0023] Based on these structures, the entire spacer portion can be constructed using a deep n-type layer with a high concentration of n-type impurities. Therefore, the on-resistance of the field-effect transistor can be further reduced.

[0024] In one example of a field-effect transistor disclosed in this specification, the plurality of n-type deep layers may be interconnected via a region that is lower than the lower surface of the plurality of p-type deep layers.

[0025] In one example of the field-effect transistor disclosed in this specification, the size of the n-type deep layer in the thickness direction of the semiconductor substrate may be 1.07 times or less the size of the p-type deep layer in the thickness direction of the semiconductor substrate.

[0026] Based on this structure, higher breakdown voltage can be achieved in field-effect transistors.

[0027] Figure 1 , 2 The MOSFET 10 (metal-oxide-semiconductor field-effect transistor) of the illustrated embodiment has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (or orthogonal to the z-direction) will be referred to as the x-direction, and a direction orthogonal to both the x-direction and the z-direction will be referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (SiC). Alternatively, the semiconductor substrate 12 may also be made of other semiconductor materials such as silicon or gallium nitride. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Figure 2 As shown, a plurality of grooves 14 extend elongatedly along the y-direction in the upper surface 12a. The plurality of grooves 14 are spaced apart in the x-direction.

[0028] like Figure 1 , Figure 2 As shown, the inner surfaces (i.e., the side surfaces and bottom surfaces) of each trench 14 are covered by a gate insulating film 16. A gate electrode 18 is disposed within each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. Figure 1 As shown, the upper surface of each gate electrode 18 is covered by an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. In the location where the interlayer insulating film 20 is not present, the source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0029] like Figure 1 , Figure 2 As shown, the semiconductor substrate 12 has multiple source layers 30, multiple contact layers 32, a bulk layer 34, multiple p-type deep layers 36, multiple n-type deep layers 37, a drift layer 38, and a drain layer 40.

[0030] Each source layer 30 is an n-type layer with a high n-type impurity concentration. Each source layer 30 is disposed within a region of the semiconductor substrate 12 that locally includes the upper surface 12a. Each source layer 30 is in ohmic contact with the source electrode 22. At the uppermost part of the sidewall of the trench 14, each source layer 30 is in contact with the gate insulating film 16. Each source layer 30 is opposed to the gate electrode 18 through the gate insulating film 16. Each source layer 30 extends relatively long in the y-direction along the sidewall of the trench 14.

[0031] Each contact layer 32 is a p-type layer with a high p-type impurity concentration. Each contact layer 32 is disposed within a region of the semiconductor substrate 12 that locally includes the upper surface 12a. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends relatively long in the y-direction.

[0032] Body layer 34 is a p-type layer with a lower p-type impurity concentration than contact layer 32. Body layer 34 is disposed below the plurality of source layers 30 and the plurality of contact layers 32. Body layer 34 is connected to the plurality of source layers 30 and the plurality of contact layers 32 from below. On the side of the trench 14 located below the source layers 30, body layer 34 is connected to gate insulating film 16. Body layer 34 is opposed to gate electrode 18 through gate insulating film 16.

[0033] Each p-type deep layer 36 is a p-type layer protruding downwards from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than that of the body layer 34, but lower than that of the contact layer 32. When... Figure 3 When the semiconductor substrate 12 is viewed from above as shown, each p-type deep layer 36 extends relatively long in the x-direction and is orthogonal to the trench 14. The multiple p-type deep layers 36 are spaced apart in the y-direction. Hereinafter, the portion between the multiple p-type deep layers 36 will be referred to as the spacer portion 39. Figure 4 As shown, the p-type deep layer 36 has a shape that is longer in the z-direction in the yz section. That is, the dimension in the z-direction of the p-type deep layer 36 (hereinafter referred to as depth Dp) is larger than the dimension in the y-direction of the p-type deep layer 36 (hereinafter referred to as width Wp). For example, the depth Dp can be set to 1 to 4 times the width Wp. Figure 5 As shown, each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth lower than the bottom surface of each trench 14. Each p-type deep layer 36 is in contact with the gate insulating film 16 at the side of the trench 14 located below the body layer 34. Furthermore, each p-type deep layer 36 is in contact with the gate insulating film 16 at the bottom surface of the trench 14. Each p-type deep layer 36 is opposed to the gate electrode 18 through the gate insulating film 16.

[0034] Each n-type depth layer 37 has a higher n-type impurity concentration than the drift layer 38. The n-type impurity concentration in each n-type depth layer 37 is lower than the p-type impurity concentration in each p-type depth layer 36. For example... Figure 1 , Figure 2 As shown, each n-type deep layer 37 is disposed within a corresponding spacer 39. Each n-type deep layer 37 is in contact with the lower surface of the body layer 34. Each n-type deep layer 37 is in contact with the sides of the p-type deep layers 36 on both sides. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position lower than the bottom surface of each groove 14 and the lower surface of each p-type deep layer 36. Figure 4 As shown, the n-type deep layer 37 within the spacer 39 has a shape that is longer in the z-direction in the yz cross-section. That is, the dimension of the n-type deep layer 37 in the z-direction (hereinafter referred to as depth Dn) is larger than the dimension of the n-type deep layer 37 in the y-direction (hereinafter referred to as width Wn) within the spacer 39. For example, the depth Dn can be set to 1 to 4 times the width Wn. In this embodiment, the width Wn of the n-type deep layer 37 is approximately equal to the width Wp of the p-type deep layer 36. Each n-type deep layer 37 has a connecting region 37a extending directly below the lower surface of the adjacent p-type deep layer 36. Each connecting region 37a is in contact with the lower surface of the corresponding p-type deep layer 36. Each n-type deep layer 37 is interconnected via each connecting region 37a. The thickness T1 of the portion of the n-type deep layer 37 that protrudes downwards from the lower surface of the p-type deep layer 36 (i.e., the distance in the z-direction from the lower surface of the p-type deep layer 36 to the lower surface of the n-type deep layer 37) is approximately 0.1 μm, which is very thin. For example... Figure 1 , Figure 2 As shown, each n-type deep layer 37 is in contact with the gate insulating film 16 within each spacer 39. That is, each n-type deep layer 37 is in contact with the gate insulating film 16 on the side surface and bottom surface of the trench 14 located below the body layer 34.

[0035] The drift layer 38 is an n-type layer with a lower n-type impurity concentration than the source layer 30. The drift layer 38 is disposed below the n-type deep layer 37. The drift layer 38 is connected to the n-type deep layer 37 from the bottom.

[0036] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type depth layer 37. The drain layer 40 is connected to the drift layer 38 from the bottom. The drain layer 40 is disposed within the area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0037] Next, the manufacturing method of MOSFET 10 will be described. MOSFET 10 is manufactured from a semiconductor substrate that is entirely composed of a drain layer 40. First, as... Figure 6 As shown, a drift layer 38 is formed on the drain layer 40 by epitaxial growth, and an n-type deep layer 37 is formed by ion implantation of n-type impurities into the surface portion of the formed drift layer 38. Next, as... Figure 7 As shown, multiple p-type deep layers 36 are formed in the n-type deep layer 37 by selectively ion implanting p-type impurities into the n-type deep layer 37. Then, as... Figure 8 As shown, a body layer 34 is formed on the n-type deep layer 37 and the p-type deep layer 36 by epitaxial growth. Alternatively, the formation of the p-type deep layer 36 can be performed after the formation of the body layer 34. Next, the source layer 30 and the contact layer 32 are formed by selectively ion implanting n-type and p-type impurities into the body layer 34. Then, the MOSFET 10 is completed by forming a trench 14, a gate insulating film 16, a gate electrode 18, an interlayer insulating film 20, a source electrode 22, and a drain electrode 24.

[0038] MOSFET 10 is used when a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. Through the channel, the source layer 30 is connected to the n-type deep layer 37. Therefore, as Figure 1 As indicated by arrow 100, electrons flow from the source layer 30 through the channel, the n-type deep layer 37, and the drift layer 38 to the drain layer 40. That is, MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced from a value above the gate threshold to a value below the gate threshold, the channel disappears, and the flow of electrons stops. That is, MOSFET 10 is turned off.

[0039] Next, the operation when MOSFET 10 is turned off will be explained in more detail. If the channel disappears, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and each n-type deep layer 37. Therefore, the depletion layer extends from the body layer 34 to each n-type deep layer 37. Furthermore, each p-type deep layer 36 is connected to the body layer 34 and has approximately the same potential as the body layer 34. Therefore, if the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, the depletion layer also extends from each p-type deep layer 36 to each n-type deep layer 37. As... Figure 5As shown, at the intersection of each p-type deep layer 36 and the trench 14, a p-type deep layer 36 exists directly below the trench 14. Therefore, the depletion layer extends from the p-type deep layer 36 directly below the trench 14 to the n-type deep layer 37 around the bottom surface of the trench 14. Thus, the depletion layer extending from the p-type deep layer 36 rapidly depletes the n-type deep layer 37 around the bottom surface of the trench 14. This suppresses electric field concentration near the bottom surface of the trench 14. Furthermore, the depletion layer extending from the bulk layer 34 and each p-type deep layer 36 depletes the entire n-type deep layer 37. Additionally, since the n-type impurity concentration is lower in each n-type deep layer 37 compared to the drift layer 38, the depletion layer is less likely to extend into each n-type deep layer 37 compared to the drift layer 38. However, since each n-type deep layer 37 is sandwiched between p-type deep layers 36, and the width Wn of each n-type deep layer 37 is relatively narrow, the entire n-type deep layer 37 is depleted. Furthermore, the depletion layer extends towards the drift layer 38 via each n-type deep layer 37. Because the n-type impurity concentration in the drift layer 38 is low, the drift layer 38 is almost entirely depleted. Through the depleted drift layer 38 and each n-type deep layer 37, the high voltage applied between the drain electrode 24 and the source electrode 22 is maintained. Therefore, the MOSFET 10 has a high breakdown voltage.

[0040] Next, the operation when MOSFET10 is turned on will be explained in more detail. As described above, if MOSFET10 is turned on, then... Figure 1 As indicated by arrow 100, electrons flow from the source layer 30 through the channel and the n-type deep layer 37 to the drift layer 38. Figure 9 This indicates the distribution of the depletion layer 90 within the n-type deep layer 37 when MOSFET10 is turned on. Figure 9 In the diagram, the area shaded by a diagonal line is the depletion layer 90. When the MOSFET 10 is turned on, the pn junction (hereinafter referred to as pn junction 70) at the interface between the n-type deep layer 37 and the p-type deep layer 36 is not subjected to a reverse voltage. However, in this state, a depletion layer 90 exists at the pn junction 70 due to the built-in potential. In this embodiment, because the n-type impurity concentration in the n-type deep layer 37 is high, the width Wd of the depletion layer 90 extending from the pn junction 70 into the n-type deep layer 37 is relatively narrow. Therefore, the width We of the electron flow path within the spacer 39 (i.e., the undepleted n-type deep layer 37) is relatively wide. Consequently, when the MOSFET 10 is turned on, the resistance of the n-type deep layer 37 is low. Therefore, the MOSFET 10 has a low on-resistance.

[0041] As explained above, the MOSFET10 constructed according to the embodiment can achieve high withstand voltage and low on-resistance. Figure 10This represents the results obtained by simulating the on-resistance and breakdown voltage of the MOSFET when the depth Dn of the n-type layer 37 is changed. The horizontal axis represents the specification value Dn / Dp obtained by dividing the depth Dn of the n-type layer 37 by the depth Dp of the p-type layer 36. When Dn / Dp > 1.00, as... Figure 4 In that case, the n-type deep layer 37 extends to a lower position than the p-type deep layer 36. When Dn / Dp = 1.00, as... Figure 11 As shown, the lower end of the n-type depth 37 coincides with the lower end of the p-type depth 36. When Dn / Dp < 1.00, as... Figure 12 As shown, the lower end of the n-type deep layer 37 is positioned above the lower end of the p-type deep layer 36, and the drift layer 38 extends to the spacer 39 on the lower side of the n-type deep layer 37 (i.e., Figure 12 Within region 39a). For example... Figure 10 As shown, the larger the specification value Dn / Dp, the lower the on-resistance. The reason for the high on-resistance when the specification value Dn / Dp is small can be attributed to the fact that... Figure 12 The n-type impurity concentration in region 39a (i.e., the drift layer 38 within the spacer 39) is low, so the width of the depletion layer extending from the p-type deep layer 36 to region 39a is wider when the MOSFET is in the on state, and the electron flow path in region 39a becomes narrower. Figure 10 As shown, a Dn / Dp ratio of 0.67 or higher can significantly reduce on-resistance, and a Dn / Dp ratio of 1.0 or higher can reduce on-resistance even more effectively. Furthermore, a larger Dn / Dp ratio results in a lower MOSFET breakdown voltage. This can be attributed to the fact that if the thickness T1 of the portion of the n-type deep layer 37 protruding downwards from the lower surface of the p-type deep layer 36 is greater, the electric field tends to concentrate within the drift layer 38. A higher breakdown voltage is achieved when the Dn / Dp ratio is below 1.07, and a more stable breakdown voltage is obtained when the Dn / Dp ratio is below 1.03.

[0042] Furthermore, as described above, in the MOSFET 10 of this embodiment, each n-type deep layer 37 and each p-type deep layer 36 has a shape that is relatively long in the vertical direction. If each n-type deep layer 37 and each p-type deep layer 36 is configured in this way, the electrostatic capacitance (i.e., the feedback capacitance) between the gate electrode 18 and the drain electrode 24 is reduced. This allows for an increase in the switching speed of the MOSFET 10.

[0043] In addition, Figures 1-5 In the MOSFET 10 of the aforementioned embodiment, the depth of the n-type deep layer 37 is greater than the depth of the p-type deep layer 36. However, it is also possible to proceed as described above. Figure 11 In that case, the depth of the n-type deep layer 37 is equal to the depth of the p-type deep layer 36. Alternatively, it can be as described above. Figure 12Therefore, the depth of p-type deep layer 36 is greater than the depth of n-type deep layer 37.

[0044] In addition, Figures 1-5 In the MOSFET 10 of the illustrated embodiment, each n-type depth 37 has a connection region 37a extending directly below the p-type depth 36. However, it is also possible to... Figure 13 Therefore, the n-type deep layer 37 does not have a connecting region 37a.

[0045] Furthermore, in the above-described embodiments, each p-type deep layer 36 is orthogonal to each trench 14, but each p-type deep layer 36 may also be obliquely intersecting with respect to each trench 14.

[0046] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations to the specific examples described above. The technical elements described in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving even one of these objectives is itself technically useful.

Claims

1. A field-effect transistor, characterized in that, have: A semiconductor substrate with trenches on its upper surface; A gate insulating film covers the inner surface of the aforementioned trench; as well as The gate electrode is disposed in the trench and is insulated from the semiconductor substrate by the gate insulating film. The above-mentioned semiconductor substrate has: The n-type source layer is in contact with the gate insulating film on the side of the trench. The p-type body layer is in contact with the gate insulating film on the side of the trench located below the source layer. Multiple p-type deep layers; Multiple n-type deep layers; and Drift layer; Each of the above-mentioned p-type deep layers protrudes downward from the above-mentioned body layer, extends from the above-mentioned body layer to a position lower than the bottom surface of the above-mentioned trench, extends along a first direction that intersects with the above-mentioned trench when the semiconductor substrate is viewed from above, and is arranged with a spacer portion in a second direction that is orthogonal to the above-mentioned first direction when the semiconductor substrate is viewed from above. The above-mentioned side surface of the above-mentioned trench located below the above-mentioned body layer and the above-mentioned bottom surface of the above-mentioned trench are in contact with the above-mentioned gate insulating film. Each of the above-mentioned n-type deep layers is disposed in the corresponding spacer portion, and the side of the trench located on the lower side of the body layer is in contact with the gate insulating film. The aforementioned drift layer is an n-type layer with a lower n-type impurity concentration compared to the aforementioned n-type deep layers, and is in contact with the lower surface of the aforementioned plurality of n-type deep layers; Each of the above-mentioned p-type deep layers has a shape in which the dimension in the thickness direction of the semiconductor substrate is larger than the dimension in the second direction; Each of the above-mentioned n-type deep layers has a shape in which the dimension in the thickness direction of the semiconductor substrate is larger than the dimension in the second direction; The aforementioned n-type deep layers extend from the lower surface of the aforementioned body layer to a position lower than the lower surface of the aforementioned p-type deep layers.

2. The field-effect transistor as described in claim 1, characterized in that, The aforementioned n-type deep layers are interconnected via the region on the lower side of the aforementioned lower surface of the aforementioned p-type deep layers.

3. The field-effect transistor as described in claim 1 or 2, characterized in that, The size of the n-type deep layer in the thickness direction of the semiconductor substrate is less than 1.07 times the size of the p-type deep layer in the thickness direction of the semiconductor substrate.

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