Field effect transistor, electronic equipment and preparation method of field effect transistor

Abstract

The embodiment of the invention provides a field effect transistor, electronic equipment and a preparation method of the field effect transistor, and relates to the technical field of semiconductors. Wherein the field effect transistor comprises a second substrate, an oxide layer and a grid electrode, and the material of the second substrate comprises silicon carbide; the second substrate comprises a source region and a channel region, and the doping concentration of the source region is larger than that of the channel region. The oxide layer is bonded with the second substrate; the oxide layer covers at least part of the channel region; the oxide layer is formed by oxidizing a silicon material. The grid electrode is arranged on the side, away from the second substrate, of the oxide layer. According to the field effect transistor provided by the embodiment of the invention, the oxidation degree of the gate oxide layer is relatively high, and the interface state density between the silicon carbide substrate and the gate oxide layer is relatively small, so that the channel mobility of the silicon carbide field effect transistor is effectively improved, and the electrical performance and reliability of the field effect transistor are optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a field effect transistor, an electronic device, and a method for preparing the field effect transistor. Background Art

[0002] Silicon carbide (SiC) is a compound semiconductor material composed of silicon (Si) and carbon (C). It has many excellent properties such as large bandgap, high breakdown field strength, high thermal conductivity, high saturation velocity, and high maximum operating temperature. These properties enable silicon carbide electronic devices to operate in high voltage, high heat generation, and high frequency environments. Compared with traditional Si MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor), SiC MOSFET of the same power has smaller size, lower power consumption and excellent thermal conductivity. Therefore, SiC MOSFET is widely used in electric vehicles, charging piles, uninterruptible power supplies, smart grids and other fields.

[0003] In the preparation process of SiC MOSFET, the preparation of the gate oxide layer is one of the key links that affects the performance of SiC MOSFET. At present, in SiC MOSFET, the interface quality between the silicon carbide substrate and the gate oxide layer is poor, the interface state density is high, and the channel mobility is low, which seriously affects the electrical performance and reliability of SiC MOSFET. Summary of the invention

[0004] The embodiments of the present application provide a field effect transistor, an electronic device, and a method for preparing a field effect transistor, which are intended to increase the degree of oxidation of a gate oxide layer in a field effect transistor and improve the interface quality between a silicon carbide substrate and the gate oxide layer, thereby improving the electrical performance and reliability of the field effect transistor.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a field effect transistor is provided. The field effect transistor includes a second substrate, an oxide layer and a gate.

[0007] The material of the second substrate includes silicon carbide; the second substrate includes a source region and a channel region, and the doping concentration of the source region is greater than the doping concentration of the channel region. The oxide layer is bonded to the second substrate; the oxide layer covers at least part of the channel region; the oxide layer is formed by oxidation of silicon material. The gate is arranged on a side of the oxide layer away from the second substrate.

[0008] In the field effect transistor provided in the embodiment of the present application, by bonding the oxide layer to the second substrate and using the oxide layer formed by oxidation of the silicon material as at least part of the gate oxide layer, it is possible to ensure that the gate oxide layer has good quality. In addition, there are fewer impurity elements (such as carbon) remaining on the interface of the oxide layer formed by oxidation of the silicon material, thereby effectively reducing the interface state density between the gate oxide layer and the channel region, improving the channel mobility of the field effect transistor, and thus improving the electrical performance of the field effect transistor.

[0009] In a possible implementation of the first aspect, the second substrate also includes a third oxide layer, which is formed by oxidation of silicon carbide material; the third oxide layer is arranged between the channel region and the oxide layer, the third oxide layer is bonded to the oxide layer, and the third oxide layer is in contact with at least part of the channel region.

[0010] By oxidizing the side of the second substrate close to the oxide layer into a third oxide layer, the bonding effect between the second substrate and the oxide layer can be improved. For example, the materials of the oxide layer and the third oxide layer are both silicon dioxide, and the bonding difficulty of two structures of the same material is lower and the bonding strength is higher.

[0011] In a possible implementation of the first aspect, the ratio of the thickness of the third oxide layer to the thickness of the oxide layer is 1:5 to 1:20. That is, the third oxide layer is ensured to have a smaller thickness to avoid high temperature and long-term oxidation treatment of the second substrate, thereby avoiding the formation of interface defects.

[0012] In a possible implementation of the first aspect, an oxidation temperature of the oxide layer during the oxidation process is less than or equal to 1150° C.; when the second substrate includes a third oxide layer, an oxidation temperature of the third oxide layer during the oxidation process is less than or equal to 1150° C.

[0013] By controlling the temperature during the oxidation process to be less than or equal to 1150° C., the interface defects between the silicon carbide substrate and the oxide layer can be greatly reduced, thereby improving the electrical performance and stability of the field effect transistor.

[0014] In a possible implementation of the first aspect, the gate material includes single crystal silicon; the gate and the oxide layer are integrally provided. The gate performance of single crystal silicon is relatively stable, thereby further improving the reliability of the field effect transistor.

[0015] In a possible implementation of the first aspect, the interface state density between the portion of the second substrate located in the channel region and the oxide layer is less than or equal to 10 11 / eV·cm 2 or, in the case where the second substrate includes a third oxide layer, the interface state density between the portion of the second substrate located in the channel region and the third oxide layer is less than or equal to 10 11 / eV·cm2 .

[0016] In the field effect transistor provided in the embodiment of the present application, the interface state density between the channel region and the gate oxide layer (oxide layer, or a combination structure of the oxide layer and the third oxide layer) (i.e., between SiC / SiO2) is set to be less than or equal to 10 11 / eV·cm 2 , which can effectively improve the channel mobility of the field effect transistor, thereby improving the electrical performance and reliability of the field effect transistor.

[0017] In a possible implementation of the first aspect, the field effect transistor further includes a source and a drain, wherein at least a portion of the source is disposed on the second substrate and in contact with the source region, and the drain is disposed on a side of the second substrate away from the oxide layer.

[0018] In a second aspect, a method for preparing a field effect transistor is provided, the method comprising: providing a first substrate; the material of the first substrate comprises silicon, and the first substrate comprises a functional layer and a sacrificial layer arranged in a stacked manner; bonding the first substrate to a second substrate; the material of the second substrate comprises silicon carbide, and the functional layer contacts the second substrate; oxidizing at least a portion of the functional layer; removing the sacrificial layer; and forming a gate.

[0019] By oxidizing the silicon material (first substrate) to silicon dioxide to form an oxide layer, the process of directly performing high-temperature thermal oxidation on silicon carbide (second substrate) to form an oxide layer can be avoided, thereby reducing the difficulty of preparing field effect transistors. In addition, the use of high-cost equipment such as high-temperature thermal oxidation furnaces can be avoided, effectively reducing the preparation cost of field effect transistors. In addition, by oxidizing the silicon material to form an oxide layer, an excellent interface between SiC / SiO2 (i.e., between the channel region and the oxide layer) can be ensured, thereby reducing the density of interface defects, and even the interface state density can be reduced to 10 11 / eV·cm 2 In addition, by preparing silicon dioxide as an oxide layer through a separate silicon wafer (i.e., the first substrate), the thickness of the oxide layer can be controlled as required, without being limited to less than 50nm, which broadens the application scenarios of field effect transistors.

[0020] In a possible implementation of the second aspect, after removing the sacrificial layer, at least a portion of the functional layer is oxidized, including: oxidizing the entire functional layer to form a first oxide layer. The first oxide layer can serve as a gate oxide layer.

[0021] In a possible implementation manner of the second aspect, forming the gate further includes: depositing a gate material on the first oxide layer to form the gate.

[0022] In a possible implementation of the second aspect, before bonding the first substrate to the second substrate, at least a portion of the functional layer is oxidized, including: oxidizing a portion of the functional layer away from the sacrificial layer to form a second oxide layer.

[0023] The second oxide layer can be used as a gate oxide layer. Forming the gate oxide layer before the first substrate and the second substrate are bonded together can avoid the restriction of the silicon carbide substrate in the preparation process of the gate oxide layer, thereby improving the oxidation degree of the gate oxide layer, obtaining a high-quality gate oxide layer, and thus improving the electrical performance of the field effect transistor.

[0024] In a possible implementation of the second aspect, the unoxidized portion of the functional layer is used as a first sublayer, and the first sublayer is located between the second oxide layer and the sacrificial layer. After removing the sacrificial layer, the preparation method further includes: doping the first sublayer to form a gate.

[0025] A gate made of single crystal silicon can be prepared by this method, thereby improving the stability of the field effect transistor.

[0026] In a possible implementation of the second aspect, bonding the first substrate to the second substrate includes: oxidizing a portion of the second substrate to form a third oxide layer. Bonding the third oxide layer to the second oxide layer.

[0027] The third oxide layer can be bonded with the second oxide layer and serve together as a gate oxide layer. The method can reduce the bonding difficulty between the first substrate and the second substrate and improve the bonding stability between the two.

[0028] In a possible implementation of the second aspect, providing the first substrate includes: injecting target ions into a set thickness of the first substrate to form a bubble layer; the bubble layer separates the first substrate into a functional layer and a sacrificial layer. Removing the sacrificial layer includes: heat-treating the first substrate to crack the first substrate at the location of the bubble layer, so that the sacrificial layer is peeled off.

[0029] In a third aspect, an integrated circuit is provided, which includes an electronic device and a field effect transistor as provided in any of the foregoing embodiments, wherein the electronic device is electrically connected to the field effect transistor.

[0030] In a fourth aspect, an electronic device is provided, comprising a circuit board and an integrated circuit as provided in the aforementioned embodiment, wherein the integrated circuit is arranged on the circuit board.

[0031] The technical effects brought about by the integrated circuit in the third aspect and the technical effects brought about by the electronic device in the fourth aspect can be referred to the technical effects brought about by the method for preparing the field effect transistor in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0033] Figure 2 A cross-sectional view of a field effect transistor provided in an embodiment of the present application;

[0034] Figure 3 Another cross-sectional view of a field effect transistor provided in an embodiment of the present application;

[0035] Figure 4 A preparation flow chart of a field effect transistor provided in an embodiment of the present application;

[0036] Figure 5 Another preparation flow chart of a field effect transistor provided in an embodiment of the present application;

[0037] Figure 6 Another preparation flow chart of a field effect transistor provided in an embodiment of the present application;

[0038] Figure 7 to Figure 22 This is a structural diagram corresponding to the preparation steps of the field effect transistor provided in the embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0040] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expression "connection" and its derivatives may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0046] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0047] In addition, the scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that, with the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0048] The embodiment of the present application provides an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, an on-board device, a vehicle, and other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device.

[0049] Figure 1 The following is a schematic diagram of the structure of an electronic device provided by way of example in an embodiment of the present application. Figure 1 As shown, the electronic device 1000 includes an integrated circuit 100 and a circuit board 200 , and the integrated circuit 100 can be arranged on the circuit board 200 .

[0050] Exemplarily, the circuit board 200 may be a printed circuit board (PCB).

[0051] Understandably, Figure 1 The structure of the electronic device 1000 shown in the figure does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include, for example, Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0052] The embodiment of the present application also provides an integrated circuit 100 .

[0053] For example, Figure 1 As shown, the integrated circuit 100 may include a logic circuit 101, an analog circuit 102, a storage circuit 103, an input-output circuit 104, and the like.

[0054] It should be understood that the integrated circuit 100 includes but is not limited to a logic circuit 101, an analog circuit 102, a storage circuit 103 and an input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 may also include circuits of other types or functions, or discrete devices.

[0055] Furthermore, the integrated circuit 100 may include one or more of a logic circuit 101 , an analog circuit 102 , a memory circuit 103 , and an input-output circuit 104 .

[0056] On this basis, the number of logic circuits 101, analog circuits 102, storage circuits 103, and input-output circuits 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 can include one or more logic circuits 101. The integrated circuit 100 can also include one or more analog circuits 102. The integrated circuit 100 can also include one or more storage circuits 103. The integrated circuit 100 can also include one or more input-output circuits 104.

[0057] like Figure 1 As shown, the integrated circuit 100 may include a field effect transistor 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the field effect transistor 10.

[0058] For example, see Figure 1 The field effect transistor 10 and the electronic device 20 can be integrated in the logic circuit 101. The field effect transistor 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to realize functions such as "AND", "OR", and "NOT" in the logic circuit 101.

[0059] Alternatively, illustratively, the field effect transistor 10 may also be integrated into other circuits, for example, may be integrated into a power integrated circuit, which is not specifically limited in the present application.

[0060] Alternatively, illustratively, the field effect transistor 10 may also be provided in the integrated circuit 100 as a discrete device. For example, the field effect transistor 10 may be integrated in the integrated circuit 100 as a power device together with the logic circuit 101 , the analog circuit 102 , etc.

[0061] By way of example, the electronic device 20 may be a resistor, a capacitor or the like.

[0062] Exemplarily, the field effect transistor 10 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), for example, which is not limited in the present application.

[0063] The embodiment of the present application also provides a field effect transistor 10 . Figure 2 and Figure 3 They are respectively schematic diagrams of the structures of the field effect transistor 10 provided in the embodiments of the present application.

[0064] like Figure 2 and Figure 3 As shown, the field effect transistor 10 includes a second substrate 2 , an oxide layer M and a gate 3 .

[0065] The material of the second substrate 2 includes silicon carbide. That is, the field effect transistor 10 can be a SiC MOSFET. SiC is a semiconductor material with a large bandgap, which can make the field effect transistor 10 have multiple excellent properties such as high voltage resistance and high temperature resistance.

[0066] It is understandable that the material of the second substrate 2 is not limited to SiC. For example, semiconductor materials such as gallium nitride (GaN) materials and diamond also have a large bandgap, so that semiconductor materials such as gallium nitride (GaN) materials and diamond can also be applied to the above-mentioned field effect transistor 10. This application does not limit this.

[0067] For example, Figure 2 and Figure 3 As shown, the second substrate 2 may include a base 21 and an epitaxial layer 22 which are stacked, and the epitaxial layer 22 may be grown on the surface of the base 21 .

[0068] For example, the method of forming the epitaxial layer 22 may include a Metal-Organic Chemical Vapor Deposition (MOCVD) growth method or a Molecular Beam Epitaxy (MBE) growth method.

[0069] Exemplarily, the materials of the substrate 21 and the epitaxial layer 22 may be the same, for example, both materials may include silicon carbide.

[0070] Exemplarily, the substrate 21 and the epitaxial layer 22 may both be P-type doped or N-type doped, or may be undoped, which is not limited in the present application.

[0071] For example, when the field effect transistor 10 to be formed is a P-channel transistor, the substrate 21 and the epitaxial layer 22 may be P-type doped.

[0072] Exemplarily, the doping concentrations of the substrate 21 and the epitaxial layer 22 are different. For example, the doping concentration of the substrate 21 may be greater than the doping concentration of the epitaxial layer 22 .

[0073] For example, the substrate 21 may be doped with a high concentration such as N+ doping or N++ doping, and the epitaxial layer 22 may be doped with N-. The substrate 21 with a high doping concentration may be used as a drain region for connecting to the drain electrode (see Figure 2 The drain electrode 5) is in contact with the drain electrode 1 to facilitate the input of the drain electrical signal.

[0074] Exemplarily, the second substrate 2 can also be regarded as a whole. For example, the second substrate 2 is made of silicon carbide material as a whole, such as a silicon carbide wafer, or a chip cut from a silicon carbide wafer. For example, the doping concentration of the second substrate 2 as a whole is the same. Figure 2 and Figure 3 As shown, the second substrate 2 may further include a source region 2B.

[0075] Among them, see Figure 2 The source region 2B can be formed by performing high-concentration doping (for example, N+ doping or N++ doping) on ​​the epitaxial layer 22 .

[0076] See also Figure 2 The source region 2B extends from the surface of the epitaxial layer 22 away from the substrate 21 to the inside of the epitaxial layer 22 .

[0077] The source region 2B is used to communicate with the source (see Figure 2 The source 4) is electrically contacted in order to realize the input of the source signal.

[0078] like Figure 2 and Figure 3 As shown, the second substrate 2 may further include a channel region 2A. The channel region 2A may refer to a region where a carrier transmission path is located.

[0079] Among them, see Figure 2 , the channel region 2A can be formed by doping the epitaxial layer 22 (eg, P-type doping).

[0080] Exemplarily, the doping concentration of the source region 2B is greater than the doping concentration of the channel region 2A, so that electrical conduction between the source region 2B and the source 4 can be achieved.

[0081] See also Figure 2 The channel region 2A extends from the surface of the epitaxial layer 22 away from the substrate 21 to the inside of the epitaxial layer 22 .

[0082] For example, see Figure 2 , the depth of the source region 2B is smaller than the depth of the channel region 2A.

[0083] For example, see Figure 2 , at least a portion of the channel region 2A is adjacent to the gate oxide layer (eg Figure 2 The oxide layer M in, or for example Figure 3 The structure in which the oxide layer M in the gate region 2 is combined with the third oxide layer M3 is in contact with each other, thereby facilitating the formation of a channel in the channel region 2A under the control of the gate 3.

[0084] For example, see Figure 2 The source region 2B contacts the source electrode 4 and the channel region 2A respectively, so as to form a good ohmic contact between the source region 2B and the source electrode 4.

[0085] For example, Figure 2 As shown, the second substrate 2 may further include a contact region 2C.

[0086] The contact region 2C can be formed by doping the epitaxial layer 22 with a high concentration (eg, P+ doping).

[0087] See also Figure 2 The contact region 2C extends from the surface of the source substrate 21 of the epitaxial layer 22 to the interior of the epitaxial layer 22 .

[0088] For example, see Figure 2 The contact region 2C can contact the source region 2B and the channel region 2A respectively, so that a short circuit can occur between the source region 2B and the channel region 2A, thereby preventing the PN junction between the source region 2B and the channel region 2A from being turned on.

[0089] For example, see Figure 2 In the field effect transistor 10, both sides of the gate 3 (eg Figure 2 A channel region 2A, a source region 2B and a contact region 2C are provided on both sides of the gate 3 (left and right sides), thereby ensuring that a conductive channel can be formed on both sides of the gate 3 of the SiC MOSFET (ie, the field effect transistor 10).

[0090] It should be noted that in the drawings provided in the embodiments of the present application, only the relative position relationship of the channel region 2A, the source region 2B and the contact region 2C is exemplarily illustrated, and the relative position relationship of the three may also undergo other possible deformations, and the present application does not impose any restrictions on this.

[0091] In addition, the doping types of the aforementioned channel region 2A, source region 2B and contact region 2C are merely exemplary descriptions. In other embodiments, the doping types of these structures may be completely opposite to those described above, and the present application does not impose any limitation on this.

[0092] It should be noted that, in the present application, the aforementioned P or P+ indicates that holes are the majority carriers, and the aforementioned N-, N+ or N++ indicates that electrons are the majority carriers. In addition, the "+" marked on N or P indicates that the doping concentration is higher than the doping concentration of the structure not marked with +, and the "-" marked on N or P indicates that the doping concentration is lower than the doping concentration of the structure not marked with -. It can be understood that the more "+" there are, the higher the doping concentration is, and similarly, the more "-" there are, the lower the doping concentration is.

[0093] It should also be noted that the comparison of the doping concentrations of the two structures in the present application only refers to the comparison of the concentrations of the impurities doped in the two structures, and does not limit the composition of the impurities and the substrate used to dope the impurities, that is, the composition of the impurities can be the same or different, and the material of the substrate used to dope the impurities can be the same or different.

[0094] See also Figure 2 The oxide layer M is disposed on the second substrate 2 , and the gate 3 is disposed on a side of the oxide layer M away from the second substrate 2 .

[0095] The oxide layer M is used as at least a part of a gate oxide layer and is disposed between the channel region 2A and the gate 3 to achieve electrical insulation between the channel region 2A and the gate 3 .

[0096] The oxide layer M is bonded to the second substrate 2 .

[0097] It should be noted that the "bonding arrangement" herein may refer to a technology that directly bonds the oxide layer M and the second substrate 2 under certain conditions, and bonds the wafers together through van der Waals force, molecular force, or even atomic force. Alternatively, it may refer to other technologies that can bond the oxide layer M and the second substrate 2 to each other, which is not limited in this application.

[0098] See also Figure 2 and Figure 3 , the oxide layer M covers at least a portion of the channel region 2A, specifically, see Figure 2 and Figure 3 The oxide layer M is disposed between the gate 3 and the channel region 2A to achieve electrical insulation between the gate 3 and the channel region 2A, so that the gate 3 has the ability to control the formation of a channel in the channel region 2A.

[0099] It should be noted that the term “covering” herein may include a situation where the oxide layer M and the channel region 2A are in direct contact, or may include a situation where the two are in indirect contact, for example, see Figure 2 , the oxide layer M serves as a gate oxide layer and is in direct contact with the channel region 2A, or, for example, see Figure 3The oxide layer M covers the channel region 2A, and a third oxide layer M3 is disposed between the oxide layer M and the channel region 2A. The oxide layer M and the third oxide layer M3 together form a gate oxide layer that contacts the channel region 2A.

[0100] The oxide layer M is formed by oxidizing a silicon material. For example, the oxide layer M can be formed by oxidizing a silicon wafer.

[0101] Exemplarily, the material of the oxide layer M may include silicon dioxide. Exemplarily, the dielectric constant of the oxide layer M may be greater than or equal to 3.9, thereby ensuring good electrical insulation performance between the gate 3 and the channel region 2A.

[0102] In the related art, a silicon carbide substrate (i.e., the second substrate) is usually directly subjected to high-temperature thermal oxidation to form silicon dioxide on its surface, and the silicon dioxide is used as a gate oxide layer. In order to obtain a high-quality gate oxide layer, the oxidation temperature during high-temperature thermal oxidation needs to be controlled at 1400°C to 1600°C, which consumes a lot of energy and is difficult to process.

[0103] In addition, in order to facilitate the control of the aforementioned high-temperature oxidation temperature, people often use expensive high-temperature and low-pressure oxidation furnace tubes dedicated to silicon carbide products, which has high production costs and brings great economic pressure.

[0104] On the other hand, by thermally oxidizing the silicon carbide substrate to form a gate oxide layer, there are dangling bonds, carbon clusters and a large number of interface states at the SiC / SiO2 interface (i.e., the second substrate and the gate oxide layer). These interface traps will bind the carriers in the inversion layer, resulting in a decrease in the device current density. At the same time, the bound carriers will produce Coulomb scattering on the free carriers in the channel, resulting in a decrease in the channel mobility and the conduction characteristics of the device. Although the SiC / SiO2 interface can be nitrided by subsequent annealing after high-temperature thermal oxidation to improve the channel mobility, the channel mobility is still much lower than that of silicon carbide materials.

[0105] On the other hand, it is currently difficult to prepare a gate oxide layer having a thickness greater than 50 nm by the high temperature thermal oxidation process.

[0106] In the field effect transistor 10 provided in the embodiment of the present application, by bonding the oxide layer M to the second substrate 2, and by using the oxide layer M formed by oxidation of the silicon material as at least part of the gate oxide layer, it is possible to ensure that the gate oxide layer has good quality, for example, to ensure that the dielectric constant of the gate oxide layer is high, the degree of oxidation is high, etc., thereby improving the reliability of the field effect transistor 10. In addition, there are fewer impurity elements (such as carbon) remaining on the interface of the oxide layer M formed by oxidation of the silicon material, thereby effectively reducing the interface state density between the gate oxide layer and the channel region 2A, improving the channel mobility of the field effect transistor 10, and thus improving the electrical performance of the field effect transistor 10.

[0107] In some embodiments, Figure 3 As shown, the second substrate 2 may further include a third oxide layer M3.

[0108] See also Figure 3 The third oxide layer M3 is disposed between the channel region 2A and the oxide layer M. One side of the third oxide layer M3 is in contact with the channel region 2A, and the other side is bonded to the oxide layer M.

[0109] The third oxide layer M is bonded to the oxide layer M and is jointly used as a gate oxide layer and is disposed between the gate 3 and the channel region 2A to achieve electrical insulation between the gate 3 and the channel region 2A.

[0110] The third oxide layer M3 is formed by oxidizing silicon carbide material. For example, the third oxide layer M3 is formed by oxidizing a portion of the second substrate 2 made of silicon carbide material away from the base 21 .

[0111] Exemplarily, the material of the third oxide layer M3 is silicon dioxide.

[0112] By oxidizing the side of the second substrate 2 close to the oxide layer M into a third oxide layer M3, the bonding effect between the second substrate 2 and the oxide layer M can be improved. For example, the materials of the oxide layer M and the third oxide layer M3 are both silicon dioxide, and the bonding difficulty of two structures of the same material is lower and the bonding strength is higher.

[0113] In some embodiments, the ratio of the thickness of the third oxide layer M3 to the thickness of the oxide layer M is 1:5-1:20.

[0114] Exemplarily, the thickness of the third oxide layer M3 may be The thickness of the oxide layer M can be

[0115] By controlling the ratio of the thickness of the third oxide layer M3 to the thickness of the oxide layer M to be 1:5 to 1:20, the third oxide layer M3 is ensured to have a smaller thickness, the proportion of the oxide layer M formed by oxidation of silicon material in the gate oxide layer is increased, and the proportion of the third oxide layer M3 formed by oxidation of silicon carbide material is reduced, so that the third oxide layer M3 can be prepared by a lower temperature process, avoiding high-temperature and long-term oxidation treatment of the second substrate 2, thereby reducing the probability of interface defects formed between SiC / SiO2.

[0116] In some embodiments, the preparation temperature of the gate oxide layer is less than or equal to 1150° C. For example, the preparation temperature of the gate oxide layer may be 1150° C., 1000° C., 756.5° C., 300.67° C., or 56° C., etc.

[0117] For example, see Figure 2and Figure 3 In the case where there is an oxide layer M between the gate 3 and the channel region 2A of the field effect transistor 10, the oxidation temperature of the oxide layer M during the oxidation process is less than or equal to 1150°C.

[0118] For example, see Figure 3 In the case where there is a third oxide layer M3 between the gate 3 and the channel region 2A of the field effect transistor 10, the oxidation temperature of the third oxide layer M3 during the oxidation process is less than or equal to 1150°C.

[0119] By controlling the preparation temperature of the gate oxide layer (oxide layer M, or the combined structure of oxide layer M and third oxide layer M3) to be less than or equal to 1150°C, the interface defects between SiC / SiO2 can be greatly reduced, thereby improving the electrical performance and reliability of the field effect transistor 10.

[0120] In some embodiments, the portion of the second substrate 2 located in the channel region 2A is adjacent to the gate oxide layer (eg Figure 2 The oxide layer M in the Figure 3 The interface state density between the oxide layer M in the structure after the oxide layer M and the third oxide layer M3 are combined (i.e., the interface state density at the SiC / SiO2 interface) is less than or equal to 10 11 / eV·cm 2 .

[0121] For example, see Figure 2 In the case where only the oxide layer M is provided between the gate 3 and the channel region 2A, the interface state density between the portion of the second substrate 2 located in the channel region 2A and the oxide layer M is less than or equal to 10 11 / eV·cm 2 .

[0122] Or, for example, see Figure 3 In the case where the second substrate 2 includes the third oxide layer M3, the interface state density between the portion of the second substrate 2 located in the channel region 2A and the third oxide layer M3 is less than or equal to 10 11 / eV·cm 2 .

[0123] It can be understood that in the field effect transistor 10, there are a large number of interface states at the SiC / SiO2 interface (i.e., the interface between the second substrate 2 and the gate oxide layer) (interface states refer to some discrete or continuous electronic energy levels or energy bands whose energy values ​​are located in the silicon bandgap. The higher the interface state, the lower the channel mobility).

[0124] In the field effect transistor 10 provided in the embodiment of the present application, the interface state density between the second substrate 2 and the gate oxide layer (ie, SiC / SiO2) is set to be less than or equal to 10 11 / eV·cm2 , which can effectively improve the channel mobility of the field effect transistor 10, thereby improving the electrical performance and reliability of the field effect transistor 10.

[0125] In some embodiments, the material of the gate 3 includes single crystal silicon.

[0126] By setting the material of the gate 3 to include single crystal silicon, the electronic characteristics of the gate 3 can be improved, the stability of the gate 3 can be increased, and the performance of the field effect transistor 10 can be further optimized.

[0127] It should be noted that the material of the gate 3 may also include polysilicon, so that the field effect transistor 10 can be flexibly used in different application scenarios.

[0128] In some embodiments, the gate 3 can be integrally provided with the oxide layer M. For example, both can be prepared from the same silicon wafer. For example, a portion of the silicon wafer is oxidized to form an oxide layer M, and a portion of the silicon wafer in contact with the oxide layer M is processed to form polycrystalline silicon (i.e., the gate 3). Thus, while achieving the preparation of a high-performance single-crystal silicon gate 3, the same silicon wafer can be shared, thereby reducing the difficulty of preparing the gate 3 and improving the preparation efficiency of the field effect transistor 10.

[0129] Alternatively, in other embodiments, the gate 3 can also be prepared by other methods. For example, a gate material can be deposited on the side of the oxide layer M away from the second substrate 2 to form the gate 3. The embodiments of the present application do not limit the specific process of the gate 3.

[0130] In some embodiments, Figure 2 and Figure 3 As shown, the field effect transistor 10 further includes a source 4 and a drain 5 .

[0131] See also Figure 2 and Figure 3 At least part of the source 4 can be disposed on the second substrate 2 and in contact with the source region 2B, thereby facilitating the input of the source signal.

[0132] See also Figure 2 and Figure 3 The drain is arranged on a side of the second substrate 2 away from the oxide layer M.

[0133] For example, see Figure 2 and Figure 3 The drain electrode 5 is disposed on a side of the substrate 21 away from the epitaxial layer 22 and in contact with the substrate 21 , thereby facilitating input of a drain signal.

[0134] For example, the source electrode 4 and the drain electrode 5 may be made of one or more conductive materials such as nickel, titanium, platinum and gold.

[0135] It should be noted that the positions of the source 4 and the drain 5 can be interchanged according to the application scenario. Figure 2 , the source 4 can be located on the side surface of the second substrate 2 where the gate 3 is set, and the drain 5 can be located on the side of the second substrate 2 away from the gate 3. In other embodiments, the source 4 can be located on the side of the second substrate 2 away from the gate 3, and the drain 5 can be located on the side surface of the second substrate 2 where the gate 3 is set. This application does not limit this.

[0136] It is understandable that when the gate 3 controls the formation of a channel in the second substrate 2, the source 4 and the drain 5 can be conductive. On the contrary, the source 4 and the drain 5 are insulated from each other, thereby realizing the opening or closing of the field effect transistor 10.

[0137] In order to solve the aforementioned technical problems such as low channel mobility and poor device reliability, the embodiment of the present application further provides a method for preparing a field effect transistor 10.

[0138] Figure 4 A diagram of the steps for preparing the field effect transistor 10 provided in an embodiment of the present application. Figure 7 to Figure 22 1 and 2 are cross-sectional views corresponding to various steps of manufacturing the field effect transistor 10 .

[0139] In some embodiments, Figure 4 As shown, the method for preparing the field effect transistor 10 includes the following steps S1 to S5:

[0140] S1: Figure 7 As shown, a first substrate 1 is provided.

[0141] The material of the first substrate 1 includes silicon.

[0142] Exemplarily, the first substrate 1 may be a silicon wafer.

[0143] See also Figure 7 The first substrate 1 includes a functional layer 11 and a sacrificial layer 12 which are stacked.

[0144] Understandably, see Figure 7 The functional layer 11 and the sacrificial layer 12 are stacked.

[0145] The functional layer 11 is a portion of the first substrate 1 used to form a corresponding structure (eg, gate oxide layer M) of the field effect transistor 10 , and the sacrificial layer 12 is a portion of the first substrate 1 that needs to be removed later.

[0146] It can be understood that the functional layer 11 and the sacrificial layer 12 are respectively part of the silicon wafer (first substrate 1 ), and the materials of both are silicon.

[0147] For example, Figure 7 As shown, step S1 may include:

[0148] S11 : injecting target ions into a set thickness of the first substrate 1 to form a bubble layer 13 .

[0149] See also Figure 7 The bubble layer 13 separates the first substrate 1 into a functional layer 11 and a sacrificial layer 12 .

[0150] Exemplarily, in step S11 , the target ions implanted into the first substrate 1 may be hydrogen ions.

[0151] Exemplarily, the aforementioned “set thickness” is approximately the thickness of the oxide layer M to be formed subsequently.

[0152] Exemplarily, in step S11, the treatment temperature when injecting the target ions may be 300° C., and the treatment time may be 2 hours.

[0153] S2: Figure 8 to Figure 10 As shown, the first substrate 1 and the second substrate 2 are bonded together.

[0154] The material of the second substrate 2 includes silicon carbide.

[0155] It should be noted that the "bonding arrangement" herein may refer to a technology that directly bonds the first substrate 1 and the second substrate 2 under certain conditions, and bonds the wafers together through van der Waals force, molecular force, or even atomic force. Alternatively, it may refer to other technologies that can bond the first substrate 1 and the second substrate 2 to each other, which is not limited in this application.

[0156] For example, it is understood that if Figure 8 and Fig. 9 As shown, step S2 may also include:

[0157] S21 : providing a substrate 21 , and growing an epitaxial layer 22 on the substrate 21 to form a second substrate 2 .

[0158] S22: forming the channel region 2A, the source region 2B and the contact region 2C.

[0159] For example, Fig. 9 As shown, step S22 may include the following steps S221 to S223:

[0160] S221: setting a first mask K1 on the epitaxial layer 22, and doping the epitaxial layer 22 according to the first mask K1 to form a channel region 2A.

[0161] Exemplarily, the channel region 2A may be P-type doped. For example, the ions implanted during the doping process may be chloride ions, boron ions, indium ions, or the like.

[0162] It can be understood that in other embodiments, the doping type of the channel region 2A can also be N-type (for example, the doping ions can be phosphorus ions, arsenic ions, etc.), and the doping type of the channel region 2A can be set differently according to different application scenarios, and the present application does not impose any restrictions on this.

[0163] S222: Disposing a second mask K2 on the epitaxial layer 22, and doping the epitaxial layer 22 according to the second mask K2 to form a contact region 2C.

[0164] For example, Fig. 9 As shown, the epitaxial layer 22 may be doped within the range of the channel region 2A, so that part of the channel region 2A forms the contact region 2C. That is, part of the channel region 2A may be doped to form the contact region 2C.

[0165] Exemplarily, the doping type of the contact region 2C may be the same as the doping type of the channel region 2A. For example, when the doping type of the channel region 2A is P-type doping, the doping type of the contact region 2C may also be P-type doping.

[0166] Exemplarily, the doping concentration of the contact region 2C may be greater than the doping concentration of the channel region 2A. For example, the channel region 2A may be P-doped and the contact region 2C may be P+-doped.

[0167] S223: setting a third mask K3 on the epitaxial layer 22, and doping the epitaxial layer 22 according to the third mask K3 to form a source region 2B.

[0168] For example, Fig. 9 As shown, the epitaxial layer 22 can be doped in the range of the channel region 2A and the range of the contact region 2C at the same time to form the source region 2B. That is, part of the channel region 2A and part of the contact region 2C can be doped to form the source region 2B, so that the formed source region 2B can contact the channel region 2A and the contact region 2C at the same time.

[0169] Exemplarily, the doping type of the source region 2B may be different from the doping type of the channel region 2A and the contact region 2C. For example, when the channel region 2A and the contact region 2C are P-type doped, the source region 2B may be N-type doped.

[0170] Exemplarily, the doping concentration of the source region 2B may be greater than the doping concentration of the portion of the epitaxial layer 22 close to the substrate 21. For example, when the portion of the epitaxial layer 22 close to the substrate 21 is N-doped, the source region 2B may be N+ doped.

[0171] It is understandable that the specific preparation process of step S22 provided in the embodiment of the present application is only for illustrative purposes, and step S22 can also be implemented in other ways, and the implemented structure can also be appropriately deformed, and the present application does not impose any restrictions on this.

[0172] Illustratively, before performing step S2, the preparation method may further include: cleaning the first substrate 1 and the second substrate 2 respectively.

[0173] For example, the cleaning of the first substrate 1 and the second substrate 2 may be achieved by using a standard wet cleaning process (RCA cleaning).

[0174] Illustratively, the cleaning process may be carried out under the conditions of nitrogen atmosphere and 300° C. for 24 hours.

[0175] By cleaning the first substrate 1 and the second substrate 2 , the electrical performance of the bonding between the two can be effectively improved, and unnecessary defects (such as the presence of impurities) at the interface between the two can be avoided, thereby further improving the electrical performance and stability of the field effect transistor 10 .

[0176] S3: Fig.12 or Fig.14 As shown, at least part of the functional layer 11 is oxidized.

[0177] It can be understood that the aforementioned step S3 is to oxidize at least a portion of the functional layer 11 away from the sacrificial layer 12, so that after the first substrate 1 and the second substrate 2 are bonded, the oxidized portion of the functional layer 11 can serve as a gate oxide layer M in contact with the second substrate 2.

[0178] For example, see Fig.12 , the entire functional layer 11 can be oxidized to form a first oxide layer M1.

[0179] Or, for example, see Fig.14 , part of the functional layer 11 can be oxidized to form a second oxide layer M.

[0180] It can be understood that the “first oxide layer M1” and the “second oxide layer M2” here are both the oxide layers M described in the aforementioned embodiments. Here, the oxide layers M are distinguished and named as “first oxide layer M1” and “second oxide layer M2” only according to the difference in their preparation processes (full oxidation or partial oxidation), and there is no restriction on the size, structure, material, etc. of the two.

[0181] The material of the functional layer 11 is silicon material. By oxidizing at least a portion of the functional layer 11, an oxide layer M (a first oxide layer M1 or a second oxide layer M2) made of silicon dioxide can be formed. The oxide layer M can be used as at least a portion of the gate oxide layer of the field effect transistor 10 (for example, it can be used as a gate oxide layer alone, or together with the third oxide layer M3 as a gate oxide layer). The oxide layer M prepared from silicon material has higher quality, for example, a higher degree of oxidation, less residue at the interface (SiC / SiO2 interface), a lower interface state density, etc., thereby effectively reducing the probability of current breakdown of the gate oxide layer and improving the reliability of the field effect transistor 10.

[0182] For example, the oxidation temperature when oxidizing at least part of the functional layer 11 may be less than or equal to 1150° C., for example, 1150° C., 1000° C., 756.5° C., 300.67° C., or 56° C. The oxidation time may be 0.5 h to 1.5 h, for example, 0.5 h, 0.75 h, 1 h, or 1.5 h.

[0183] In the method for preparing the field effect transistor 10 provided in the embodiment of the present application, the gate oxide layer can be prepared at a relatively low temperature (less than or equal to 1150°C), avoiding the process of directly performing high-temperature thermal oxidation on silicon carbide (the second substrate 2) to form a gate oxide layer, thereby reducing the difficulty of preparing the field effect transistor 10, reducing energy consumption during the preparation process, and reducing preparation costs.

[0184] S4: Fig.11 or Fig.18 As shown, the sacrificial layer 12 is removed.

[0185] For example, the sacrificial layer 12 may be removed by mechanical grinding or the like.

[0186] Or, for example, Fig.11 or Fig.18 As shown, in the case where the first substrate 1 includes the bubble layer 13, the sacrificial layer 12 can be removed by heat treatment.

[0187] For example, the first substrate 1 may be cleaved at the location of the bubble layer 13 by heat treatment, so as to achieve peeling between the functional layer 11 and the sacrificial layer 12 .

[0188] It is understandable that the method of removing the sacrificial layer 12 is not limited to the method described in the embodiment of the present application.

[0189] Exemplarily, the bonding setting of the first substrate 1 and the second substrate 2 may be completed before removing the sacrificial layer 12 (ie, step S4 is located after step S2 ) so as to reduce the bonding difficulty between the first substrate 1 and the second substrate 2 .

[0190] S5: Fig.13 or Fig.19 As shown, a gate 3 is formed.

[0191] There are many methods for forming the gate 3, for example:

[0192] For example, see Fig.13 After removing the sacrificial layer 12, the method for forming the gate 3 (ie, step S5) may be:

[0193] S5A: doping the first sublayer 11A (ie, the portion of the functional layer 11 away from the second substrate 2 ) to form a gate 3 .

[0194] Or, for example, see the following Fig.19 After removing the sacrificial layer 12 and forming the first oxide layer M1, the method for forming the gate 3 (ie, step S5) may also be:

[0195] S5B: depositing a gate material on the first oxide layer M1 (ie, a side of the first oxide layer M1 away from the second substrate 2 ) to form a gate 3 .

[0196] By oxidizing the silicon material (first substrate 1) to silicon dioxide (i.e., oxide layer M) to form a gate oxide layer, the process of directly performing high-temperature thermal oxidation on silicon carbide (second substrate 2) to form a gate oxide layer can be avoided, thereby reducing the difficulty of preparing the field effect transistor 10. In addition, the preparation method adopted in the embodiment of the present application can avoid the use of high-cost equipment such as high-temperature thermal oxidation furnaces, effectively reducing the preparation cost of the field effect transistor 10. In addition, by oxidizing the silicon material to form an oxide layer M, or performing low-temperature oxidation on the silicon carbide material to form a third oxide layer M3, an excellent interface between SiC / SiO2 (i.e., between the channel region 2A and the gate oxide layer) can be ensured, thereby reducing the density of interface defects, and even the interface state density can be reduced to less than or equal to 10 11 / eV·cm 2 , thereby improving the channel mobility of the field effect transistor 10. In addition, by preparing silicon dioxide as the oxide layer M through a separate silicon wafer (i.e., the first substrate 1), the thickness of the gate oxide layer can be controlled as required without being limited to less than 50nm, which broadens the applicable scenarios of the field effect transistor 10.

[0197] It is understandable that the order of steps in the above-mentioned preparation method is not fixed, and the order of steps can be adjusted accordingly according to actual conditions if feasible.

[0198] Two specific embodiments are provided below to provide a detailed and exemplary description of the method for preparing the field effect transistor 10 .

[0199] Figure 5FIG. 1 is a flow chart of the preparation of the field effect transistor 10 corresponding to the first embodiment.

[0200] Embodiment 1:

[0201] like Figure 5 ,as well as Figure 7 to Figure 13 As shown, the preparation method comprises the following steps:

[0202] S1: Figure 7 As shown, a first substrate 1 is provided.

[0203] S2: Fig.10 As shown, the first substrate 1 and the second substrate 2 are bonded together.

[0204] Understandably, see Figure 8 and Fig. 9 Before bonding the first substrate 1 and the second substrate 2, the above-mentioned step S21 and step S22 may also be included. Fig.10 In step S2, the functional layer 11 of the first substrate 1 and the second substrate 2 are bonded together.

[0205] S4: Fig.11 As shown, the sacrificial layer 12 is removed.

[0206] For example, the first substrate 1 may be heat treated to break the bubble layer 13 in the first substrate 1 , thereby removing the sacrificial layer 12 .

[0207] Exemplarily, the sacrificial layer 12 may be removed by other methods, such as mechanical grinding, etc., which is not limited in the present application.

[0208] S3: Fig.12 As shown, the entire functional layer 11 is oxidized to form a first oxide layer M1.

[0209] The first oxide layer M1 is used as a gate oxide layer M of the field effect transistor 10 .

[0210] Through the above process, the silicon layer (i.e., the functional layer 11 in the first substrate 1) is transferred to the second substrate 2 by bonding, and then the functional layer 11 is oxidized to obtain the gate oxide layer M, thereby achieving the purpose of forming the gate oxide layer M on the silicon carbide substrate. Compared with the oxidation of silicon carbide, the oxidation temperature when the first substrate 1 made of silicon material is oxidized is lower, which, on the one hand, reduces the difficulty of preparing the gate oxide layer M, and on the other hand, improves the interface defects between SiC / SiO2 and reduces the interface state density between the two, thereby improving the channel mobility of the field effect transistor 10 and improving the electrical performance and stability of the field effect transistor 10.

[0211] For example, Figure 5 As shown, in this embodiment, the preparation method further includes:

[0212] S5A: Fig.13 As shown, a gate material is deposited on the first oxide layer M1 to form a gate 3 .

[0213] Exemplarily, the gate 3 may be prepared by using low pressure chemical vapor deposition (LP-CVD) technology.

[0214] Exemplarily, the gate material may be a conductive material such as poly-Si.

[0215] Exemplarily, in step S5A, the preparation temperature of the gate 3 may be 600° C. to 650° C., for example, 600° C., 621.5° C., 637.28° C. or 650° C.

[0216] Figure 6 FIG. 1 is a flow chart of the preparation of the field effect transistor 10 corresponding to the second embodiment.

[0217] Embodiment 2:

[0218] like Figure 6 , Figure 7 to Figure 9 as well as Figures 14 to 19 As shown, the preparation method may include the following steps:

[0219] S1: Figure 7 As shown, a first substrate 1 is provided.

[0220] S3: Fig.14 As shown, part of the functional layer 11 is oxidized to form a second oxide layer M2.

[0221] The second oxide layer M2 can be used as a gate oxide layer.

[0222] S2: Fig.15 or Fig.17 As shown, the first substrate 1 and the second substrate 2 are bonded together.

[0223] Understandably, see Figure 8 and Fig. 9 Before bonding the first substrate 1 and the second substrate 2, the aforementioned step S21 and step S22 may also be included.

[0224] After forming the gate oxide layer (i.e., the second oxide layer), the bonding arrangement between the first substrate 1 and the second substrate 2 is performed so that the gate oxide layer is arranged on the silicon carbide substrate, which can avoid the process of preparing the gate oxide layer being restricted by the silicon carbide substrate (i.e., the second substrate 2), thereby improving the oxidation degree of the gate oxide layer and improving the electrical performance of the field effect transistor 10. In addition, it can further avoid the generation of interface defects at the interface between the gate oxide layer and the silicon carbide substrate in a high temperature environment, thereby further improving the channel mobility of the field effect transistor 10, and improving the electrical performance and stability of the field effect transistor 10.

[0225] Exemplarily, in this embodiment, step S2 may further include:

[0226] S23: Fig.16 As shown, part of the second substrate 2 is oxidized to form a third oxide layer M3.

[0227] Exemplarily, the oxidation temperature during the process of oxidizing part of the second substrate 2 to form the third oxide layer M3 is less than or equal to 1150° C., for example, 1150° C., 1000° C., 756.5° C., 300.67° C., or 56° C. The oxidation time may be 0.5 h to 1.5 h, for example, 0.5 h, 0.75 h, 1 h, or 1.5 h.

[0228] S24: Fig.17 As shown, the third oxide layer M3 and the second oxide layer M2 are bonded together.

[0229] See also Fig.16 In step S23, the side of the second substrate 2 that needs to be bonded with the first substrate 1 is oxidized, so that the formed third oxide layer M3 can be bonded with the second oxide layer M2 formed by oxidation of the functional layer 11, and together serve as a gate oxide layer.

[0230] By partially oxidizing the second substrate 2 , the relative surfaces of the first substrate 1 and the second substrate 2 are made of silicon dioxide, thereby improving the bonding degree between the two and optimizing the bonding effect, thereby further improving the stability of the field effect transistor 10 .

[0231] Exemplarily, the ratio of the thickness of the third oxide layer M3 to the thickness of the second oxide layer M2 may be 1:5 to 1:20.

[0232] For example, the thickness of the third oxide layer M3 may be The thickness of the second oxide layer M2 can be

[0233] That is, the third oxide layer M3 formed by oxidation on the second substrate 2 is a thin layer, so high temperature and long time oxidation can also be avoided, thereby avoiding the interface defects of SiC / SiO2.

[0234] S4: Fig.18 As shown, the sacrificial layer is removed.

[0235] For example, see Figure 6 In this embodiment, the preparation method further comprises:

[0236] S5B: Fig.19 As shown, the first sub-layer 11A is doped to form a gate 3 .

[0237] The first sublayer 11A refers to the unoxidized portion of the functional layer 11. Fig.15 and Fig.17 , the first sub-layer 11A is disposed between the second oxide layer M2 and the sacrificial layer 12. For example, see Fig.18 After the sacrificial layer 12 is removed, the first sub-layer 11A is located on a side of the second oxide layer M2 away from the second substrate 2 .

[0238] The gate 3 made of single crystal silicon can be prepared by this method. On the one hand, the preparation difficulty is relatively low, and on the other hand, the stability of the gate 3 in the field effect transistor 10 can be effectively improved.

[0239] In some embodiments, see Figure 20 to Figure 22 The method for preparing the field effect transistor 10 may further include the following steps S7 to S9:

[0240] S7: Fig. 20 As shown, the gate 3 and the gate oxide layer (the gate oxide layer is taken as the oxide layer M as an example in the figure) are patterned.

[0241] Step S7 is used to obtain the gate 3 and the oxide layer M of target size, and to drain the source region 2B and the contact region 2C.

[0242] S8: Fig.21 As shown, an interlayer dielectric layer 6 is formed.

[0243] Exemplarily, the interlayer dielectric layer 6 has an electrical insulation property. For example, the material of the interlayer dielectric layer 6 may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0244] See also Fig.21 The interlayer dielectric layer 6 covers the top surface and side surfaces of the gate 3 and the side surfaces of the gate oxide layer M, thereby protecting the gate 3 and the oxide layer M to prevent them from being damaged in subsequent processes or from unexpected electrical connections.

[0245] S9: Fig. 22 As shown, a source electrode 4 and a drain electrode 5 are formed.

[0246] Exemplarily, the source electrode 4 and the drain electrode 5 may include one or more conductive materials such as nickel, titanium, platinum and gold.

[0247] See also Fig. 22 At least part of the source 4 is disposed on the second substrate 2, and the source 4 is in contact with the source region 2B to implement the input of the source signal.

[0248] For example, see Fig. 22 The source electrode 4 is in contact with the source region 2B and the contact region 2C at the same time.

[0249] See also Fig. 22 , the drain electrode 5 is disposed on a side of the second substrate 2 away from the oxide layer M. For example, see Fig. 22 The drain electrode 5 is in contact with a base 21 with a higher doping concentration (for example, N+ doping) in the second substrate 2, thereby improving the input effect of the drain electrode signal.

[0250] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A field effect transistor, characterized in that: include: a second substrate; The material of the second substrate includes silicon carbide; the second substrate includes a source region and a channel region, and the doping concentration of the source region is greater than the doping concentration of the channel region; Oxide layer; The oxide layer is bonded to the second substrate; the oxide layer covers at least a portion of the channel region; The oxide layer is formed by oxidation of silicon material; A gate is arranged on a side of the oxide layer away from the second substrate.

2. The field effect transistor according to claim 1, characterized in that The second substrate also includes a third oxide layer, which is formed by oxidation of silicon carbide material; the third oxide layer is arranged between the channel region and the oxide layer, the third oxide layer is bonded to the oxide layer, and the third oxide layer is in contact with at least part of the channel region.

3. The field effect transistor according to claim 2, characterized in that: The ratio of the thickness of the third oxide layer to the thickness of the oxide layer is 1:5 to 1:

20.

4. The field effect transistor according to any one of claims 1 to 3, characterized in that The oxidation temperature of the oxide layer during the oxidation process is less than or equal to 1150° C.; In the case where the second substrate includes a third oxide layer, an oxidation temperature of the third oxide layer during an oxidation process is less than or equal to 1150° C.

5. The field effect transistor according to any one of claims 1 to 4, characterized in that The material of the gate includes single crystal silicon; the gate is integrally arranged with the oxide layer.

6. The field effect transistor according to any one of claims 1 to 5, characterized in that The interface state density between the portion of the second substrate located in the channel region and the oxide layer is less than or equal to 10 11 / eV·cm 2 ; or, In the case where the second substrate includes a third oxide layer, an interface state density between a portion of the second substrate located in the channel region and the third oxide layer is less than or equal to 10 11 / eV·cm 2 .

7. The field effect transistor according to any one of claims 1 to 6, characterized in that Also includes: A source electrode, at least partially disposed on the second substrate and in contact with the source region; The drain is arranged on a side of the second substrate away from the oxide layer.

8. A method for preparing a field effect transistor, characterized in that: include: Providing a first substrate; the material of the first substrate comprises silicon, and the first substrate comprises a functional layer and a sacrificial layer which are stacked; The first substrate is bonded to a second substrate; the material of the second substrate includes silicon carbide, and the functional layer is in contact with the second substrate; oxidizing at least a portion of the functional layer; removing the sacrificial layer; A gate is formed.

9. The preparation method according to claim 8, characterized in that: After removing the sacrificial layer, oxidizing at least a portion of the functional layer comprises: The entire functional layer is oxidized to form a first oxide layer.

10. The preparation method according to claim 9, characterized in that: The forming of the gate comprises: A gate material is deposited on the first oxide layer to form a gate.

11. The preparation method according to claim 8, characterized in that: Before bonding the first substrate to the second substrate, oxidizing at least a portion of the functional layer comprises: A portion of the functional layer away from the sacrificial layer is oxidized to form a second oxide layer.

12. The preparation method according to claim 11, characterized in that: The unoxidized portion of the functional layer serves as a first sublayer, and the first sublayer is located between the second oxide layer and the sacrificial layer; After removing the sacrificial layer, forming a gate comprises: The first sublayer is doped to form a gate.

13. The preparation method according to claim 11 or 12, characterized in that: The step of bonding the first substrate to the second substrate comprises: oxidizing a portion of the second substrate to form a third oxide layer; The third oxide layer and the second oxide layer are bonded together.

14. The preparation method according to any one of claims 8 to 13, characterized in that: Providing the first substrate includes: injecting target ions into a set thickness of the first substrate to form a bubble layer; the bubble layer separates the first substrate into the functional layer and the sacrificial layer; The removing of the sacrificial layer comprises: performing a heat treatment on the first substrate to crack the first substrate at the location of the bubble layer, so as to peel off the sacrificial layer.

15. An integrated circuit, characterized in that: include: The field effect transistor according to any one of claims 1 to 7; The electronic device is electrically connected to the field effect transistor.

16. An electronic device, characterized in that: include: The integrated circuit as claimed in claim 15; A circuit board, on which the integrated circuit is arranged.

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