Through-silicon via structures and methods of forming the same

Abstract

The application provides a through silicon via structure and a forming method thereof. The forming method comprises the following steps: providing a silicon substrate, the silicon substrate comprising a first surface and a second surface; forming a ring-shaped groove in the silicon substrate and filling the ring-shaped groove with metal to form a ring-shaped metal layer, and the surface of the ring-shaped metal layer is flush with the first surface; forming a dielectric layer on the surface of the ring-shaped metal layer and the first surface; forming a mask layer comprising a through silicon via pattern on the second surface, wherein the orthographic projection of the aperture of the through silicon via pattern falls within the inner diameter of the ring-shaped metal layer, and the diameter of the aperture is smaller than the inner diameter of the ring-shaped metal layer; etching the silicon substrate with the mask layer as a mask and stopping on the dielectric layer, and exposing the inner wall of the ring-shaped metal layer to form a through silicon via. The technical scheme can improve the quality of the through silicon via.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to a through-silicon via (TSV) structure and a method for forming the same. Background Technology

[0002] Through-Silicon Via (TSV) technology is the core and most important supporting technology for 3D ICs. TSV technology can provide the shortest chip-to-chip interconnects, the smallest pad size, and the smallest pitch. Currently, over 95% of TSV vias are fabricated using the Bosch DRIE process. Unlike previous processes that relied primarily on a balance between ion etching and polymer passivation, the Bosch process uses alternating etching and passivation. Due to the directionality of the ion beam bombardment, only the polymer at the bottom of the via is removed, thus etching primarily occurs along the depth direction of the via.

[0003] However, TSV holes made using the DRIE Bosch process still have many defects, such as scallop, undercut, and notching. Summary of the Invention

[0004] The technical problem to be solved by this application is to improve the quality of through silicon vias.

[0005] To address the aforementioned technical problems, this application provides a method for forming a through-silicon via (TSV) structure, comprising: providing a silicon substrate, the silicon substrate including a first surface and a second surface opposite to each other; forming an annular groove in the silicon substrate and filling the annular groove with metal to form an annular metal layer, wherein the surface of the annular metal layer is flush with the first surface; forming a dielectric layer on the first surface and the surface of the annular metal layer; forming a mask layer including a TSV pattern on the second surface, wherein the aperture of the TSV pattern is orthographically projected into the inner diameter of the annular metal layer, and the diameter of the aperture is smaller than the inner diameter of the annular metal layer; using the mask layer as a mask, etching the silicon substrate and stopping at the dielectric layer, thereby exposing the inner wall of the annular metal layer to form a TSV.

[0006] In this embodiment, the difference between the aperture of the through-silicon via pattern and the inner diameter of the annular metal layer is 0.01 μm to 0.02 μm, the thickness of the annular metal layer is 500 angstroms to 1000 angstroms, and the diameter of the bottom of the through-silicon via is equal to the inner diameter of the annular metal layer.

[0007] In this embodiment of the application, the method for forming an annular groove in the silicon substrate includes: patterning a first surface of the silicon substrate; and etching the silicon substrate from the first surface to form the annular groove.

[0008] In this embodiment of the application, the process of filling the annular groove with metal includes: depositing metal into the annular groove and the first surface using an electroplating process; and grinding the metal so that the surface of the metal is flush with the first surface.

[0009] In this embodiment of the application, the etching process for forming the through-silicon via includes: etching a portion of the silicon substrate using a main etching process, wherein in the main etching process, the selectivity ratio of the silicon substrate to the dielectric layer is (15-20):1, and the etching rate of the silicon substrate by the main etching process is 3 μm / min to 3.5 μm / min; and continuing to etch the silicon substrate using an over-etching process and stopping on the dielectric layer, wherein in the over-etching process, the selectivity ratio of the silicon substrate to the dielectric layer is (60-80):1, and the etching rate of the silicon substrate by the over-etching process is 1 μm / min to 1.5 μm / min.

[0010] In this embodiment of the application, the ratio of the thickness of the silicon substrate removed by the main etching process to the thickness of the silicon substrate removed by the over-etching process is 1:(0.08~0.12).

[0011] In this embodiment, the material of the annular metal layer includes at least one of copper, nickel, and tungsten.

[0012] In the embodiments of this application, the dielectric layer is a single-layer structure or a stacked structure, and the material of the dielectric layer includes silicon oxide and / or silicon nitride.

[0013] In this embodiment, the ratio of the height of the through-silicon via to the thickness of the mask layer is 1:(0.08~0.12).

[0014] In this embodiment of the application, after the through-silicon via is formed, the forming method further includes: performing a thermal annealing process, wherein the temperature of the thermal annealing process is 200℃~350℃ and the time is 10min~20min.

[0015] In this embodiment of the application, after the thermal annealing process, the forming method further includes: forming an oxide layer on the wall of the through-silicon via.

[0016] In the embodiments of this application, the thickness of the oxide layer is 100 angstroms to 150 angstroms.

[0017] This application also provides a through-silicon via (TSV) structure, fabricated using the above-described method for forming a TSV structure, comprising: a silicon substrate, the silicon substrate including opposing first and second surfaces; an annular metal layer located in the silicon substrate, the surface of the annular metal layer being flush with the first surface; a dielectric layer located on the first surface and the surface of the annular metal layer; and a TSV extending from the second surface of the silicon substrate into the interior of the silicon substrate and stopping on the dielectric layer, exposing the inner wall of the annular metal layer.

[0018] In this embodiment of the application, the wall of the through silicon via further includes an oxide layer.

[0019] Compared with the prior art, the through-silicon via structure and its formation method in this application have the following advantages:

[0020] When a ring-shaped metal layer is formed in a silicon substrate and the silicon substrate is etched to expose the ring-shaped metal layer, the ions being etched will be guided away by the ring-shaped metal layer because the metal is an excellent conductor. The ions will not continue to be scooped out to the sides, thus preventing notching and providing a good mask morphology for subsequent etching of the dielectric layer, thereby ensuring the morphology of the dielectric layer after etching.

[0021] By employing a main etching process with strong etching capabilities to first etch the silicon substrate to a deeper depth, and then using an over-etching process to continue etching and stop at the dielectric layer, the etching distance required for the over-etching process is reduced, the overall etching rate is improved, and the production capacity is increased.

[0022] After the through-silicon via (TSV) etching is completed, thermal annealing can improve the inner wall of the annular metal layer damaged by ions. Simultaneously, the thermal expansion property of metals reduces the inner diameter of the annular metal layer, thereby improving the diameter uniformity of each part of the TSV. Furthermore, forming an oxide layer on the TSV wall can cover the inner wall of the annular metal layer, allowing subsequent etching of the dielectric layer without altering the current recipe. Attached Figure Description

[0023] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0024] Figure 1 This is a schematic diagram of a through-silicon via (TSV) fabricated using the Bosch process.

[0025] Figure 2SEM image of a through-silicon via fabricated using Bosch process;

[0026] Figure 3 SEM image of the notching morphology of a through-silicon via fabricated using the Bosch process;

[0027] Figure 4 This is a schematic flowchart of a method for forming a through-silicon via structure according to an embodiment of this application;

[0028] Figures 5 to 11 This is a schematic diagram of the steps in the method for forming a through-silicon via (TSV) structure according to an embodiment of this application, wherein... Figure 11 This is a SEM image of the bottom of the through-silicon via structure in an embodiment of this application. Detailed Implementation

[0029] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0030] Currently, most through-silicon vias (TSVs) are fabricated using the Bosch process. The Bosch process employs alternating etching and passivation steps. First, a passivation layer is formed, followed by reactive ion etching. Due to the directionality of ion bombardment, only the passivation layer at the bottom of the TSV is removed; therefore, etching primarily occurs along the depth of the TSV. During TSV etching, the sidewalls of the TSV are continuously bombarded by the ion beam. Furthermore, as the etching depth increases, the time required for both the passivation and etching steps needs to be increased, necessitating a ramp-up recipe. This recipe, akin to a secret formula in industrial automated manufacturing, may include multiple steps in the process, along with various process parameter values ​​and the duration of each step.

[0031] Although passivation and etching capabilities increase with etching, the overall etching effect is further enhanced because silicon via etching must continue. This results in larger scallop A sizes, especially at the junction of mask 10 and silicon via 20, creating a large gap, i.e., undercut morphology B. Figure 1 and Figure 2 As shown, the shape of both the scallop and the undercut significantly affects the subsequent metallic filling effect.

[0032] As the etching depth of through-silicon vias (TSVs) increases, the passivation layer thickness also increases. This necessitates an increasingly powerful etching recipe, requiring a higher selectivity for both the Si substrate and the underlying dielectric layer (ONO). However, the front-end process introduces thickness variation in the Si substrate, necessitating a sufficiently large working window for the etching recipe. Once the thinner Si substrate is etched through first, reaching the underlying ONO, the ion beam rapidly expands outwards to the sidewalls, quickly creating a notching morphology, such as... Figure 3 As shown.

[0033] To improve the notching morphology at the bottom of through-silicon vias (TSVs), some methods adjust the Bosch process recipe by adding over-etching (OE) on top of the main etching (ME) step. Controlling the ratio of the depth step to the etch step, and adjusting the overall etching recipe to a lean state (i.e., a thinner passivation layer with strong etching capability), ensures the etching rates of both ME and OE (primarily guaranteeing the etching rate of the OE portion). Increasing the OE etching depth reduces the thickness variation of the silicon substrate. However, because the etched TSVs are deep, they are continuously bombarded by ions, and thinning the passivation layer can cause increased scallop and sidewall effects such as cell breakage. Increasing the etching recipe to areas with thicker passivation layers to enhance sidewall protection requires a highly uniform passivation layer; otherwise, non-uniform deposition can damage the sidewalls. However, achieving uniform passivation deposition is very difficult, requiring precise matching of process parameters and high-level hardware construction. Meanwhile, when the passivation layer is thick and the ME is far from the bottom, the etching rate of OE is slow; when the distance that OE needs to etch is too long, it is impossible to etch the sidewall morphology of the bottom smoothly and uniformly, and it is easy to form fish scale-like sidewall C( Figure 2 In severe cases, etching may stop. When the ME is close to the bottom, the thickness of the silicon substrate varies considerably. Once the ME comes into contact with the bottom ONO, notching defects will occur, creating an irreconcilable conflict.

[0034] Other methods involve using passivation layer deposition alone to protect the sidewalls. However, this method has a small process window, making it unsuitable for mass production. After etching to a certain depth using the traditional Bosch process, an ALD layer of oxide thickness is deposited on the sidewalls for protection. The Bosch process is then repeated, and this process can be repeated if necessary until the through-silicon via (TSV) etching is complete. Thanks to the protective effect of the oxide layer on the sidewalls, a relatively lean etch recipe can be used, ensuring a high etching rate and ultimately improving the TSV morphology. However, this method adds four extra processes: a cleaning process after Bosch etching to a certain depth, an oxide layer deposition process, an etching process to open the bottom oxide layer, and a subsequent cleaning process. Because the TSVs are deep, maintaining the uniformity of the oxide layer thickness is crucial. Therefore, ALD is used instead of PECVD to deposit the oxide layer, significantly increasing the cost and time, making it unsuitable for mass production.

[0035] Other methods avoid using OE (Optical Encapsulation) to improve wafer variation by precisely controlling the thickness of the incoming wafers. This requires sufficiently precise grinding equipment in the preceding processes, followed by CMP (Chemical Mechanical Polishing) for fine wafer finishing after grinding. Since grinding is a mechanical process, the through-silicon vias (TSVs) on each wafer vary significantly, requiring subsequent CMP to manually polish each wafer according to its thickness, which is difficult to meet mass production requirements.

[0036] In summary, the challenges of through-silicon via (TSV) fabrication lie in the depth of the etched holes. The etching directionality of ions deteriorates in deep holes, necessitating protection of the sidewalls of the etched portions. This requires a relatively thick passivation layer in the recipe. Simultaneously, the etching capability must not be significantly compromised; the etched recipe needs a sufficiently large working window, and the bottom of the TSV must maintain a good morphology. Adding an ALD oxide layer to protect the sidewalls during etching would substantially increase processing time and cost, failing to meet mass production requirements.

[0037] Based on this, the technical solution of this application forms an annular metal layer in the silicon substrate, thereby avoiding notching when etching reaches the bottom of the silicon substrate and contacts the dielectric layer.

[0038] refer to Figure 4 The method for forming a through-silicon via structure according to embodiments of this application includes:

[0039] Step S1: Provide a silicon substrate, the silicon substrate including opposing first and second surfaces;

[0040] Step S2: An annular groove is formed in the silicon substrate, and metal is filled in the annular groove to form an annular metal layer, wherein the surface of the annular metal layer is flush with the first surface;

[0041] Step S3: Form a dielectric layer on the surface of the first surface and the annular metal layer;

[0042] Step S4: Form a mask layer including a through-silicon via pattern on the second surface, wherein the orthographic projection of the aperture of the through-silicon via pattern falls into the inner diameter of the annular metal layer, and the diameter of the aperture is smaller than the inner diameter of the annular metal layer;

[0043] Step S5: Using the mask layer as a mask, etch the silicon substrate and stop on the dielectric layer, exposing the inner wall of the annular metal layer to form a through-silicon via.

[0044] Combination Figure 4 and Figure 5 A silicon substrate 100 is provided. The silicon substrate 100 may be an incoming wafer. The silicon substrate 100 includes a first surface 101 and a second surface 102 opposite to each other. A device structure (not shown) is also formed in the silicon substrate 100, and the device structure may be designed according to actual conditions.

[0045] Combination Figure 5 and Figure 6 A ring-shaped metal layer 200 is formed in the silicon substrate 100. The method for forming the ring-shaped metal layer 200 includes:

[0046] Step S21: Patterning is performed on the first surface 101 of the silicon substrate, and the silicon substrate 100 is etched from the first surface 101 of the silicon substrate 100 to form an annular groove;

[0047] Step S22: Fill the annular groove with metal to form the annular metal layer 200.

[0048] In step S21, since the etched silicon substrate 100 is relatively thin, a non-Bosch etching process can be used. During etching, the first surface 101 is kept facing upwards and the second surface is kept facing downwards. The formed annular groove is used to define the annular metal layer 200.

[0049] In step S22, metal is first deposited onto the annular groove and the first surface 101 using an electroplating process. The electroplating process includes: sequentially forming a barrier layer and a seed layer (not shown) on the sidewalls and bottom of the annular groove and on the first surface 101; then electroplating metal (ECP) onto the seed layer, filling the annular groove with the metal. Next, the metal is ground until its surface is flush with the first surface 101, forming the annular metal layer 200. Chemical mechanical polishing (CMP) can be used during grinding to remove the barrier layer, seed layer, and metal from the first surface 101. The material of the annular metal layer 200 includes at least one of copper, nickel, and tungsten.

[0050] The thickness of the annular metal layer 200 needs to be strictly controlled. If the thickness of the annular metal layer 200 is too large, the inner wall of the annular metal layer 200 will be exposed too early during subsequent etching processes. This will cause the ion beam to contact the annular metal layer 200 too early and be preferentially guided away by the annular metal layer 200, resulting in incomplete etching. If the thickness of the annular metal layer 200 is too small, the ion beam cannot be guided away in time. In the embodiments of this application, the thickness of the annular metal layer 200 should be around 700 angstroms, for example, 500 angstroms to 1000 angstroms.

[0051] refer to Figure 7 A dielectric layer 300 is formed on the surfaces of the first surface 101 and the annular metal layer 200. The dielectric layer 300 can be a single-layer structure or a stacked structure. The material of the dielectric layer 300 includes silicon oxide and / or silicon nitride. In this embodiment, the dielectric layer 300 includes a stacked first silicon oxide layer 310, a first silicon nitride layer 320, a second silicon oxide layer 330, and a second silicon nitride layer 340. The thickness of the dielectric layer 300 is determined according to actual conditions.

[0052] refer to Figure 8After forming the dielectric layer 300, the second surface 102 is positioned upwards. A mask layer 400 is formed on the second surface 102. The mask layer 400 has a through-silicon via (TSV) pattern 401, wherein the orthographic projection of the aperture of the TSV pattern 401 falls within the inner diameter of the annular metal layer 200, and the aperture d1 of the TSV pattern 401 is smaller than the inner diameter d2 of the annular metal layer 200. This ensures that the subsequent TSV etching process can be completed smoothly, preventing the plasma from contacting the annular metal before the TSV etching is finished, thus preventing the TSV etching from failing. Simultaneously, it prevents the bottom CD from expanding significantly compared to other locations during the TSV etching process. In this embodiment, the difference between the aperture d1 of the TSV pattern 401 and the inner diameter d2 of the annular metal layer 200 is 0.01 μm to 0.02 μm. As an example, the aperture d1 of the through-silicon via pattern 401 is 5 μm, and the inner diameter d2 of the annular metal layer 200 is 5.01 μm to 5.02 μm. The ratio of the height of the through-silicon via to the thickness of the mask layer 400 is 1:(0.08 to 0.12), for example, the height of the through-silicon via is 50 μm, and the thickness of the mask layer 400 is 4 μm.

[0053] refer to Figure 9 Using the mask layer 400 as a mask, the silicon substrate 100 is etched and the etching stops on the dielectric layer 300 to form a through-silicon via 500. In this embodiment, the etching stops on the first silicon oxide 310. During the downward etching process, the ion beam located in the center first contacts the dielectric layer 300 at the bottom. Since the etching recipe has a low etching rate on the dielectric layer 300, it continues to etch the silicon substrate 100 on both sides. At the same time, the ion beam at the edge also etches the silicon substrate 100 downward. When the ion beam contacts the annular metal layer 200, the etched ion beam is preferentially guided away by the annular metal layer 200, causing the etching to stop. This avoids the problem of the ion beam, which could not etch the dielectric layer 300 and instead moved to the sides to scoop out the silicon substrate 100, thus avoiding the formation of notching morphology. When the etching stops, the inner wall of the annular metal layer 200 is exposed. The diameter of the bottom of the through-silicon via 500 is equal to the inner diameter of the annular metal layer 200.

[0054] The etching process for etching the silicon substrate 100 to form the through-silicon via 500 includes: etching a portion of the silicon substrate using a main etching process, wherein in the main etching process, the selectivity ratio of the silicon substrate to the dielectric layer is (15-20):1, and the etching rate of the main etching process on the silicon substrate is 3 μm / min to 3.5 μm / min; and continuing to etch the silicon substrate using an over-etching process and stopping on the dielectric layer, wherein in the over-etching process, the selectivity ratio of the silicon substrate to the dielectric layer is (60-80):1, and the etching rate of the over-etching process on the silicon substrate is 1 μm / min to 1.5 μm / min.

[0055] Currently, the main etching process cannot etch too deeply into the silicon substrate. For example, when the silicon substrate 100 is 50 μm thick, the main etching process can only etch up to 45 μm, leaving 5 μm etched using an over-etching process. This results in significant defects in the current etching process. If any area is thinner than 45 μm, notching will immediately occur at the bottom when the main etching process reaches it. Because the over-etching process has weak etching capability, if the over-etching thickness exceeds 5 μm, etching will stall as byproducts increase. The existing process has almost no process window; that is, once the silicon substrate thickness exceeds 50 μm, etching will fail. Therefore, this phenomenon is generally avoided by reducing the main etching thickness. However, with the process method of this application, the thickness of the main etching process can be increased to 48 μm to 50 μm, with the remainder etched using an over-etching process, thus providing a 6% to 10% process window. Simultaneously, it avoids the phenomenon of notching that occurs when thin areas prematurely contact the underlying dielectric layer due to over-etching. The main etching process has a relatively deep etching depth, while the over-etching process will not exceed 5μm. Even if the thickness of the silicon substrate on the wafer slightly exceeds 50μm in some locations, etching can still be guaranteed. In the embodiments of this application, the ratio of the thickness of the silicon substrate 100 removed by the main etching process to the thickness of the silicon substrate 100 removed by the over-etching process is 1:(0.08~0.12).

[0056] The etching process combines main etching and over-etching, reducing the etching distance required for the over-etching process and increasing the etching rate. Furthermore, by appropriately increasing the etching time, the wafer thickness variation introduced by the front-end processes can be mitigated. The morphology of the bottom of the etched through-silicon via 500 is deep in the center and shallow at the edges, as shown in the image. Figure 10 As shown.

[0057] After the via 500 is formed, a thermal annealing process is performed. This process slightly expands the metal, repairing the damage caused by ion beam bombardment to the inner wall of the annular metal layer 200, resulting in a smoother and more uniform surface of the subsequently deposited film. The slight expansion of the metal reduces the inner diameter of the annular metal layer 200, thereby reducing the diameter of the bottom of the via 500. This improves the uniformity of the diameter of each part of the via 500 and facilitates subsequent etching of the dielectric layer 300. The thermal annealing process is performed at a temperature of 200℃ to 350℃ for 10 to 20 minutes.

[0058] refer to Figure 11 After the thermal annealing process, the method further includes forming an oxide layer 600 on the wall of the through-silicon via 500, wherein the oxide layer 600 can cover the inner wall of the annular metal layer 200. In this embodiment, a thinner oxide layer 600 can cover the exposed portion of the annular metal layer 200 and minimize the reduction in the inner diameter of the etched through-silicon via 500. The oxide layer 600 is formed by atomic layer deposition (ALD), and the film formed by ALD has good uniformity. Although the ALD process is time-consuming and costly, the oxide layer 600 deposited in this embodiment is thin, which is beneficial for increasing yield and reducing costs, making it suitable for mass production. In this embodiment, the thickness of the oxide layer 600 is 100 angstroms to 150 angstroms. The oxide layer 600 can effectively cover the annular metal layer 200, preventing the plasma from being carried away by the metal in subsequent etching processes. Furthermore, the thickness of the oxide layer 600 is negligible compared to the thickness of the first silicon oxide layer 310 in the dielectric layer 300 to be etched. Therefore, the current recipe can be left unchanged, and the subsequent etching process of the dielectric layer 300 can continue.

[0059] This application also provides a through-silicon via (TSV) structure fabricated by the above-described method for forming a TSV structure. The TSV structure includes: a silicon substrate 100, comprising a first surface 101 and a second surface 102 opposite to each other; an annular metal layer 200 located within the silicon substrate 100, with its surface flush with the first surface 101; a dielectric layer 300 located on the surfaces of the first surface 101 and the annular metal layer 200; and a TSV 500 extending from the second surface 102 of the silicon substrate 100 into the interior of the silicon substrate 100 and ending on the dielectric layer 300, exposing the inner wall of the annular metal layer 200. In some embodiments, the wall of the TSV 500 further includes an oxide layer 600.

[0060] The method for forming a through-silicon via (TSV) structure according to the embodiments of this application forms an annular metal layer in a silicon substrate. When the silicon substrate is etched to expose the annular metal layer, the etching step is completed, and a TSV is formed. The formation method has a large process window for differences in silicon substrate thickness within the same wafer and between wafers, and the bottom of the formed TSV does not produce notching, which significantly improves the morphology of the TSV.

[0061] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0062] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0063] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0065] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a through-silicon via (TSV) structure, characterized in that, include: A silicon substrate is provided, the silicon substrate including opposing first and second surfaces; An annular groove is formed in the silicon substrate, and metal is filled in the annular groove to form an annular metal layer, wherein the surface of the annular metal layer is flush with the first surface; A dielectric layer is formed on the surface of the first surface and the surface of the annular metal layer; A mask layer including a through-silicon via pattern is formed on the second surface, wherein the aperture of the through-silicon via pattern is projected into the inner diameter of the annular metal layer, and the diameter of the aperture is smaller than the inner diameter of the annular metal layer. Using the mask layer as a mask, the silicon substrate is etched and the etching stops on the dielectric layer, exposing the inner wall of the annular metal layer to form a through-silicon via.

2. The method for forming a through-silicon via structure according to claim 1, characterized in that, The difference between the aperture of the through-silicon via pattern and the inner diameter of the annular metal layer is 0.01 μm to 0.02 μm, the thickness of the annular metal layer is 500 angstroms to 1000 angstroms, and the diameter of the bottom of the through-silicon via is equal to the inner diameter of the annular metal layer.

3. The method for forming a through-silicon via structure according to claim 1, characterized in that, The method for forming annular grooves in the silicon substrate includes: The first surface of the silicon substrate is patterned; The annular groove is formed by etching the silicon substrate from the first surface.

4. The method for forming a through-silicon via structure according to claim 1, characterized in that, The process of filling the annular groove with metal includes: Metal is deposited onto the annular groove and the first surface using an electroplating process; The metal is ground until its surface is flush with the first surface.

5. The method for forming a through-silicon via structure according to claim 1, characterized in that, The etching process for forming the through-silicon via includes: The silicon substrate is partially etched using a main etching process, wherein the selectivity ratio of the silicon substrate to the dielectric layer in the main etching process is (15~20):1, and the etching rate of the silicon substrate in the main etching process is 3μm / min~3.5μm / min; The silicon substrate is further etched using an over-etching process and the etching stops on the dielectric layer. In the over-etching process, the selectivity ratio of the silicon substrate to the dielectric layer is (60~80):1, and the etching rate of the silicon substrate by the over-etching process is 1μm / min~1.5μm / min.

6. The method for forming a through-silicon via structure according to claim 5, characterized in that, The ratio of the thickness of the silicon substrate removed by the main etching process to the thickness of the silicon substrate removed by the over-etching process is 1:(0.08~0.12).

7. The method for forming a through-silicon via structure according to claim 1, characterized in that, The material of the annular metal layer includes at least one of copper, nickel, and tungsten.

8. The method for forming a through-silicon via structure according to claim 1, characterized in that, The dielectric layer is a single-layer structure or a multilayer structure, and the material of the dielectric layer includes silicon oxide and / or silicon nitride.

9. The method for forming a through-silicon via structure according to claim 1, characterized in that, The ratio of the height of the through-silicon via to the thickness of the mask layer is 1:(0.08~0.12).

10. The method for forming a through-silicon via structure according to claim 1, characterized in that, After the through-silicon via is formed, the forming method further includes: performing a thermal annealing process, wherein the temperature of the thermal annealing process is 200℃~350℃ and the time is 10min~20min.

11. The method for forming a through-silicon via structure according to claim 10, characterized in that, After the thermal annealing process, the forming method further includes: forming an oxide layer on the wall of the through-silicon via.

12. The method for forming a through-silicon via structure according to claim 11, characterized in that, The thickness of the oxide layer is 100 angstroms to 150 angstroms.

13. A through-silicon via (TSV) structure, characterized in that, The through-silicon via (TSV) structure is fabricated using the method for forming the TSV structure according to any one of claims 1 to 12, characterized in that it comprises: A silicon substrate, the silicon substrate including opposing first and second surfaces; A ring-shaped metal layer is located in the silicon substrate, and the surface of the ring-shaped metal layer is flush with the first surface; A dielectric layer is located on the surface of the first surface and the surface of the annular metal layer; A through-silicon via extends from the second surface of the silicon substrate into the interior of the silicon substrate and terminates on the dielectric layer, exposing the inner wall of the annular metal layer.

14. The through-silicon via structure according to claim 13, characterized in that, The walls of the through-silicon via also include an oxide layer.

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