A circuit board of a POFV design and a method of manufacturing the same

Abstract

The application discloses a POFV designed circuit board and a preparation method thereof. The preparation method of the POFV designed circuit board comprises the following steps: obtaining a processing plate piece provided with a conductive layer on at least one target side, wherein at least one POFV designed through hole is formed in the processing plate piece, and the hole opening of each through hole is covered by the corresponding conductive layer; removing the conductive layer on the target side of the processing plate piece, and retaining the conductive layer corresponding to the hole opening of each through hole; performing whole plate flash plating on the target side of the processing plate piece, so as to form a base layer on the target side of the processing plate piece; and performing electroplating on the target side of the processing plate piece, so as to form a conductive circuit on the base layer and a pad on the conductive layer corresponding to the hole opening of each through hole, thereby obtaining the circuit board. Through the above method, the preparation of the high aspect ratio circuit board with the fine circuit of the POFV design can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of printed circuit board, and particularly relates to a POFV designed circuit board and a preparation method thereof. BACKGROUND

[0002] With the development of product miniaturization and multi-function, the number of components to be loaded is greatly increased, and the space left for the point board is smaller and smaller, so it is a trend to make high-density lines.

[0003] At present, there are various methods for making fine lines, but if a fine line with a POFV (Plating Over Filled Via) design is encountered, it is helpless; the fine line is made by first preparing a pattern line and a hole, and then plugging the hole; the plugging and baking process of the board will damage the dry film, the tin surface and the fine line. If a subtractive process is used to make POFV, due to the existence of side etching effect, fine lines cannot be prepared.

[0004] In general, there is no process that can make POFV designed through holes and meet the requirements of fine lines, so it is difficult to realize the fine line board with POFV design by the existing process. SUMMARY

[0005] The application provides a POFV designed circuit board and a preparation method thereof, to solve the problem that it is difficult to make a fine line circuit board with a POFV design.

[0006] To solve the above technical problems, the application provides a POFV designed circuit board preparation method, which comprises the following steps: obtaining at least one target side of a processing board part provided with a conductive layer, wherein at least one POFV designed through hole is formed in the processing board part, and the hole of each through hole is covered by the corresponding conductive layer; removing the conductive layer on the target side of the processing board part and retaining the conductive layer corresponding to the hole of each through hole; performing whole plate flash plating on the target side of the processing board part to form a primer layer on the target side of the processing board part; performing electroplating on the target side of the processing board part to form a conductive line on the primer layer and a pad on the conductive layer corresponding to the hole of each through hole, so as to obtain a circuit board.

[0007] The step of removing the conductive layer on the target side of the processing board part and retaining the conductive layer corresponding to the hole of each through hole comprises the following steps: attaching a first protective layer on the side of the conductive layer corresponding to the hole of each through hole away from the processing board part; etching the target side of the processing board part to remove the conductive layer on the target side of the processing board part and retain the conductive layer corresponding to the hole of each through hole; and removing the first protective layer.

[0008] The step of attaching the first protective layer to the side of the conductive layer corresponding to the hole of each through hole away from the processing plate member includes: attaching the first protective layer to the entire target side of the processing plate member; and exposing and developing the first protective layer to retain the first protective layer corresponding to the hole of each through hole.

[0009] The step of electroplating the target side of the processing plate member to form the conductive circuit on the base layer and the pads on the conductive layer corresponding to the hole of each through hole to obtain the circuit board includes: attaching the second protective layer to the target side of the processing plate member except the conductive circuit and the conductive layer corresponding to the hole of each through hole; performing whole plate electroplating on the target side of the processing plate member to form the conductive circuit on the base layer and the pads on the conductive layer corresponding to the hole of each through hole; removing the second protective layer and performing flash etching on the target side of the processing plate member until the base layer corresponding to the second protective layer is removed to obtain the circuit board.

[0010] The step of attaching the second protective layer to the target side of the processing plate member except the conductive circuit and the conductive layer corresponding to the hole of each through hole includes: attaching the second protective layer to the entire target side of the processing plate member; and exposing and developing the second protective layer based on the track of the conductive circuit to expose the preset positions and attach the second protective layer to the positions except the preset positions, the preset positions being the positions corresponding to the conductive circuit and the conductive layer corresponding to the hole of each through hole.

[0011] The flash etching amount of the flash etching ranges from 1 to 6 microns, and the thickness of the base layer ranges from 1 to 5 microns.

[0012] The step of obtaining the processing plate member with the conductive layer attached to the entire target side includes: obtaining the compression plate member and preparing the through hole designed according to the POFV design on the compression plate member; and electroplating the target side of the compression plate member until the conductive layer is formed to obtain the processing plate member.

[0013] The step of preparing the through hole designed according to the POFV design on the compression plate member includes: drilling the compression plate member to form at least one hole on the compression plate member; the hole includes a through hole and / or a blind hole; metalizing the hole wall of each hole and resin plugging each hole to align the hole of each hole with the corresponding outer side of the compression plate member to obtain the through hole designed according to the POFV design.

[0014] The thickness of the pad is greater than the thickness of the conductive circuit.

[0015] To solve the above technical problems, the application further provides a POFV designed circuit board prepared by the POFV designed circuit board preparation method, comprising: a board body, at least one POFV designed through hole is formed on the board body, and a solder pad is formed at the outermost side of the board body; and a conductive circuit, which is arranged on the target side of the board body.

[0016] To solve the above technical problems, the POFV designed circuit board preparation method can prevent the fine circuit from being damaged by the hole plugging and baking process, and can shorten the preparation time, so as to realize the preparation of the fine circuit board with a high thickness-diameter ratio and a POFV design. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a flowchart of an embodiment of the POFV designed circuit board preparation method provided by the application;

[0018] Figure 2 is a flowchart of another embodiment of the POFV designed circuit board preparation method provided by the application;

[0019] Figure 3 is Figure 2 is a preparation flow structure diagram of the embodiment;

[0020] Figure 4 is a structure diagram of an embodiment of the POFV designed circuit board provided by the application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0022] It should be noted that if the embodiments of the application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0023] In addition, if the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor in the protection scope required by the present application.

[0024] Please refer to Figure 1 , Figure 1 is an embodiment of the method for manufacturing a circuit board provided by the present application.

[0025] Step S11: Obtain at least one target side of the processing plate piece provided with a conductive layer.

[0026] The processing plate piece is a multilayer plate piece, for example: the processing plate piece can be a 5-layer circuit board, an 8-layer circuit board, a 10-layer circuit board, a 20-layer circuit board, a 30-layer circuit board, etc., which is not limited here.

[0027] In one specific application scenario, the processing plate piece can include at least one layer of dielectric layer and at least one layer of conductive layer which are sequentially stacked and attached. In another specific application scenario, the processing plate piece can include a core plate and at least one layer of dielectric layer and at least one layer of conductive layer which are sequentially stacked and attached on at least one side of the core plate. The specific structure of the processing plate piece is not limited here.

[0028] At least one POFV (Plating Over Filled) designed through-hole is formed in the processing plate piece, and the hole of each through-hole is covered by the corresponding conductive layer. The through-hole is used to connect different conductive layers in the processing plate piece to realize interlayer connection.

[0029] The number of through-holes can be set based on actual needs, for example: 5, 10, 20, 100, 200 or 500, etc., which is not limited here.

[0030] The target side is the side where the hole of the through-hole on the processing plate piece is located. One target side or opposite two target sides of the processing plate piece can be used to set the hole of the through-hole.

[0031] Step S12: Remove the conductive layer on the target side of the processing plate piece, and retain the conductive layer corresponding to the hole of each through-hole.

[0032] In a specific application scenario, the conductive layer on the target side of the processing plate can be etched after the protective layer is attached to the conductive layer corresponding to the hole of each through hole, so as to remove the conductive layer on the target side of the processing plate and retain the conductive layer corresponding to the hole of each through hole.

[0033] In a specific application scenario, the conductive layer on the target side of the processing plate can be removed by laser depth control or mechanical depth control, and the conductive layer corresponding to the hole of each through hole can be retained.

[0034] After this step, the conductive layer corresponding to the hole of each through hole protrudes from other positions of the processing plate.

[0035] The conductive layer on the target side of the processing plate is removed to leave a space for preparing the conductive circuit. The conductive layer corresponding to the hole of each through hole is retained to prevent the removal step from affecting the conductivity of the through hole and to improve the structural stability and reliability of the through hole.

[0036] Step S13: The target side of the processing plate is flash plated to form a base layer on the target side of the processing plate.

[0037] Flash plating refers to obtaining an extremely thin plating layer on the surface of the plated object in a very short time with a large current density.

[0038] After the conductive layer on the target side of the processing plate is removed, a base layer is flash plated on the target side, covering the position where the conductive layer is removed on the target side and the conductive layer corresponding to the hole of each through hole. The thickness of the base layer is less than the thickness of the conductive layer.

[0039] The base layer helps to make fine lines after electroplating and etching. The base layer can include but is not limited to a copper layer, a silver layer, a gold layer, an aluminum layer or other alloy layers.

[0040] Step S14: Electroplating is performed on the target side of the processing plate to form a conductive circuit on the base layer and a pad on the conductive layer corresponding to the hole of each through hole to obtain a circuit board.

[0041] Since the base layer is previously provided on the target side of the processing plate, metal ions can be attached and accumulated by the base layer during electroplating, thereby thickening and forming a conductive circuit.

[0042] Electroplating is performed on the target side of the processing plate to form a conductive circuit on the base layer, which can realize the preparation of fine lines, and the pad is formed by electroplating thickening on the conductive layer corresponding to the hole of each through hole, which can minimize the distance between the pad and the through hole and increase the thickness of the pad, thereby improving the stability and reliability of the pad signal transmission.

[0043] The preparation method of the POFV designed circuit board provided in the embodiment can prevent the fine circuit from being damaged in the hole plugging and baking process of the through hole, and can obtain the fine circuit and the pad of the through hole with the POFV design in the plating process, thereby shortening the preparation time and realizing the preparation of the high aspect ratio circuit board with the fine circuit and the POFV design.

[0044] The circuit board provided in the embodiment can be applied to the field of semiconductor HDI (High Density Interconnector) high-density circuit or other circuit board fields.

[0045] Through the above steps, the preparation method of the POFV designed circuit board provided in the embodiment can obtain a processing board piece provided with a conductive layer on the target side, at least one POFV designed through hole is formed in the processing board piece, and the hole opening of each through hole is covered by the corresponding conductive layer; the conductive layer on the target side of the processing board piece is removed, and the conductive layer corresponding to the hole opening of each through hole is retained; the target side of the processing board piece is subjected to whole-board flash plating to form a primer layer on the target side of the processing board piece; and finally, electroplating is performed on the target side of the processing board piece to form a conductive circuit on the primer layer and a pad on the conductive layer corresponding to the hole opening of each through hole, thereby obtaining a circuit board. The preparation method can prevent the fine circuit from being damaged in the hole plugging and baking process of the through hole, and can obtain the fine circuit and the pad of the through hole with the POFV design in the plating process, thereby shortening the preparation time and realizing the preparation of the high aspect ratio circuit board with the fine circuit and the POFV design.

[0046] Please refer to Figures 2-3 , Figure 2 is a flowchart of another embodiment of the preparation method of the POFV designed circuit board provided in the embodiment. Figure 3 is Figure 2 the preparation flow structure diagram of the embodiment.

[0047] Step S21: obtaining a pressing board piece, and preparing at least one POFV designed through hole on the pressing board piece; and electroplating on the target side of the pressing board piece until a conductive layer is formed, thereby obtaining a processing board piece.

[0048] Please refer to Figure 3 a, first obtain a pressing board piece 10. The pressing board piece 10 can include at least one dielectric layer 13 and at least one conductive layer 12 which are sequentially stacked and attached. The pressing board piece 10 can be obtained by sequentially placing and pressing the at least one dielectric layer 13 and the at least one conductive layer 12.

[0049] In other embodiments, the processed board can further include a core board, and at least one dielectric layer and at least one conductive layer sequentially and adhesively arranged on at least one side of the core board. The specific structure of the laminated board is not limited here.

[0050] Referring to Figure 3 a. Drilling the laminated board 10 to form at least one hole 11 on the laminated board 10; the hole 11 includes a through hole 111 and / or a blind hole 112.

[0051] The drilling can be laser ablation drilling or mechanical milling drilling. The number of holes 11, the number of through holes 111 and blind holes 112 can be set based on actual needs. The hole opening direction of the hole 11 is also set based on actual needs.

[0052] Further referring to Figure 3 b. Metallizing the hole wall of each hole 11, and resin plugging each hole 11 to make the hole opening of each hole 11 flush with the corresponding outer side of the laminated board 10, to obtain a POFV designed via hole 15. The blind hole 112 and the through hole 111 can form the POFV designed via hole 15 through the above preparation means.

[0053] The step of hole wall metallization can include copper deposition and hole copper plating.

[0054] Electroplating on the target side of the laminated board 10 until the conductive layer 12 is formed to obtain the processed board 14. This embodiment takes the opposite sides of the board as an example when the target side is one side of the board. The subsequent preparation is the same as this embodiment, and will not be repeated here.

[0055] The step of electroplating the conductive layer 12 can include copper deposition and surface copper plating.

[0056] The processed board 14 has at least one POFV designed via hole 15 formed therein, and the hole opening of each via hole 15 is covered by the corresponding conductive layer 12. The via hole 15 formed by the through hole 111 has two hole openings, both of which are covered by the corresponding conductive layer 12. The via hole 15 formed by the blind hole 112 has one hole opening, which is also covered by the corresponding conductive layer 12.

[0057] This embodiment first completes the preparation of the POFV designed via hole 15 on the processed board 14, so that the preparation of the via hole 15 will not affect the preparation of the subsequent fine lines or other structures.

[0058] Step S22: adhesively arranging a first protective layer on the side of the conductive layer corresponding to the hole opening of each via hole away from the processed board; etching the target side of the processed board to remove the conductive layer on the target side of the processed board and retain the conductive layer corresponding to the hole opening of each via hole; and removing the first protective layer.

[0059] Please further refer to Figure 3 c, the first protective layer 16 is attached to the side of the conductive layer 12 corresponding to the hole of each through hole 15 away from the machining plate 14. The first protective layer 16 can be a photosensitive resist film or other protective layer structure. The photosensitive resist film is a kind of high molecular compound, which can produce a polymerization reaction to form a stable substance attached to the plate surface after irradiation by a specific light source, so as to achieve the function of blocking etching or electroplating.

[0060] The setting of the first protective layer 16 can include: setting the first protective layer 16 on the whole plate of at least one target side of the machining plate 14; exposing and developing the first protective layer 16 to retain the first protective layer 16 corresponding to the hole of each through hole 15. In other embodiments, the setting of the first protective layer 16 can also include: first obtaining the first protective layer 16 on the whole plate, then hollowing out the first protective layer 16, and retaining the first protective layer 16 corresponding to the hole of each through hole 15, and finally attaching the hollowed first protective layer to the target side of the machining plate 14.

[0061] The first protective layer 16 is used to protect the conductive layer 12 corresponding to the hole of each through hole 15 from the subsequent etching step, and to ensure the structural stability and reliability of each through hole 15.

[0062] Please further refer to Figure 3 d, etching the target side of the machining plate 14 until the conductive layer 12 on the target side of the machining plate 14 is removed, and the conductive layer 12 corresponding to the hole of each through hole 15 is retained; and finally removing the first protective layer 16.

[0063] That is, this step removes all the conductive layers 12 on the target side of the machining plate 14 except the conductive layers 12 corresponding to the hole of each through hole 15, and exposes the dielectric layer 13 as a substrate for preparing subsequent fine lines. Moreover, the conductive layers 12 corresponding to the hole of each through hole 15 are protected by the first protective layer 16, which can prevent the through holes 15 from being affected by the preparation of fine lines, and ensure the structural stability and reliability of the through holes 15. In addition, the conductive layers 12 corresponding to the hole of each through hole 15 can be used to directly prepare the pads, which maximizes the distance between the through holes 15 and the pads, and realizes the preparation of the pads by using the existing structure, saves the additional pad preparation process, and improves the structural simplicity and preparation efficiency of the circuit board.

[0064] Step S23: whole plate flash plating is performed on the target side of the machining plate to form a primer layer on the target side of the machining plate.

[0065] Please further refer to Figure 3 e, whole plate flash plating is performed on the target side of the machining plate 14 to form a primer layer 17 on the target side of the machining plate 14.

[0066] The primer layer 17 covers the surface and side of the dielectric layer 13 and the conductive layer 12 on the target side of the processing board piece 14.

[0067] The primer layer 17 helps to make the fine line after electroplating thickening and etching. The primer layer 17 can include but is not limited to a copper layer, a silver layer, a gold layer, an aluminum layer or other alloy layer.

[0068] The thickness of the primer layer 17 ranges from 1 to 5 microns, preferably 2 microns, and can be 1 micron, 2 microns, 3 microns, 4 microns or 5 microns, etc. The primer layer 17 in the above thickness range helps to make the fine line after electroplating thickening and etching.

[0069] Before flash plating, the target side of the processing board piece 14 can also be subjected to plasma decontamination, which aims to roughen the substrate surface by electrochemical removal of the resin on the substrate surface, increase the roughness of the substrate surface, enhance the bonding force between the primer layer 17 and the dielectric layer 13, and improve the structural stability.

[0070] Step S24: A second protective layer is arranged on the target side of the processing board piece 14 except the position corresponding to the conductive layer of the conductive line and the hole of each through hole; whole plate electroplating is performed on the target side of the processing board piece to form a conductive line on the primer layer and a pad on the conductive layer corresponding to the hole of each through hole. The second protective layer is removed, and flash etching is performed on the target side of the processing board piece until the primer layer corresponding to the second protective layer is removed, to obtain a circuit board.

[0071] Please further refer to Figure 3 f, a second protective layer 18 is arranged on the target side of the processing board piece 14 except the position corresponding to the conductive layer of the conductive line and the hole of each through hole 15. Specifically, the second protective layer 18 can be arranged on the target side of the processing board piece 14 first; the second protective layer 18 is exposed and developed based on the track of the conductive line to expose the preset position, and the second protective layer 18 is arranged on the position except the preset position. The preset position is the position corresponding to the conductive line and the conductive layer 12 corresponding to the hole of each through hole 15.

[0072] The second protective layer 18 can include but is not limited to a photosensitive anti-plating film or a wet film anti-toxic agent.

[0073] That is, the position corresponding to the conductive line and the conductive layer 12 corresponding to the hole of each through hole 15 are exposed in the embodiment.

[0074] Please further refer to Figure 4g, the target side of the processed plate piece 14 is subjected to whole-board electroplating to thicken the positions of the conductive layer 12 corresponding to the apertures of the through holes 15 and the positions of the conductive circuit 191, form the conductive circuit 191 on the underlying layer 17 and the pads 192 on the conductive layer 12 corresponding to the apertures of the through holes 15, and remove the second protective layer 18 after electroplating.

[0075] Finally, the target side of the processed plate piece 14 is subjected to flash etching until the underlying layer 17 corresponding to the second protective layer 18 is removed, so that the conductive circuits 191 are independent of each other and realize electrical transmission. The structure of the circuit board can be referred to Figure 4 .

[0076] The flash etching amount of the flash etching ranges from 1 to 6 microns, and can be 1 micron, 2 microns, 3 microns, 4 microns, 5 microns or 6 microns, etc., so that the tin-free protective and exposed underlying layer 17 is completely removed, forming the final conductive circuit, and the conductive circuits are independent of each other and do not interfere with each other.

[0077] The thickness of the pad 192 is greater than the thickness of the conductive circuit 191, and the pad 192 is in a stepped structure, so that the pad 192 protrudes from the surface of the plate piece, thereby facilitating the connection between the pad 192 and the external device, reducing the collision between the pad 192 and the external device when the pad 192 is connected to the external device, and increasing the position where the pad 192 can be contacted by the external device, increasing the welding area, and improving the welding effect and reliability.

[0078] The conductive circuit 191 prepared by the above method can realize the preparation of a fine circuit, and can realize the preparation of a fine circuit with a thickness-diameter ratio of 25 / 25um or less.

[0079] Through the above steps, the circuit board preparation method of the POFV designed circuit board of the embodiment first prepares the through hole designed by POFV, and then uses the scheme of etching the substrate to expose the substrate and then electroplating to prepare the fine circuit, which can prevent the fine circuit from being damaged by the plate brushing process after the through hole is plugged and baked, and can prepare the fine circuit and the pad of the through hole designed by POFV at the same time when the circuit is electroplated, thereby reducing the preparation time and realizing the preparation of a fine circuit with a high thickness-diameter ratio of the circuit board with a POFV design. The pad and the conductive circuit are arranged in a stepped manner, so that the pad protrudes from the surface of the plate piece, thereby facilitating the connection between the pad and the external device, reducing the collision between the pad and the external device when the pad is connected to the external device, and increasing the position where the pad can be contacted by the external device, increasing the welding area, and improving the welding effect and reliability.

[0080] Please refer to Figure 4 , ​ is a structural schematic diagram of an embodiment of the POFV designed circuit board provided by the application.

[0081] The POFV designed circuit board 20 of the embodiment comprises a board body 21 and conductive lines 211.

[0082] At least one POFV designed through hole 25 is formed on the board body 21, and a pad 251 is formed on the outermost side of the board body at the aperture of each through hole 25.

[0083] The conductive lines 211 are arranged on the target side of the board body 21. The target side is the side on which the apertures of the through holes 25 are located on the board body 21. One target side or opposite target sides of the board body 21 can be used to arrange the apertures of the through holes 25.

[0084] The board body 21 comprises at least one dielectric layer 22 and at least one conductive layer 23 which are sequentially stacked and arranged in abutment, and the conductive layer 23 has lines formed thereon. Each through hole 25 is connected to different conductive lines 211 and conductive layers 23 to realize interlayer interconnection.

[0085] The thickness of the pad 251 is greater than the thickness of the conductive line 211, and the pad 251 has a stepped structure so as to protrude from the surface of the board, thereby facilitating the connection between the pad 251 and external devices, reducing the collision between the conductive line 211 and external devices when the pad 251 is connected to the external devices, and increasing the position where the pad 251 can be contacted by external devices, increasing the welding area, and improving the welding effect and reliability.

[0086] The POFV designed circuit board is prepared by the POFV designed circuit board preparation method of any one of the above embodiments.

[0087] The circuit board of the embodiment can be compatible with POFV designed through holes and fine lines, and realize a high aspect ratio circuit board with POFV designed fine lines.

[0088] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method for fabricating a circuit board with POFV design, characterized in that, The circuit board fabrication method for the POFV design includes: A processed board with a conductive layer on at least one target side is obtained, wherein at least one POFV-designed through hole is formed in the processed board, and the opening of each through hole is covered by the corresponding conductive layer. Remove the conductive layer on the target side of the processed board, while retaining the conductive layer corresponding to the opening of each of the through holes; wherein, a first protective layer is attached to the side of the conductive layer corresponding to the opening of each of the through holes away from the processed board; etch the target side of the processed board to remove the conductive layer on the target side of the processed board, while retaining the conductive layer corresponding to the opening of each of the through holes; remove the first protective layer; The target side of the processed board is flash plated to form an underlayer on the target side of the processed board; Electroplating is performed on the target side of the processed board to form conductive lines on the underlay and pads on the conductive layer corresponding to the orifices of each of the vias, to obtain a circuit board; wherein a second protective layer is provided on the target side of the processed board at locations other than the conductive lines and the conductive layer corresponding to the orifices of each of the vias; full-board electroplating is performed on the target side of the processed board to form the conductive lines on the underlay and pads on the conductive layer corresponding to the orifices of each of the vias; the second protective layer is removed, and flash etching is performed on the target side of the processed board until the underlay corresponding to the second protective layer is removed, to obtain the circuit board.

2. The method for fabricating a circuit board using the POFV design according to claim 1, characterized in that, The step of attaching a first protective layer to the side of the conductive layer corresponding to the opening of each of the through holes away from the processed plate includes: A first protective layer is provided on at least one target side of the processed plate. The first protective layer is exposed and developed to retain the first protective layer corresponding to the opening of each of the vias.

3. The method for fabricating a circuit board using the POFV design according to claim 1, characterized in that, The step of setting a second protective layer on the target side of the processed board, excluding the conductive layers corresponding to the conductive lines and the orifices of each of the through holes, includes: A second protective layer is provided on the entire plate on the target side of the processed plate. The second protective layer is exposed and developed based on the trajectory of the conductive line to expose a preset position, and a second protective layer is set at positions other than the preset position, wherein the preset position is the position corresponding to the conductive line and the conductive layer corresponding to the opening of each of the through holes.

4. The method for fabricating a circuit board using the POFV design according to claim 1, characterized in that, The flash etch amount ranges from 1 to 6 micrometers, and the thickness of the underlayer ranges from 1 to 5 micrometers.

5. The method for fabricating a circuit board using the POFV design according to claim 1, characterized in that, The step of obtaining a processed board with a conductive layer on at least one target side plate includes: A press-fit plate is obtained, and at least one POFV-designed through hole is prepared on the press-fit plate; Electroplating is performed on the target side of the pressed plate until the conductive layer is formed, thus obtaining the processed plate.

6. The method for fabricating a circuit board using the POFV design according to claim 5, characterized in that, The step of preparing at least one POFV-designed through hole on the press-fit plate includes: Drilling is performed on the pressed plate to form at least one hole; the hole includes a through hole and / or a blind hole; The walls of each hole are metallized and each hole is filled with resin so that the opening of each hole is flush with the corresponding outer side of the pressed plate, thus obtaining the through hole designed by POFV.

7. The method for fabricating a circuit board using the POFV design according to claim 1, characterized in that, The thickness of the pad is greater than the thickness of the conductive line.

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