Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: a substrate; a plurality of word lines located on the top surface of the substrate, each of the word lines extending in a direction parallel to the top surface of the substrate, and the plurality of word lines arranged at intervals in a direction perpendicular to the top surface of the substrate, and any two adjacent word lines are at least partially staggered in the direction perpendicular to the top surface of the substrate. The present disclosure reduces the capacitive coupling effect between two adjacent word lines and helps to control the size of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] In semiconductor structures such as DRAM, multiple word lines are located at the same level, which results in a strong capacitive coupling effect between adjacent word lines, thereby affecting the electrical performance of the semiconductor structure.

[0004] Therefore, how to reduce the capacitive coupling effect between adjacent word lines, thereby improving the performance of the semiconductor structure, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to solve the problem of strong capacitive coupling effect between adjacent word lines, so as to improve the electrical performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, including:

[0007] substrate;

[0008] A plurality of word lines are located on the top surface of the substrate, each of the word lines extends in a direction parallel to the top surface of the substrate, and the plurality of word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered.

[0009] In some embodiments, in a direction perpendicular to the top surface of the substrate, any two adjacent word lines are completely staggered.

[0010] In some embodiments, each of the word lines extends along a first direction, and on a plane formed by the first direction and a direction perpendicular to a top surface of the substrate, projections of any two adjacent word lines partially overlap.

[0011] In some embodiments, in a direction perpendicular to the top surface of the substrate, the plurality of word lines are arranged in sequence, and the projections of any two adjacent odd-numbered word lines on the top surface of the substrate overlap, and the projections of any two adjacent even-numbered word lines on the top surface of the substrate overlap.

[0012] In some embodiments, each of the word lines extends along a first direction, and each of the word lines includes a first end and a second end opposite to the first end along the first direction, and the first direction is a direction parallel to the top surface of the substrate; the semiconductor structure further includes:

[0013] A plurality of word line leads are located on the top surface of the substrate, each of the word line leads extends in a direction perpendicular to the top surface of the substrate, and the plurality of word line leads are electrically connected to the first end portions of the plurality of word lines respectively.

[0014] In some embodiments, among any two adjacent odd-numbered word lines in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction;

[0015] Of any two even-numbered word lines adjacent to each other in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction.

[0016] In some embodiments, among any two adjacent word lines along a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction.

[0017] In some embodiments, each of the word lines extends along a first direction, and each of the word lines includes a first end and a second end opposite to the first end along the first direction, and the first direction is a direction parallel to the top surface of the substrate; the semiconductor structure further includes:

[0018] A plurality of word line leads are located on the top surface of the substrate, each of the word line leads extends in a direction perpendicular to the top surface of the substrate, the word line leads electrically connected to the word lines of odd-numbered bits are all located at the first end of the word lines of odd-numbered bits, and the word line leads electrically connected to the word lines of even-numbered bits are all located at the second end of the word lines of even-numbered bits.

[0019] In some embodiments, each of the word lines includes a first end surface and a second end surface opposite to the first end surface along the first direction;

[0020] The first end surfaces of all the odd-numbered word lines are flush with each other, and the second end surfaces of all the odd-numbered word lines are flush with each other;

[0021] The first end surfaces of all the even-numbered word lines are flush with each other, and the second end surfaces of all the even-numbered word lines are flush with each other.

[0022] In some embodiments, among any two adjacent odd-numbered word lines in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction;

[0023] Of any two adjacent even-numbered word lines in a direction perpendicular to the top surface of the substrate, the second end of one of the word lines closer to the substrate protrudes beyond the second end of the other word line along the first direction.

[0024] In some embodiments, a bottom surface of the word line lead electrically connected to one of the word lines is completely located on the word line.

[0025] In some embodiments, a bottom surface of the word line lead connected to one of the word lines is only partially located on the word line.

[0026] In some embodiments, in a direction perpendicular to the top surface of the substrate, the multiple word lines are arranged in sequence, and the projections of any two adjacent word lines at the 3nth position on the top surface of the substrate overlap, the projections of any two adjacent word lines at the 3n+1th position on the top surface of the substrate overlap, and the projections of any two adjacent word lines at the 3n+2th position on the top surface of the substrate overlap, where n is an integer.

[0027] In some embodiments, it also includes:

[0028] A plurality of semiconductor layers are located on the top surface of the substrate, each of the semiconductor layers comprises a plurality of active pillars arranged at intervals along a first direction, and the plurality of semiconductor layers are arranged at intervals along a direction perpendicular to the top surface of the substrate, each of the active pillars comprises a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction, each of the word lines continuously covers the plurality of channel regions arranged at intervals along the first direction in one of the semiconductor layers, the first direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction is orthogonal to the second direction;

[0029] A plurality of bit lines are located on the top surface of the substrate, each of the bit lines extends in a direction perpendicular to the top surface of the substrate, the plurality of bit lines are arranged at intervals along the first direction, and one bit line is electrically connected to the plurality of source regions arranged at intervals along a direction perpendicular to the top surface of the substrate.

[0030] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure as described in any one of the above items, comprising the following steps:

[0031] providing a substrate;

[0032] A plurality of word lines are formed on the top surface of the substrate, each of the word lines extends in a direction parallel to the top surface of the substrate, and the plurality of word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered.

[0033] In the semiconductor structure and the method for forming the same provided by some embodiments of the present disclosure, each word line extends in a direction parallel to the top surface of the substrate, and in a direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered, so that the facing area between the two adjacent word lines can be reduced, thereby reducing the capacitive coupling effect between the two adjacent word lines, and improving the electrical performance of the semiconductor structure. In addition, the present disclosure reduces the capacitive coupling effect by reducing the facing area between the two adjacent word lines, and the distance between the two adjacent word lines in the direction perpendicular to the top surface of the substrate does not need to be increased, which helps to control the size of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Attached Figure 1 is a schematic diagram of a first top view structure of a semiconductor structure in a specific embodiment of the present disclosure;

[0035] Attached Figure 2 is a schematic diagram of a first three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure;

[0036] Attached Figure 3 is a schematic diagram of a second top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0037] Attached Figure 4 is a schematic diagram of a second three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure;

[0038] Attached Figure 5 It is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0040] This specific embodiment provides a semiconductor structure, Figure 1 is a schematic diagram of a first top view of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 1 is a schematic diagram of a first three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure. The semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM. Figure 1 and Figure 2 As shown, the semiconductor structure comprises:

[0041] substrate;

[0042] A plurality of word lines 15 are located on the top surface of the substrate, each of the word lines 15 extends in a direction parallel to the top surface of the substrate, and the plurality of word lines 15 are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate. In the direction D3 perpendicular to the top surface of the substrate, any two adjacent word lines 15 are at least partially staggered.

[0043] Specifically, the substrate may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate as a silicon substrate as an example. In other embodiments, the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate is used to support the device structure thereon. The word line 15 may be made of a conductive material such as metal tungsten or TiN.

[0044] Specifically, if Figure 1 and Figure 2As shown, each of the word lines 15 extends along a first direction D1 parallel to the top surface of the substrate, and a plurality of the word lines 15 are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate, thereby forming a horizontal word line structure. Compared with the vertical word line structure, the horizontal word line structure provided in this specific embodiment helps to increase the storage density of the semiconductor structure. Along the direction D3 perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered, which means that for two adjacent word lines 15 along the direction perpendicular to the top surface of the substrate, the projection of one word line 15 on the top surface of the substrate is at least partially staggered with the projection of another word line 15 on the top surface of the substrate. Taking the first word line 151 and the second word line 152 adjacent in the direction D3 perpendicular to the top surface of the substrate as an example, the projection of the first word line 151 on the plane formed by the first direction D1 and the second direction D2 and the projection of the second word line 152 on the plane formed by the first direction D1 and the second direction D2 are at least partially staggered, the second direction D2 is a direction parallel to the top surface of the substrate, and the first direction D1 intersects with the second direction D2, and the first direction D1 and the second direction D2 are both perpendicular to the direction D3 perpendicular to the top surface of the substrate. The intersection in this specific embodiment can be a vertical intersection or an oblique intersection.

[0045] In this specific embodiment, any two adjacent word lines 15 are at least partially staggered in the direction D3 perpendicular to the top surface of the substrate, so that the area facing each other between the two adjacent word lines 15 is reduced, thereby reducing the capacitive coupling effect between the two adjacent word lines 15. Moreover, in this specific embodiment, when reducing the capacitive coupling effect between the two adjacent word lines 15, there is no need to increase the spacing between the two adjacent word lines 15 in the direction D3 perpendicular to the top surface of the substrate, so there is no need to increase the size of the semiconductor structure, which helps to further improve the integration of the semiconductor structure.

[0046] In some embodiments, in a direction perpendicular to the top surface of the substrate, any two adjacent word lines 15 are completely staggered.

[0047] Specifically, the plurality of word lines 15 are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate, and any two adjacent word lines 15 are completely staggered, which means that any two adjacent word lines 15 (for example, the adjacent first word line 151 and the second word line 152) along the direction D3 perpendicular to the top surface of the substrate have projections on the top surface of the substrate separated from each other (i.e., they do not overlap each other). By completely staggering the two adjacent word lines 15, the capacitive coupling effect between the two adjacent word lines 15 can be eliminated, thereby better improving the performance of the semiconductor structure.

[0048] In some embodiments, each of the word lines 15 extends along a first direction D1 , and on a plane formed by the first direction D1 and a direction D3 perpendicular to the top surface of the substrate, projections of any two adjacent word lines 15 partially overlap.

[0049] For example, for the first word line 151 and the second word line 152 adjacent to each other in the direction perpendicular to the top surface of the substrate, the projection of the first word line 151 on the plane formed by the first direction D1 and the direction D3 perpendicular to the top surface of the substrate partially overlaps with the projection of the second word line 152 on the plane formed by the first direction D1 and the direction D3 perpendicular to the top surface of the substrate, thereby helping to reduce the spacing between the first word line 151 and the second word line 152 in the direction D3 perpendicular to the top surface of the substrate, so as to further improve the storage density of the semiconductor structure.

[0050] In some embodiments, in a direction perpendicular to the top surface of the substrate, the plurality of word lines 15 are arranged in sequence, and the projections of any two adjacent odd-numbered word lines 15 on the top surface of the substrate overlap, and the projections of any two adjacent even-numbered word lines 15 on the top surface of the substrate overlap.

[0051] Specifically, if Figure 1 and Figure 2As shown, in the direction D3 perpendicular to the top surface of the substrate, the plurality of word lines 15 are arranged in sequence, that is, in the direction D3 perpendicular to the top surface of the substrate, the word lines 15 of the odd-numbered bits (for example, the first word line 151) and the word lines 15 of the even-numbered bits (for example, the second word line 152) are arranged alternately, and any adjacent word lines 15 of the odd-numbered bits and the word lines 15 of the even-numbered bits are at least partially staggered in the direction D3 perpendicular to the top surface of the substrate. The overlap of the projections of any two adjacent word lines 15 of the odd-numbered bits on the top surface of the substrate means that any two adjacent word lines 15 of the odd-numbered bits are aligned in the direction D3 perpendicular to the top surface of the substrate. The overlap of the projections of any two adjacent word lines 15 of the even-numbered bits on the top surface of the substrate means that any two adjacent word lines 15 of the even-numbered bits are aligned in the direction D3 perpendicular to the top surface of the substrate. By setting odd and even word lines, and the projections of any two adjacent word lines 15 of odd bits on the top surface of the substrate overlap, and the projections of any two adjacent word lines 15 of even bits on the top surface of the substrate overlap, the number of masks can be reduced, thereby simplifying the process technology of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure.

[0052] In some embodiments, each of the word lines 15 extends along a first direction D1, and each of the word lines 15 includes a first end 201 and a second end 202 opposite to the first end 201 along the first direction D1, wherein the first direction D1 is a direction parallel to the top surface of the substrate; the semiconductor structure further includes:

[0053] A plurality of word line leads 16 are located on the top surface of the substrate, each of the word line leads 16 extends in a direction D3 perpendicular to the top surface of the substrate, the word line leads 16 electrically connected to the word lines 15 at odd positions are all located at the first end 201 of the word lines at odd positions, and the word line leads 16 electrically connected to the word lines 15 at even positions are all located at the second end 202 of the word lines 15 at even positions.

[0054] Specifically, the plurality of word lines 15 are arranged in sequence along a direction D3 perpendicular to the top surface of the substrate, the word line leads 16 connected to the word lines 15 of odd bits are all located at the first end 201 of the word line 15, and the word line leads 16 connected to the word lines 15 of even bits are all located at the second end 202 of the word line 15, that is, the two word line leads 16 connected to any two adjacent word lines 15 are distributed at opposite ends of the transistor region 11 along the first direction D1 on opposite sides, thereby increasing the distance between the two adjacent word line leads 16 and reducing the capacitive coupling effect between the adjacent word line leads 16, thereby further improving the electrical performance of the semiconductor structure, and also increasing the process window when forming the word line leads 16, reducing the manufacturing difficulty of the semiconductor structure.

[0055] In some embodiments, each of the word lines 15 includes a first end surface 203 and a second end surface opposite to the first end surface 203 along the first direction D1;

[0056] The first end surfaces 203 of all the odd-numbered word lines 15 are flush with each other, and the second end surfaces of all the odd-numbered word lines 15 are flush with each other;

[0057] The first end surfaces of all the word lines 15 of the even-numbered bits are flush with each other, and the second end surfaces of all the word lines 15 of the even-numbered bits are flush with each other.

[0058] Specifically, the first end faces 203 of all the odd-numbered word lines 15 are flush, and the second end faces of all the odd-numbered word lines 15 are flush, which means that the edges of the projections of all the odd-numbered word lines 15 on the top surface of the substrate are completely overlapped. The first end faces of all the even-numbered word lines 15 are flush, and the second end faces of all the even-numbered word lines 15 are flush, which means that the projections of all the even-numbered word lines 15 on the top surface of the substrate are completely overlapped. Since the first end faces 203 of all the odd-numbered word lines 15 are flush, the second end faces of all the odd-numbered word lines 15 are flush, the first end faces of all the even-numbered word lines 15 are flush, and the second end faces of all the even-numbered word lines 15 are flush, there is no need to etch a plurality of the word lines 15 to form a stepped structure, thereby simplifying the manufacturing process of the semiconductor structure. At this time, since the word line lead 16 electrically connected to the word line 15 of the lower layer needs to penetrate the word line 15 of the upper layer, the side wall of the word line lead 16 needs to be covered with an isolation layer to isolate the side wall of the word line lead 16 from the word line 15 of the upper layer. The material of the word line lead 16 can be a conductive material such as metal tungsten, and the material of the isolation layer can be an insulating material such as silicon dioxide.

[0059] In some other embodiments, among any two adjacent odd-numbered word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the first end 201 of one word line 15 closer to the substrate protrudes beyond the first end 201 of the other word line 15 along the first direction D1;

[0060] Among any two adjacent even-numbered word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the second end 202 of one word line 15 closer to the substrate protrudes beyond the second end 202 of the other word line 15 along the first direction D1.

[0061] Specifically, the first ends 201 of the word lines 15 of multiple odd bits together form a step-like structure, and the second ends 202 of the word lines 15 of multiple even bits also together form a step-like structure, so that the word line lead 16 connected to the word line 15 of the lower layer does not need to pass through the word line 15 of the upper layer. On the one hand, the formation process of the word line lead 16 can be simplified; on the other hand, it can also effectively avoid signal crosstalk between adjacent word lines 15.

[0062] Attached Figure 3 is a schematic diagram of a second top view of a semiconductor structure in a specific embodiment of the present disclosure, Figure 4is a schematic diagram of a second three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure. In other embodiments, such as Figure 3 and Figure 4 As shown, each of the word lines 15 extends along a first direction D1, and each of the word lines 15 includes a first end 201 and a second end 202 opposite to the first end 201 along the first direction D1, and the first direction D1 is a direction parallel to the top surface of the substrate; the semiconductor structure further includes:

[0063] A plurality of word line leads 16 are located on the top surface of the substrate. Each of the word line leads 16 extends along a direction D3 perpendicular to the top surface of the substrate. The plurality of word line leads 16 are electrically connected to the first end portions 201 of the plurality of word lines 15 , respectively.

[0064] Specifically, each of the word lines 15 includes the first end 201 and the second end 201, and the plurality of word line leads 16 are electrically connected to the first end 201 of the plurality of word lines 15, respectively, so that the signals of the plurality of word lines 15 can be led out on the same side, thereby helping to reduce the occupied area of ​​the word line leads 16 in the semiconductor structure and improve the space utilization inside the semiconductor structure.

[0065] In some embodiments, among any two adjacent odd-numbered word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the first end 201 of one word line 15 closer to the substrate protrudes beyond the first end 201 of the other word line 15 along the first direction D1;

[0066] Among any two adjacent even-numbered word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the first end 201 of one word line 15 closer to the substrate protrudes beyond the first end 201 of the other word line 15 along the first direction D1.

[0067] Specifically, the first ends 201 of the plurality of odd-numbered word lines 15 together form a step-like structure, and the first ends 201 of the plurality of even-numbered word lines 15 together form a step-like structure, so that the word line lead 16 connected to the odd-numbered or even-numbered word lines 15 of the lower layer does not need to pass through the odd-numbered or even-numbered word lines 15 of the upper layer. On the one hand, the formation process of the word line lead 16 can be simplified; on the other hand, signal crosstalk between adjacent word lines 15 can be effectively avoided.

[0068] In some embodiments, among any two adjacent word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the first end 201 of the word line 15 closer to the substrate protrudes beyond the first end 201 of the other word line 15 along the horizontal direction.

[0069] Specifically, among any two adjacent word lines 15 along the direction D3 perpendicular to the top surface of the substrate, the first end portion 201 of the word line 15 closer to the substrate protrudes horizontally beyond the first end portion 201 of the other word line 15, thereby increasing the distance between the two word line leads 16 respectively connected to the two adjacent word lines 15, reducing the capacitive coupling effect between the adjacent word line leads 16, and further improving the performance of the semiconductor structure.

[0070] In order to enhance the connection stability between the word line 23 and the word line lead 16 , in some embodiments, the bottom surface of the word line lead 16 electrically connected to one of the word lines 15 is completely located on the word line 15 .

[0071] In some other embodiments, the bottom surface of the word line lead 16 connected to one of the word lines 15 is only partially located on the word line 15 .

[0072] Specifically, the bottom surface of the word line lead 16 is only partially located on the word line 15, for example, in the direction D3 perpendicular to the top surface of the substrate, the overlapping area between the projection of the bottom surface of the word line lead 16 and the projection of the word line 15 is greater than or equal to 60% of the total projection area of ​​the bottom surface of the word line lead 16. With this structure, while ensuring the stable electrical connection between the word line lead 16 and the word line 15, it is also possible to increase the process window when forming the word line lead 16, improve the tolerance of the semiconductor structure process, and help improve the yield of the semiconductor structure.

[0073] This specific implementation is described by taking the example that the word line lead 16 is overlapped on the surface of the word line 15 (that is, the word line lead 16 is in contact with the top surface of the word line 15 facing away from the substrate). In other specific implementations, the word line lead 16 can also be embedded in the word line 15, thereby increasing the contact area between the word line lead 16 and the word line 15 and reducing the contact resistance between the word line lead 16 and the word line 15.

[0074] In order to further improve the integration of the semiconductor structure, in some embodiments, in the direction D3 perpendicular to the top surface of the substrate, the multiple word lines 15 are arranged in sequence, and the projections of any two adjacent word lines 15 at the 3nth position on the top surface of the substrate overlap, the projections of any two adjacent word lines 15 at the 3n+1th position on the top surface of the substrate overlap, and the projections of any two adjacent word lines 15 at the 3n+2th position on the top surface of the substrate overlap, where n is an integer.

[0075] In some embodiments, the semiconductor structure further comprises:

[0076] A plurality of semiconductor layers are located on the top surface of the substrate, each of the semiconductor layers includes a plurality of active pillars 131 arranged at intervals along a first direction D1, and the plurality of semiconductor layers are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate, each of the active pillars 131 includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction D2, each of the word lines 15 continuously covers the plurality of channel regions arranged at intervals along the first direction D1 in one semiconductor layer, the first direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate, and the first direction D1 is orthogonal to the second direction D2;

[0077] A plurality of bit lines 17 are located on the top surface of the substrate, each of the bit lines 17 extends along a direction D3 perpendicular to the top surface of the substrate, the plurality of bit lines 17 are arranged at intervals along the first direction D1, and one bit line 17 is electrically connected to a plurality of source regions arranged at intervals along the direction D3 perpendicular to the top surface of the substrate.

[0078] Specifically, the material of the semiconductor layer may be, but is not limited to, silicon. Figure 1 and Figure 2As shown, the top surface of the substrate includes a transistor region 11, and a bit line region 10 and a capacitor region 12 distributed on opposite sides of the transistor region 11 along the second direction D2. The plurality of semiconductor layers are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate, and each of the semiconductor layers includes a plurality of semiconductor pillars 13 arranged at intervals along the first direction D1, and the semiconductor pillars 13 include an active pillar 131 located in the transistor region 11 and a conductive pillar 132 located in the capacitor region 12. The active pillar 131 includes a channel region, and a source region and a drain region located on opposite sides of the channel region along the second direction D2. The drain region is in contact and electrically connected with the conductive pillar 132, and the drain region and the conductive pillar 132 have the same doping ions to further reduce the contact resistance between the drain region and the conductive pillar 132. The capacitor region 12 also includes a plurality of capacitors 14 distributed around the conductive pillar 132. The capacitor 14 includes a lower electrode layer covering the surface of the conductive pillar 132, a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer. The plurality of bit lines 17 are located in the bit line region, each of the bit lines 17 extends along a direction D3 perpendicular to the top surface of the substrate, the plurality of bit lines 17 are arranged at intervals along the first direction D1, and one bit line 17 is electrically connected to the plurality of source regions arranged at intervals along the direction D3 perpendicular to the top surface of the substrate. The plurality of bit line leads 18 are electrically connected to the plurality of bit lines 17, respectively, for leading out the signals of the bit lines 17.

[0079] This specific embodiment also provides a method for forming a semiconductor structure as described in any one of the above items, Figure 5 is a flow chart of the method for forming a semiconductor structure in a specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figure 1-Figure 4 The semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM. Figure 1-Figure 5 As shown, the method for forming the semiconductor structure comprises the following steps:

[0080] Step S51, providing a substrate;

[0081] Step S52, forming a plurality of word lines 15 on the top surface of the substrate, each of the word lines 15 extending in a direction parallel to the top surface of the substrate, and the plurality of word lines 15 are arranged at intervals along a direction D3 perpendicular to the top surface of the substrate, and in the direction D3 perpendicular to the top surface of the substrate, any two adjacent word lines 15 are at least partially staggered.

[0082] In the semiconductor structure and the method for forming the same provided in some embodiments of the present specific implementation, each word line extends in a direction parallel to the top surface of the substrate, and in a direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered, so that the facing area between the two adjacent word lines can be reduced, thereby reducing the capacitive coupling effect between the two adjacent word lines, and improving the electrical performance of the semiconductor structure. In addition, the present disclosure reduces the capacitive coupling effect by reducing the facing area between the two adjacent word lines, and the distance between the two adjacent word lines in the direction perpendicular to the top surface of the substrate does not need to be increased, which helps to control the size of the semiconductor structure.

[0083] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of word lines are located on the top surface of the substrate, each of the word lines extends in a direction parallel to the top surface of the substrate, and the plurality of word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate, and any two adjacent word lines are completely staggered in the direction perpendicular to the top surface of the substrate; Each of the word lines extends along a first direction, and on a plane formed by the first direction and a direction perpendicular to the top surface of the substrate, projections of any two adjacent word lines partially overlap; Each of the word lines extends along a first direction, and each of the word lines includes a first end and a second end opposite to the first end along the first direction, wherein the first direction is a direction parallel to a top surface of the substrate; the semiconductor structure further includes: A plurality of word line leads are located on the top surface of the substrate, each of the word line leads extends in a direction perpendicular to the top surface of the substrate, and the plurality of word line leads are electrically connected to the first end portions of the plurality of word lines, respectively; and a bottom surface of the word line lead connected to a word line is only partially located on the word line.

2. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the top surface of the substrate, the multiple word lines are arranged in sequence, and the projections of any two adjacent word lines of odd bits on the top surface of the substrate overlap, and the projections of any two adjacent word lines of even bits on the top surface of the substrate overlap.

3. The semiconductor structure according to claim 1, characterized in that: Among any two odd-numbered word lines adjacent to each other in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction; Of any two even-numbered word lines adjacent to each other in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction.

4. The semiconductor structure according to claim 3, characterized in that: Of any two adjacent word lines along a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction.

5. The semiconductor structure according to claim 2, characterized in that: Each of the word lines extends along a first direction, and each of the word lines includes a first end and a second end opposite to the first end along the first direction, wherein the first direction is a direction parallel to a top surface of the substrate; the semiconductor structure further includes: A plurality of word line leads are located on the top surface of the substrate, each of the word line leads extends in a direction perpendicular to the top surface of the substrate, the word line leads electrically connected to the word lines of odd-numbered bits are all located at the first end of the word lines of odd-numbered bits, and the word line leads electrically connected to the word lines of even-numbered bits are all located at the second end of the word lines of even-numbered bits.

6. The semiconductor structure according to claim 5, characterized in that: Each of the word lines comprises a first end surface and a second end surface opposite to the first end surface along the first direction; The first end surfaces of all the odd-numbered word lines are flush with each other, and the second end surfaces of all the odd-numbered word lines are flush with each other; The first end surfaces of all the word lines of the even-numbered bits are flush with each other, and the second end surfaces of all the word lines of the even-numbered bits are flush with each other.

7. The semiconductor structure according to claim 5, characterized in that: Among any two odd-numbered word lines adjacent to each other in a direction perpendicular to the top surface of the substrate, the first end of one of the word lines closer to the substrate protrudes beyond the first end of the other word line along the first direction; Of any two adjacent even-numbered word lines in a direction perpendicular to the top surface of the substrate, the second end of one of the word lines closer to the substrate protrudes beyond the second end of the other word line along the first direction.

8. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the top surface of the substrate, the multiple word lines are arranged in sequence, and the projections of any two adjacent word lines at the 3nth position on the top surface of the substrate overlap, the projections of any two adjacent word lines at the 3n+1th position on the top surface of the substrate overlap, and the projections of any two adjacent word lines at the 3n+2th position on the top surface of the substrate overlap, where n is an integer.

9. The semiconductor structure according to claim 1, characterized in that: Also includes: A plurality of semiconductor layers are located on the top surface of the substrate, each of the semiconductor layers comprises a plurality of active pillars arranged at intervals along a first direction, and the plurality of semiconductor layers are arranged at intervals along a direction perpendicular to the top surface of the substrate, each of the active pillars comprises a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction, each of the word lines continuously covers the plurality of channel regions arranged at intervals along the first direction in one of the semiconductor layers, the first direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction is orthogonal to the second direction; A plurality of bit lines are located on the top surface of the substrate, each of the bit lines extends in a direction perpendicular to the top surface of the substrate, the plurality of bit lines are arranged at intervals along the first direction, and one bit line is electrically connected to the plurality of source regions arranged at intervals along a direction perpendicular to the top surface of the substrate.

10. A method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The steps include: providing a substrate; A plurality of word lines are formed on the top surface of the substrate, each of the word lines extends in a direction parallel to the top surface of the substrate, and the plurality of word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, any two adjacent word lines are completely staggered.

Images