Surge protection circuit

Abstract

A surge protection circuit is proposed. The surge protection circuit includes: an input port for receiving an input voltage; and an energy release unit having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device. The surge protection circuit is adapted to close the first switching device to allow current to flow from the input port to ground through the release unit when a positive voltage surge occurs, and to close the second switching device to allow current to flow from ground to the input port through the release unit when a negative voltage surge occurs.

Description

Technical Field

[0001] This disclosure relates to surge protection circuits. In particular, this disclosure relates to a transient voltage suppression unit. background

[0002] Surge protection circuits can be used in a variety of applications, including electronic devices such as mobile phones that may be damaged by transient voltages. Existing surge protection circuits have limited protection levels within a ±100V range. Furthermore, the immunity levels for positive and negative surges cannot be adjusted independently, and circuit design modifications may be required to achieve the desired surge immunity targets. Overview

[0003] The purpose of this disclosure is to address one or more of the limitations mentioned above.

[0004] According to a first aspect of this disclosure, a surge protection circuit is provided, comprising an input port for receiving an input voltage; an energy release unit having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device; the surge protection circuit is adapted to close the first switching device to allow current to flow from the input port through the energy release unit to ground in the event of a positive voltage surge, and to close the second switching device to allow current to flow from ground through the energy release unit to the input port in the event of a negative voltage surge.

[0005] Optionally, a positive voltage surge occurs when the input voltage rises at a rising slew rate greater than a rising slew rate threshold, or when the input voltage rises at a specific rising slew rate to above a positive voltage threshold; and a negative voltage surge occurs when the input voltage decreases at a falling slew rate greater than a falling slew rate threshold, or when the input voltage decreases at a specific falling slew rate to below a negative voltage threshold.

[0006] Optionally, the surge protection circuit includes: a first surge unit adapted to provide a first signal to close a first switching device when a positive voltage surge occurs; and a second surge unit adapted to provide a second signal to close a second switching device when a negative voltage surge occurs.

[0007] Optionally, the first switching device includes a first switch coupled to the second switch.

[0008] Optionally, the first switch and the second switch have a common source node.

[0009] Optionally, the first switching device includes a first Zener diode coupled to a common source node and coupled to the gate terminals of the first and second switches.

[0010] Optionally, the second switching device includes a third switch coupled to the fourth switch.

[0011] Optionally, the fourth switch has a control terminal coupled to ground via a second Zener diode.

[0012] Optionally, the energy release unit includes a fifth switch coupled to the sixth switch.

[0013] Optionally, the fifth and sixth switches are power switches.

[0014] Optionally, the first surge unit includes a first capacitor.

[0015] Optionally, the second surge unit includes a second capacitor.

[0016] Optionally, the rising slew rate threshold and the positive voltage threshold are defined by the size of the first capacitor and the fifth switch.

[0017] Optionally, the slew rate threshold and the negative voltage threshold are defined by the size of the second capacitor and the sixth switch.

[0018] Optionally, the surge protection circuit also includes a bias circuit coupled to the energy release unit, which is adapted to bias the substrate to the input voltage or ground.

[0019] Optionally, the bias circuit includes a seventh switch coupled to an eighth switch; wherein the seventh switch has a control terminal coupled to ground, and wherein the eighth switch has a control terminal coupled to an input port.

[0020] Optionally, the seventh and eighth switches have a common node coupled to the energy release unit.

[0021] According to a second aspect of this disclosure, an apparatus is provided that includes a surge protection circuit according to the first aspect.

[0022] For example, the device could be a user device such as a mobile phone or a connector device such as a USB connector.

[0023] According to a third aspect of this disclosure, a method for surge protection is provided, the method comprising:

[0024] Receives input voltage at the input port;

[0025] An energy release unit is provided, the energy release unit having a first terminal coupled to an input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device;

[0026] In the event of a positive voltage surge, the first switching device is closed to allow current to flow from the input port to ground through the energy release unit; and

[0027] When a negative voltage surge occurs, the second switching device is closed to allow current to flow from ground through the energy release unit to the input port.

[0028] Optionally, a positive voltage surge occurs when the input voltage rises at a rising slew rate greater than a rising slew rate threshold, or when the input voltage rises at a specific rising slew rate to above a positive voltage threshold; and a negative voltage surge occurs when the input voltage decreases at a falling slew rate greater than a falling slew rate threshold, or when the input voltage decreases at a specific falling slew rate to below a negative voltage threshold.

[0029] The options described in the first aspect of this disclosure are also common to the second and third aspects of this disclosure. Brief description of the attached diagram

[0030] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, wherein:

[0031] Figure 1 This is a diagram based on a transient voltage suppression unit (TVS) from the prior art;

[0032] Figure 2 This is a flowchart of a method for surge protection;

[0033] Figure 3 It is a diagram of a surge protection circuit based on this disclosure;

[0034] Figure 4A It is shown Figure 3 A diagram showing the operation of the circuit during a positive surge;

[0035] Figure 4B It is shown Figure 3 A diagram showing the operation of the circuit during a negative surge;

[0036] Figure 5 yes Figure 3 An exemplary embodiment of the surge protection circuit;

[0037] Figure 6A It is shown Figure 5 A diagram showing the operation of the circuit during a positive surge;

[0038] Figure 6B It is shown Figure 5 A diagram showing the operation of the circuit during a negative surge;

[0039] Figure 7 It is a surge protection circuit with substrate bias;

[0040] Figure 8A This is a schematic diagram of a surge generator based on the IEC 61000-4-5 standard;

[0041] Figure 8B This is a schematic diagram of a surge generator model of the circuit disclosed herein;

[0042] Figure 9A It is the open-circuit voltage waveform defined in the IEC 61000-4-5 standard;

[0043] Figure 9B It is the short-circuit current waveform defined in the IEC 61000-4-5 standard;

[0044] Figure 10A From Figure 8B The simulation of the open-circuit voltage waveform obtained from the model;

[0045] Figure 10B yes Figure 8B Simulation of the short-circuit current waveform of the model;

[0046] Figure 11 It is a simulated graph of surge current I_VBUS, voltage VBUS, gate voltage gate_tvs of surge cell, and substrate voltage Vsub obtained for a series of positive surges;

[0047] Figure 12 It is a simulated graph of surge current I_VBUS, voltage VBUS, gate voltage gate_tvs of surge cell, and substrate voltage Vsub obtained for a series of negative surges.

[0048] Figure 13 It is a simulation of the gate voltage gate_tvs and surge current I_VBUS of the surge cell as the VBUS DC value changes;

[0049] Figure 14 This is a schematic diagram of a USB connector equipped with surge protection circuitry according to this disclosure. Detailed description

[0050] Figure 1 A transient voltage suppression unit (TVS) as described in Dialog Semiconductor's datasheet SLG59H1313C is shown. Unit 100 has a power transistor Mx disposed between an input port for receiving voltage VBUS and a ground port. The power transistor Mx has a drain terminal connected to the input port, a source terminal connected to the ground port, and a gate terminal connected to the ground port via a Zener diode Zx. A resistor Rx and a capacitor Cx are configured to be connected in parallel with the Zener diode.

[0051] The resistor Rx and capacitor Cx can be adjusted by changing the layout of the metal layers to achieve a surge immunity level of ±100V, with an absolute maximum rating (AMR) of -0.3V to 28V. Changing the layout of the metal layers is a time-consuming process.

[0052] For positive surges, a power transistor Mx is used to discharge the surge. For negative surges, Mx and a parasitic diode Dp are used to discharge the surge. Positive and negative protection capabilities have different coupling behaviors and are affected by simultaneously changing Rx, Cx, and Mx.

[0053] Circuit 100 cannot independently adjust the positive and negative surge immunity levels and has surge immunity limited to ±100V. Higher protection levels cannot be achieved simply by adjusting the metal layers; a new design is required to achieve the surge immunity target. Due to the body diode of the power switch Mx, the circuit will also suffer significant leakage if VBUS is powered by a negative voltage.

[0054] Figure 2 This is a flowchart of a method for surge protection.

[0055] At step 210, the input voltage is received at the input port.

[0056] At step 220, an energy release unit is provided. The energy release unit has a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device.

[0057] At step 230, when a positive surge occurs, the first switching device closes to allow current to flow from the input port to ground through the energy release unit.

[0058] For example, a positive voltage surge or positive surge condition may occur when the input voltage rises at a rate of change greater than the rise slew rate threshold, or when the input voltage rises above a positive voltage threshold at a specific rise slew rate.

[0059] At step 240, when a negative surge occurs, the second switching device closes to allow current to flow from ground through the release unit to the input port.

[0060] For example, a negative voltage surge or negative surge condition may occur when the input voltage decreases at a rate of change (absolute value) greater than the slew rate threshold (slew rate), or when the input voltage decreases to below the negative voltage threshold at a specific slew rate.

[0061] Figure 3 This is a diagram of a surge protection circuit based on this disclosure.

[0062] The surge protection circuit 300 has an input port 305 for receiving the input voltage VBUS, a ground port, two switching devices S1 and S2, two surge units T1 310 and T2 320, and an energy release unit E1 330.

[0063] The first surge unit T1 310, also referred to as a trigger unit for positive surges, is adapted to provide a first signal (net1) to close the first switching device S1 when a positive voltage surge occurs. As described above, a positive voltage surge may occur when the input voltage rises at a rate greater than a rise rate threshold. For example, when the input voltage rises at a rate greater than 50V / μs. Alternatively, a positive voltage surge may occur when the input voltage rises above a positive voltage threshold at a specific rise rate. For example, when the input voltage rises above 20V at a rise rate of 10V / μs.

[0064] The second surge unit T2 320, also known as the trigger unit for negative surges, is adapted to provide a second signal (net2) to close the second switching device S2 when a negative voltage surge occurs. As described above, a negative voltage surge may occur when the input voltage decreases at a rate greater than a falling rate threshold, or when the input voltage decreases to below a negative voltage threshold at a specific falling rate.

[0065] The first surge unit T1 has a first terminal coupled to the input port 305 and a second terminal for providing a signal net1 to control the first switching device S1. The second surge unit T2 has a first terminal coupled to the input port 305 and a second terminal for providing a signal net2 to control the second switching device S2. The energy release unit E1 has a first terminal coupled to the input port 305, a second terminal coupled to ground, and a third (control) terminal coupled to S1 and S2 at node N1.

[0066] When a positive surge occurs, circuit 300 closes the first switching device S1 so that current can flow from input port 305 to ground through energy release unit E1 330.

[0067] When a negative surge occurs, circuit 300 closes the second switching device S2 so that current can flow from ground through energy release unit 330 to input port 305.

[0068] Figure 4A The operation of circuit 300 during a positive surge is illustrated. Signal net1, provided by the first unit T1 310, goes high, and switching device S1 is turned on (closed). Signal net3 at node N1 goes high, and energy release unit E1 330 is turned on to release surge energy from VBUS to ground.

[0069] Figure 4BThe operation of circuit 300 during a negative surge is illustrated. Signal net2, provided by the second unit T2 320, goes low, and switching device S2 is turned on (closed). Signal net3 at node N1 goes low (to ground), and energy release unit E1330 is turned on to release surge energy from ground to VBUS.

[0070] Therefore, circuit 300 can independently achieve adjustable positive and negative surge immunity. The positive and negative surge immunity levels can be adjusted by changing specific parameters of the circuit. Additionally, the energy release unit E1 can be adapted to block DC current when VBUS is positive or negative. This can be achieved using a substrate bias circuit such that when VBUS is positive, signal net3 drops to ground and no DC current flows through E1, while when VBUS is negative, signal net3 drops to VBUS or follows VBUS and no DC current flows through E1.

[0071] Figure 5 yes Figure 3 An exemplary embodiment of the surge protection circuit is provided. In this example, the circuit 500 has a first unit 510 formed by capacitor C1, a second unit 520 formed by capacitor C2, and an energy release unit 530 formed by two transistors M5 and M6. The circuit also includes a first switching device formed by transistors M1 and M2 coupled to Zener diode Z1, and a second switching device formed by transistor M3 and M4 coupled to Zener diode Z2.

[0072] Transistor M1 has a drain terminal coupled to the input port and a source terminal coupled to the source terminal of M2 at a common source node. The gate terminals of M1 and M2 are coupled at node N2. Zener diode Z1 is disposed between the source terminal and N2.

[0073] Transistor M3 has a source terminal coupled to node N1 and a drain terminal coupled to the drain terminal of M4. The gate terminal of M3 is coupled to node N1, and the gate terminal of M4 is coupled to ground via Zener diode Z2.

[0074] Transistor M5 has a drain terminal coupled to the input port and a source terminal coupled to the source terminal of M6. The gate terminals of M5 and M6 are coupled at node N1.

[0075] Additionally, three resistors R1, R2, and R3 are provided. Resistor R1 couples C1 to ground, resistor R2 couples M2 to ground, and resistor R3 couples C2 to ground. Resistors R1, R2, and R3 provide a pull-down path to disable the surge unit, so that the surge unit is initially off when there is no surge. Zener diodes Z1 and Z2 are provided to protect the gate-source oxide of switches M1, M2, and M4 by clamping the gate voltage to the source voltage; for example, VGS < 6V.

[0076] Switches M1 and M5 can be, for example, NMOS high-voltage transistors with a rated voltage of 24V. Alternatively, switches M1 and M5 can be, for example, NMOS low-voltage transistors with a rated voltage of 5V. Switches M2 and M6 can be, for example, NMOS low-voltage transistors with a rated voltage of 5V. Switches M3 and M4 can be, for example, PMOS low-voltage transistors with a rated voltage of 5V.

[0077] Figure 6A The operation of circuit 500 during a positive surge is illustrated. The rise rate threshold and positive voltage threshold are defined by the first capacitor C1.

[0078] VBUS voltage > GND voltage (see point (1)). The gate voltage gate_m2 at node N2 becomes high through C1. This voltage is clamped by the breakdown Zener diode Z1.

[0079] The voltage at the common source node of M1 / M2 is defined by gate_m2 and Z1, such that the gate-to-source voltages of M1 and M2 are equal to the voltage across the breakdown diode Z1: Vgs(M1) = Vgs(M2) = Vbd(Z1). In the exemplary numerical example, the breakdown voltage Vbd(Z1) is ~5.8V. The gate voltage gate_m4 at node N3 is increased by C2. This voltage is clamped by the forward-biased Zener diode Z2 (see point (2)).

[0080] When M3 is off, such as Vgs(M3) = 0V, transistors M1 and M2 are on. When Vgs(M4) is too low to turn on M4, switch M4 remains off (open circuit). In the numerical example, Vgs(M4) = -Vf(Z2) (~-0.7V), where Vf is the forward diode voltage (see point (3)).

[0081] The gate voltage gate_tvs rises at node N1 (see point (4)). Transistors M5 and M6 are turned on to release surge energy from VBUS to ground (see point (5)). The level of positive surge protection can be adjusted by selecting the size and rated voltage of switch M5. The larger the size / voltage rating of M5, the higher the level of positive surge protection.

[0082] The sensitivity of the positive surge unit T1 510 can be adjusted by selecting an appropriate capacitance / size for capacitor C1. A larger capacitance / size results in greater sensitivity. For a relatively small C1 (small capacitance), the positive surge unit requires a relatively large rate of change of the input voltage (slew rate) to conduct. By increasing the capacitance of C1, the positive surge unit conducts with a relatively small rate of change of the input voltage.

[0083] Figure 6BShows the operation of circuit 500 during a negative surge. The falling rate threshold and the negative voltage threshold are defined by the second capacitor C2.

[0084] The VBUS voltage < GND voltage (see point (1)). The gate voltage gate_m2 at node N2 goes negative through C1. This voltage is clamped by the forward-biased Zener diode Z1. The gate voltage gate_m4 at node N3 goes low through C2. This voltage is clamped by the breakdown Zener diode Z2 (see point (2)).

[0085] The voltage at the common source node of M1 / M2 is defined by gate_m2 and Z1 such that the gate-to-source voltages of M1 and M2 are equal to the voltage across the forward-biased diode Z1: Vgs(M1) = Vgs(M2) = -Vf(Z1). In an exemplary numerical example, -Vf(Z1) ~ -0.7V. Transistors M1 and M2 are turned off (open circuit). The gate-to-source voltage of M4 Vgs(M4) increases above the transistor threshold, e.g., > 5V, via coupling through C2 to fully turn on M4 and force the drain terminal of M4 to ground (see point (3)).

[0086] The gate voltage gate_tvs at node N1 is between ground and -VD(M3) ( ~ -0.7V) through the parasitic diode of M3, however the resistor R2 holds gate_tvs at ground (see point (4)).

[0087] Transistors M5 and M6 are turned on to release the surge energy from GND to VBUS (see point (5)).

[0088] Zener diodes Z1 and Z2 can be selected to absorb high overvoltages in a short time, so as not to apply excessive voltages to other semiconductor devices. For example, Zener diode Z1 protects the gate-source terminals of transistors M1 and M2 from excessive voltages. Zener diodes Z1 and Z2 also protect the power supply or signal lines from transient surge events. <​​​​​​​​It is a surge protection circuit with substrate biasing function. Circuit 700 is similar to... Figure 5 The protection circuit 500, however, in this case, adds a substrate bias circuit 710 to allow operation with VBUS AMR (absolute maximum rating) between approximately -6V (DC) and approximately +28V (DC) without triggering surge protection, thus preventing large currents from flowing through switches M5 and M6. In this example, the circuit substrate can be biased to the lower of VBUS and ground.

[0092] The substrate bias circuit 710 includes two transistors M13 and M14, four resistors R13, R14, R15, and R16, and two Zener diodes Z13 and Z14. Resistors R15 and R16 provide current limiting protection to prevent large currents from being injected into the substrate bias circuit 710.

[0093] Transistors M13 and M14 are coupled such that the source terminal of M13 is connected to the source terminal of M14 at node N4. The drain terminal of M13 is coupled to the drain terminal of M5 via resistor R16, and the drain terminal of M14 is coupled to ground. The gate terminal of M13 is coupled to ground via resistor R13 and to node N4 via resistor Z13. The gate terminal of M14 is coupled to the drain terminal of M5 via resistor R14 and to node N4 via resistor Z14. Node N4 is coupled to the common source node N5 of transistors M5 and M6 via resistor R15. A substrate voltage Vsub is applied at node N5.

[0094] When VBUS drops below 0V, the substrate bias circuit 710 allows the substrate voltage Vsub to follow VBUS. For example, if VBUS = -6V (DC) and GND = 0V, M13 is turned on, and Vsub becomes -6V (in this example, M13 is implemented as an NMOS transistor). The voltage gate_m13 is held at GND via R13. When VBUS becomes DC negative, M13 is turned on, and Vsub can follow VBUS. Node N2 is connected to ground via R1, and the voltage at node N2 V(N2) = 0V. The breakdown voltage of Z1 Vbd(Z1) can be approximately 5.8V, and when VBUS = -6V, switches M1 and M2 are turned on, Vgs(M1) = Vgs(M2) = Vbd(Z1). Then, gate_tvs becomes -6V. Therefore, Vgs(M6) = 0V, and M6 is turned off. When VBUS becomes DC negative, switch M5 is also turned off. This prevents high leakage current through M5 and M6 when VBUS(DC) is negative.

[0095] Therefore, the chip substrate (same as the circuit substrate) can be biased to the lower of VBUS and ground. This ensures that the substrate voltage of the chip / circuit is at the most negative potential and can eliminate or greatly reduce parasitic device current paths that can leak when VBUS becomes negative and potentially damage the chip. For example, if VBUS = -6V and Vsub = 0V, leakage current may flow from the substrate through the M5 body diode to VBUS.

[0096] When VBUS becomes positive (e.g., >1V), M14 is turned on when R14 pulls gate_m14 high and Vsub is biased to GND. The gate-to-source voltage Vgs(M6) of M6 is 0V, and M6 is turned off. The gate_tvs signal is biased to 0V by R2, and M5 is turned off, so Vgs(M5) = 0. This design allows the chip to operate normally when VBUS becomes positive, with VBUS AMR ranging from -6V (DC) to +28V (DC).

[0097] The International Electrotechnical Commission's IEC 61000-4-5 is an international standard for surge immunity. According to this standard, generators can be used to simulate surges. An overview of this standard can be found in STMicroelectronics' "IEC 61000-4-5 standard overview" (AN4275 datasheet, application notes, August 2013).

[0098] Figure 8A This is a diagram of a surge generator based on the IEC 61000-4-5 standard. The surge definition in IEC 61000-4-5 meets the specification of a 1.2μs / 50μs surge duration. Output impedance R... out The output impedance of the generator is 2Ω, and the ratio of the peak voltage of the open circuit to the peak current of the short circuit is 2Ω.

[0099] Douglas E. Powell and Bryce Hesterman reported the equations for open-circuit surge voltage and short-circuit surge current in their “Introduction to Voltage Surge Immunity Testing” at the IEEE Power Electronics Society Denver Chapter Meeting in September 2007.

[0100] For open-circuit waveforms:

[0101] τ1 = 0.4074us

[0102] τ2 = 68.22us

[0103] A = 1.037

[0104] V p Peak voltage

[0105] For short-circuit waveforms:

[0106] τ = 3.977us

[0107] k = 2.93

[0108] A = 0.1405

[0109] I p Peak current

[0110] The parameters of the surge generator model can be derived from the above equations (1) and (2).

[0111] Figure 8B This is a schematic diagram of a surge generator model with derived parameters.

[0112] Figure 9A and Figure 9B The open-circuit voltage waveform and short-circuit current waveform are shown respectively as defined in the IEC 61000-4-5 standard.

[0113] Figure 10A and Figure 10B They are Figure 8B The simulation results of the open-circuit voltage waveform and short-circuit current waveform of the model are provided. The surge generator model provides appropriate voltage and current waveforms to simulate the IEC 61000-4-5 surge test.

[0114] Figure 11 Simulations of surge current I_VBUS, voltage VBUS, gate voltage gate_tvs of the surge cell, and substrate voltage Vsub are shown for a series of positive surges. The simulations were obtained by positive surge tests with and without bias VBUS, and for voltages of 200V, 150V, 100V, and 50V in each case.

[0115] Figure 12 Simulations of surge current I_VBUS, voltage VBUS, gate voltage gate_tvs of the surge cell, and substrate voltage Vsub are shown for a series of negative surges. The simulations were obtained by negative surge tests with and without bias VBUS, and for voltages of -200V, -150V, -100V, and -50V in each case.

[0116] Figure 11 and Figure 12The simulations shown demonstrate that the circuitry of this disclosure performs well under ±200V surge testing. During ±200V surge testing, surge energy can be released from VBUS to ground.

[0117] Figure 13 This is a simulation of the gate voltage gate_tvs and surge current I_VBUS of the surge cell, which vary with the DC value of VBUS. Trace 1310 shows Vgs(M5) = gate_tvs – VBUS, while trace 1320 shows Vgs(M6) = gate_tvs – ground. Trace 1330 shows the surge current through M5 and M6.

[0118] When VBUS is below zero, Vgs(M5) = 0, and M5 is off. Similarly, when VBUS is above zero, Vgs(M6) = 0, and M6 is off. Therefore, at least one of M5 and M6 is off.

[0119] The VBUS AMR specification ranges from -6V to +28V. Most VBUS DC simulations show that the circuit disclosed herein operates well with minimal leakage when VBUS ranges from -6V (DC) to +28V (DC). Therefore, a surge immunity level of ±200V can be achieved with a VBUS AMR range of -6V to 28V.

[0120] As this public reference Figures 2 to 13 The surge circuit described herein can be used in many applications to prevent damage caused by voltage surges. For example, the circuit disclosed herein can be used as part of a connector, such as a Universal Serial Bus (USB) connector.

[0121] Figure 14 This is a schematic diagram of a USB connector equipped with surge protection circuitry according to this disclosure.

[0122] Those skilled in the art will understand that variations in the disclosed arrangement are possible without departing from this disclosure. Therefore, the above description of specific embodiments has been made by way of example only and not for limiting purposes. Those skilled in the art will appreciate that minor modifications can be made to the described operation without significant alterations.

Claims

1. A surge protection circuit, comprising: The input port is used to receive the input voltage. An energy release unit has a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device; The surge protection circuit is adapted to close the first switching device when a positive voltage surge occurs so that current can flow from the input port through the energy release unit to ground, and to close the second switching device when a negative voltage surge occurs so that current can flow from ground through the energy release unit to the input port; The first switching device includes a first switch coupled to the second switch, the first switch and the second switch having a common source node and a common gate node, and the body diodes of the first switch and the second switch being connected back to back.

2. The surge protection circuit according to claim 1, wherein, A positive voltage surge occurs when the input voltage rises at a rate greater than the rising slew rate threshold, or when the input voltage rises at a specific rate to above the positive voltage threshold; and a negative voltage surge occurs when the input voltage decreases at a rate greater than the falling slew rate threshold, or when the input voltage decreases at a specific rate to below the negative voltage threshold.

3. The surge protection circuit according to claim 2, comprising: A first surge unit, the first surge unit being adapted to provide a first signal to close the first switching device when the positive voltage surge occurs; as well as A second surge unit is adapted to provide a second signal to close the second switching device when the negative voltage surge occurs.

4. The surge protection circuit according to claim 1, wherein, The first switching device includes a first Zener diode coupled to the common source node and coupled to the gate terminals of the first switch and the second switch.

5. The surge protection circuit according to claim 1, wherein, The second switching device includes a third switch coupled to the fourth switch.

6. The surge protection circuit according to claim 5, wherein, The fourth switch has a control terminal coupled to ground via a second Zener diode.

7. The surge protection circuit according to claim 3, wherein, The energy release unit includes a fifth switch coupled to a sixth switch.

8. The surge protection circuit according to claim 7, wherein, The fifth and sixth switches are power switches.

9. The surge protection circuit according to claim 7, wherein, The first surge unit includes a first capacitor.

10. The surge protection circuit according to claim 7, wherein, The second surge unit includes a second capacitor.

11. The surge protection circuit according to claim 9, wherein, The rising slew rate threshold and the positive voltage threshold are defined by the size of the fifth switch and the first capacitor.

12. The surge protection circuit according to claim 10; wherein, The slew rate threshold and the negative voltage threshold are defined by the size of the sixth switch and the second capacitor.

13. The surge protection circuit of claim 1 further includes a bias circuit coupled to the energy release unit, the bias circuit being adapted to bias the substrate to the input voltage or ground.

14. The surge protection circuit according to claim 13, wherein, The bias circuit includes a seventh switch coupled to an eighth switch; wherein the seventh switch has a control terminal coupled to ground, and wherein the eighth switch has a control terminal coupled to the input port.

15. The surge protection circuit according to claim 14, wherein, The seventh switch and the eighth switch have a common node coupled to the energy release unit.

16. An apparatus comprising the surge protection circuit according to claim 1.

17. A method for surge protection, the method comprising: Receives input voltage at the input port; An energy release unit is provided, the energy release unit having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switching device and coupled to ground via a second switching device; The first switching device includes a first switch coupled to the second switch, the first switch and the second switch have a common source node and a common gate node, and the body diodes of the first switch and the second switch are connected back to back. In the event of a positive voltage surge, the first switching device is closed to allow current to flow from the input port to ground through the energy release unit; and In the event of a negative voltage surge, the second switching device is closed to allow current to flow from ground through the energy release unit to the input port.

18. The method according to claim 17, wherein, A positive voltage surge occurs when the input voltage rises at a rate greater than the rising slew rate threshold, or when the input voltage rises at a specific rate to above the positive voltage threshold; and a negative voltage surge occurs when the input voltage decreases at a rate greater than the falling slew rate threshold, or when the input voltage decreases at a specific rate to below the negative voltage threshold.

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