A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module and a reset module. The driving module is used to selectively provide driving current to the light-emitting element. The reset module includes a reset transistor. The first terminal of the reset transistor receives a reset signal, and the second terminal of the reset transistor is electrically connected to the driving module and / or the light-emitting element. The operation of the pixel circuit includes a buffering stage and a reset stage. In the reset stage, the reset transistor is turned on; in the buffering stage, the reset transistor is turned off. The voltage of the reset signal received by the reset transistor in the reset stage is V1, and the voltage of the reset signal received by the reset transistor in the buffering stage is V2, where V1 ≠ V2. Embodiments of this invention can reduce the leakage current of the reset transistor and improve the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Active-matrix organic light emitting diode (AMOLED) display panels are widely used in the display field because they are superior to liquid crystal display panels in terms of color saturation, power consumption, and bending performance.

[0003] During the display process of an AMOLED display panel, the pixel circuit drives the light-emitting devices to emit light. The pixel circuit includes a reset transistor, which can write a reset signal into the pixel circuit to clear the electrical signals remaining in the pixel circuit from the previous driving cycle.

[0004] However, the reset transistor has leakage current, which causes abnormal voltage in the pixel circuit and affects the display effect. Summary of the Invention

[0005] The present invention provides a display panel and a display device to reduce the leakage current of the reset transistor and improve the display effect.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: pixel circuitry and light-emitting elements;

[0007] The pixel circuit includes a driving module and a reset module;

[0008] The driving module is used to selectively provide driving current to the light-emitting element;

[0009] The reset module includes a reset transistor; the first terminal of the reset transistor receives a reset signal, and the second terminal of the reset transistor is electrically connected to the drive module and / or the light-emitting element.

[0010] The operation of the pixel circuit includes a buffering phase and a reset phase; in the reset phase, the reset transistor is turned on; in the buffering phase, the reset transistor is turned off.

[0011] In this process, the voltage of the reset signal received by the reset transistor during the reset phase is V1, and the voltage of the reset signal received by the reset transistor during the buffer phase is V2, where V1 ≠ V2.

[0012] According to another aspect of the present invention, a display device is provided, the display device including the above-described display panel.

[0013] The technical solution of this invention, by setting a reset stage and a buffer stage during the operation of the pixel circuit, and by setting the reset signal V1 received by the reset transistor in the reset stage to be different from the voltage V2 of the reset signal received by the reset transistor in the buffer stage, can reduce the voltage difference between the first and second terminals of the reset transistor in the buffer stage, reduce the source-drain voltage of the reset transistor, alleviate the electric field stress of the reset transistor, thereby improving the performance and service life of the reset transistor and preventing the reset transistor from failing under large bias stress for a long time. At the same time, it can also reduce the offset of the threshold voltage, reduce the leakage current, and thus improve the stability of the driving module and / or the light-emitting element, so that the light-emitting element can emit light accurately and improve the display effect of the display panel.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a top view of a display panel structure in the prior art;

[0017] Figure 2 This is a schematic diagram of the circuit structure of a pixel circuit in the prior art;

[0018] Figure 3 This is a schematic diagram of the driving timing of a pixel circuit in the prior art;

[0019] Figure 4 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0020] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0022] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0023] Figure 8This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0024] Figure 9 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0025] Figure 10 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Figure 1 This is a top view diagram of a display panel in the prior art. Figure 2 This is a schematic diagram of the circuit structure of a pixel circuit in the prior art. Figure 3 This is a schematic diagram of the driving timing of a pixel circuit in the prior art. (Reference) Figure 1 , Figure 2 and Figure 3 To simplify the accompanying drawings and facilitate explanation, Figure 1The diagram only shows a portion of the display panel's structure. The display panel includes a display area AA, which comprises multiple pixel circuits 01, multiple scan lines SCANL, multiple data lines DL, multiple light emission control lines EML, and at least one first reset line VREFL1 and at least one second reset line VREFL2. The multiple pixel circuits 01 are arranged in an array along a first direction X and a second direction Y. The multiple pixel circuits 01 are arranged in rows along the first direction X and columns along the second direction Y. Pixel circuits 01 located in the same row are electrically connected to the same scan line SCANL and the same light emission control line EML. The scan line SCANL connected to the pixel circuits 01 in the same row is also multiplexed as the reset control line for the pixel circuits 01 in the next row. Pixel circuits 01 located in the same column are electrically connected to the same data line DL. All pixel circuits 01 can be electrically connected to the same first reset line VREFL1 and the same second reset line VREFL2.

[0030] The pixel circuit 01 in the prior art includes a driving transistor M3, a first light-emitting control transistor M1, a data writing transistor M2, a threshold compensation transistor M5, a second light-emitting control transistor M6, a first reset transistor M4, a second reset transistor M7, and a storage capacitor C1. Both the second light-emitting control transistor M6 and the second reset transistor M7 are electrically connected to the light-emitting element LED. The light-emitting element OLED includes, but is not limited to, Micro LED, Mini LED, and other light-emitting devices. The first terminal of the first reset transistor M4 receives the first reset signal Vref1 from the first reset line VREFL1, and the second terminal of the first reset transistor M4 is electrically connected to the gate of the driving transistor M3, used to clear the residual data signal from the gate of the driving transistor M3 in the previous driving cycle. The first terminal of the second reset transistor M7 receives the second reset signal Vref2 from the second reset line VREFL2, and the second terminal of the second reset transistor M7 is electrically connected to the anode of the light-emitting element LED, used to clear the residual electrical signal from the anode of the light-emitting element LED in the previous driving cycle. The cathode of the light-emitting element LED receives the negative power supply signal PVEE.

[0031] One driving cycle of pixel circuit 01 includes a reset phase t1, a data writing phase t2, and a light-emitting phase t3 executed sequentially. Generally, one driving cycle of pixel circuit 01 is the time of one display frame. In the reset phase t1, the (n-1)th scan signal Scan(n-1) is low, and the first reset transistor M4 and the second reset transistor M7 are turned on. The first reset transistor M4 can transmit a first reset signal Vref1 to the gate of driving transistor M3, clearing the data signal Vdata of the gate of driving transistor M3 in the previous driving cycle, thus turning on driving transistor M3. The second reset transistor M7 can transmit a second reset signal Vref2 to the anode of the light-emitting element LED, clearing the electrical signal of the anode of the light-emitting element LED in the previous driving cycle, thus turning off the light-emitting element LED. During the data writing phase t2, the (n-1)th scan signal Scan(n-1) is high and the nth scan signal Scan(n) is low. The first reset transistor M4 and the second reset transistor M7 are turned off, and the data writing transistor M2 and the threshold compensation transistor M5 are turned on. By turning on the data writing transistor M2, the driving transistor M3 and the threshold compensation transistor M5, the data signal Vdata can be transmitted to the gate of the driving transistor M3, pulling the gate of the driving transistor M3 high until the driving transistor M3 is turned off. The data signal Vdata is written to the gate of the driving transistor M3, and the storage capacitor C1 can store the gate voltage of the driving transistor M3. During the light-emitting stage t3, both the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) are at high level. The first reset transistor M4, the second reset transistor M7, the data writing transistor M2, and the threshold compensation transistor M5 are all turned off. The light-emitting control signal Em(n) is at low level. Drive current flows through the first light-emitting control transistor M1, the driving transistor M3, and the second light-emitting control transistor M6. The anode voltage of the light-emitting element LED increases, and the light-emitting element LED emits light.

[0032] As described in the background section, the first reset transistor M4 and the second reset transistor M7 exhibit leakage current, which may lead to instability in the gate voltage of the driving transistor M3 and the anode voltage of the LED. For the first reset transistor M4, during the data writing phase t2, its source-drain voltage increases as the gate of the driving transistor M3 is pulled high. During the light-emitting phase t3, the source-drain voltage of the first reset transistor M4 reaches its maximum. When the source-drain voltage is too high, the electric field stress is large. The first reset transistor M4 may fail under prolonged exposure to this large bias electric field stress, resulting in a threshold voltage shift and significant leakage current, affecting the gate stability of the driving transistor M3 and causing abnormal LED emission. For the second reset transistor M7, during the light-emitting phase t3, the anode voltage of the LED is pulled high by the positive power supply signal PVDD of the first electrode of the first light-emitting control signal M1, leading to an excessively high source-drain voltage. The second reset transistor M7 is also prone to failure under prolonged exposure to large bias stress, affecting the stability of the LED and causing abnormal LED emission.

[0033] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a pixel circuit including a driving module and a reset module; the driving module is used to selectively provide driving current to a light-emitting element; the reset module includes a reset transistor; the first terminal of the reset transistor receives a reset signal, and the second terminal of the reset transistor is electrically connected to the driving module and / or the light-emitting element; the operation of the pixel circuit 10 includes a buffering stage and a reset stage; in the reset stage, the reset transistor is turned on; in the buffering stage, the reset transistor is turned off; wherein, the voltage of the reset signal received by the reset transistor in the reset stage is V1, and the voltage of the reset signal received by the reset transistor in the buffering stage is V2, V1≠V2.

[0034] By adopting the above technical solution, the voltage difference between the first and second terminals of the reset transistor can be reduced during the buffering stage, the source-drain voltage of the reset transistor can be reduced, the electric field stress of the reset transistor can be relieved, thereby improving the performance and service life of the reset transistor and preventing the reset transistor from failing under large bias stress for a long time. At the same time, the threshold voltage offset can also be reduced, the leakage current can be reduced, thereby improving the stability of the driving module and / or the light-emitting element, enabling the light-emitting element to emit light accurately and improving the display effect of the display panel.

[0035] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0036] The similarities to existing technologies will not be repeated in the embodiments of the present invention. In the embodiments of the present invention, the operation of the pixel circuit includes a buffering stage and a reset stage. In the reset stage, the reset transistor is turned on, and the reset signal is written to the driving module and / or the light-emitting element; in the buffering stage, the reset transistor is turned off, and the reset signal no longer needs to be fixed to a specific voltage, providing ample design space for the reset signal.

[0037] Specifically, during the reset phase, the reset transistor is turned on, the reset signal voltage is V1, and the voltage at the second terminal of the reset transistor is also V1. This controls the drive module to enter its initial state, clearing the state of the drive module from the previous drive cycle. The initial state of the drive module is generally either completely off or completely on. And / or, the reset signal voltage is V1, and the voltage at the second terminal of the reset transistor is also V1, controlling the light-emitting element to enter its initial state, clearing the state of the light-emitting element from the previous drive cycle. To avoid abnormal display, the initial state of the light-emitting element is generally non-illuminating. Outside the reset phase, the reset transistor is turned off. The drive module needs to receive data signals and operates normally. At this time, the drive module is generally between a completely off state and a completely on state, causing a significant change in the voltage at the second terminal of the reset transistor, which is no longer V1. And / or, outside the reset phase, the reset transistor is turned off. The light-emitting element needs to receive power signals and illuminates according to the data signals, causing a significant change in the voltage at the second terminal of the reset transistor, which is no longer V1. By setting a buffer stage outside the reset stage and changing the voltage of the reset signal during the buffer stage, the voltage V1 of the reset signal received by the first terminal of the reset transistor during the reset stage is not equal to the voltage V2 of the reset signal received by the first terminal of the reset transistor during the buffer stage. This can reduce the voltage difference between the first and second terminals of the reset transistor during the buffer stage, that is, reduce the source-drain voltage of the reset transistor during the buffer stage. This can alleviate the electric field stress of the reset transistor, reduce the accumulation of charge carriers in the channel, prevent the reset transistor from failing under large bias stress for a long time, and thus reduce the leakage current of the reset transistor and improve the stability of the pixel circuit.

[0038] The display panel provided in this embodiment of the invention can be as follows: Figure 1 As shown, the pixel circuit structure provided in this embodiment of the invention can be as follows: Figure 2 As shown, but not limited to, the display panel and pixel circuit provided in other embodiments of the present invention may have other structures. In one embodiment, the driving module includes a driving transistor M3, the reset module includes a first reset transistor M4 and / or a second reset transistor M7, and the reset signal includes a first reset signal Vref1 and / or a second reset signal Vref2.

[0039] Figure 2 In the pixel circuit 01, all transistors are P-type transistors. In other alternative embodiments, all transistors in the pixel circuit may be N-type transistors, or a combination of P-type and N-type transistors. Different enable levels can be provided for different types of transistors; the enable level is the level that enables the transistor to conduct. For example, for P-type transistors, the enable level is low, and for N-type transistors, the enable level is high.

[0040] For example, Figure 4 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. (Reference) Figure 4 Taking the reset transistor, including the first reset transistor M4, and all transistors being P-type transistors, as an example. During the reset phase t1, the (n-1)th scan signal Scan(n-1) is at a low level, and the first reset transistor M4 is turned on. At this time, the first reset signal Vref1, which is a relatively small voltage V1, is transmitted from the first terminal of the first reset transistor M4 to the gate of the driving transistor M3 to ensure that the driving transistor M3 is in an absolutely on state. At the same time, the data signal Vdata of the gate of the driving transistor M3 in the previous driving cycle is cleared.

[0041] During the data writing phase t2, the (n-1)th scan signal Scan(n-1) is high and the nth scan signal Scan(n) is low. The first reset transistor M4 is turned off, and the data writing transistor M2 and the threshold compensation transistor M5 are turned on. The data signal Vdata is written and pulls the gate of the driving transistor M3 high. Through threshold compensation, the voltage of the gate of the driving transistor M3 is Vdata-|Vth|, Vdata-|Vth|>>V1. The source-drain voltage of the first reset transistor M4 is too large, which makes the electric field stress of the first reset transistor M4 large. The first reset transistor M4 is prone to failure under the action of large bias stress for a long time, and the threshold voltage will shift significantly. The first reset transistor M4 has obvious leakage current.

[0042] During the buffering phase t01, increasing the voltage of the first reset signal Vref1 from V1 to V2 can reduce the source-drain voltage of the first reset transistor M4, alleviate the electric field stress of the first reset transistor M4, and prevent the first reset transistor M4 from being under bias stress for a long time. In this way, the offset of the threshold voltage can be reduced, thereby reducing the leakage current of the first reset transistor M4 and improving the stability of the gate voltage of the driving transistor M3.

[0043] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 5Taking a reset transistor, including a second reset transistor M7, and both transistors being P-type transistors, as an example. During the reset phase t1, the (n-1)th scan signal Scan(n-1) is at a low level, and the second reset transistor M7 is turned on. At this time, the second reset signal Vref2, which is a relatively small voltage V1, is transmitted from the first terminal of the second reset transistor M7 to the anode of the light-emitting element LED, so that the light-emitting element LED is in a non-light-emitting state. At the same time, the electrical signal of the anode of the light-emitting element LED in the previous driving cycle is cleared.

[0044] During the light-emitting stage t3, both the (n-1)th scan signal Scan(n-1) and the nth scan signal Scan(n) are at high level, while the light-emitting control signal Em(n) is at low level. The second reset transistor M7, the data writing transistor M2, and the threshold compensation transistor M5 are all turned off, while the first light-emitting control signal M1, the second light-emitting control signal M6, and the driving transistor M3 are all turned on. The voltage of the anode of the light-emitting element LED is pulled up to PVDD by the voltage of the positive power supply signal PVDD of the first electrode of the first light-emitting control signal M1. PVDD >> V1. The source-drain voltage of the second reset transistor M7 is too large, resulting in a large electric field stress on the second reset transistor M7. The second reset transistor M7 is prone to failure under a large bias stress for a long time, and the threshold voltage will deviate significantly. The second reset transistor M7 has obvious leakage current. During the buffer phase t01, increasing the voltage of the second reset signal Vref2 from V1 to V2 can reduce the source-drain voltage of the second reset transistor M7, alleviate the electric field stress accumulated on the second reset transistor M7 in the previous driving cycle, and prevent the second reset transistor M7 from being under bias stress for a long time. In this way, the threshold voltage offset can be reduced, thereby reducing the leakage current of the second reset transistor M7 and improving the stability of the anode voltage of the light-emitting element LED.

[0045] It should be noted that the figure only shows an example of the buffer stage being located after the data writing stage and before the light emission stage, but it is not limited to this. In other optional embodiments, the buffer stage may also be after the reset stage and before the data writing stage, after the light emission stage and before the reset stage of the next driving cycle, or during the data writing stage and the light emission stage when the reset transistor is off. These embodiments of the present invention will not be described in detail.

[0046] Furthermore, the conduction phases of the first reset transistor and the second reset transistor can be different. The gates of the first reset transistor and the second reset transistor can also receive scan signals that are not provided. For example, the gate of the second reset transistor can receive the same scan signal as the gates of the data writing transistor and the threshold compensation transistor, as long as the conduction phase of the first reset transistor is before the data writing phase and the conduction phase of the second reset transistor is before the light emission phase in one driving cycle of the pixel circuit. The embodiments of the present invention do not limit the conduction phases of the first reset transistor and the second reset transistor.

[0047] The display panel provided in this embodiment of the invention, by setting a reset stage and a buffer stage during the operation of the pixel circuit, and by setting the reset signal V1 received by the reset transistor in the reset stage to be different from the voltage V2 of the reset signal received by the reset transistor in the buffer stage, can reduce the voltage difference between the first and second terminals of the reset transistor in the buffer stage, reduce the source-drain voltage of the reset transistor, alleviate the electric field stress of the reset transistor, thereby improving the performance and lifespan of the reset transistor and preventing the reset transistor from failing under large bias stress for a long time. At the same time, it can also reduce the offset of the threshold voltage, reduce the leakage current, thereby improving the stability of the driving module and / or the light-emitting element, enabling the light-emitting element to emit light accurately and improving the display effect of the display panel.

[0048] Optional, |V2|<|V1|.

[0049] For example, refer to Figure 2 and Figure 4 Taking the reset transistor, including the first reset transistor M4, as an example. When the driving transistor M3 is a P-type transistor, during the reset phase t1, the gate of the driving transistor M3 needs to receive a small negative voltage signal, that is, at this time, the voltage V1 of the first reset signal Vref1 is a small negative value with a large absolute value; during the data writing phase, the reset transistor is turned off, the gate of the driving transistor M3 writes the data signal and the threshold voltage, the driving transistor M3 is turned off, and the gate of the driving transistor M3 is raised, that is, the voltage of the second terminal of the first reset transistor M4 is raised. In order to reduce the voltage stress of the first reset transistor M4, the voltage of the first reset signal Vref1 needs to be increased. At this time, the voltage V2 of the first reset signal Vref1 is a large negative value with a small absolute value.

[0050] When the driving transistor M3 is an N-type transistor, during the reset phase t1, the gate of the driving transistor M3 needs to receive a large positive voltage signal. That is, the voltage V1 of the first reset signal Vref1 is a large positive value with a large absolute value. During the data writing phase, the first reset transistor M4 is turned off, and the gate of the driving transistor M3 is written with the data signal and the threshold voltage. The driving transistor M3 is then turned off, and its gate is pulled low. This means the voltage at the second terminal of the first reset transistor M4 is pulled low. To reduce the voltage stress on the first reset transistor M4, the voltage of the first reset signal Vref1 needs to be reduced. At this time, the voltage V2 of the first reset signal Vref1 is a small positive value with a small absolute value. This effectively alleviates the electric field stress on the first reset transistor M4 and reduces its leakage current.

[0051] refer to Figure 2 and Figure 5 Taking the reset transistor, including the second reset transistor M7, as an example. During the reset phase t1, to clear the electrical signal from the previous display cycle from the anode of the LED, the anode needs to receive a small negative electrical signal. That is, at this time, the voltage V1 of the second reset signal Vref2 is a small negative value with a large absolute value. During the light-emitting phase, the second reset transistor M7 is turned off, and a larger positive electrical signal is written to the anode of the LED. To reduce the voltage stress on the second reset transistor M5, the voltage of the second reset signal Vref2 needs to be increased. At this time, the voltage V2 of the second reset signal Vref2 is either a large negative value or a small positive value with a small absolute value. This effectively alleviates the electric field stress on the second reset transistor M7 and reduces its leakage current.

[0052] Optional, Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 6 The pixel circuit's operation also includes a light-emitting stage t3; a buffer stage t01 includes a first buffer stage t011; and a light-emitting stage t3 includes a first stage t31 and a first buffer stage t011. The driving transistor M3 provides driving current to the LED element during the light-emitting stage t3. The reset transistor receives a reset signal with a voltage of V3 in the first stage t31, where V3 ≠ V2.

[0053] For example, consider a reset transistor including a first reset transistor M4, where all transistors are P-type transistors. During the light-emitting phase t3, the light-emitting control signal Em(n) is low, the first light-emitting control transistor M1, the driving transistor M3, and the second light-emitting control transistor M6 are turned on, and all other transistors are turned off. At this time, the gate voltage of the driving transistor M3 is Vdata - |Vth|. To reduce the source-drain voltage of the first reset transistor M4, the voltage of the first reset signal Vref1 can be appropriately adjusted during the light-emitting phase t3. In one embodiment, the voltage of the first reset signal Vref1 during a portion of the light-emitting phase t3 can be greater than the voltage V1 of the first reset signal Vref1 during the reset phase t1. For example, the voltage V3 of the first reset signal Vref1 during the first phase t31 can be slightly greater than the voltage V1 of the first reset signal Vref1 during the reset phase t1, and the voltage V2 of the first reset signal Vref1 during the first buffer phase t011 is greater than the voltage V3 of the first reset signal Vref1 during the first phase t31.

[0054] Thus, by setting a first buffer stage t011 in the light-emitting stage t3, the electric field stress accumulated on the first reset transistor M4 in the current driving cycle of the pixel circuit can be alleviated. This prevents the first reset transistor M4 from being under a large electric field stress throughout the light-emitting stage t3, which is beneficial to improving the performance and lifespan of the first reset transistor M4. Furthermore, it reduces the leakage current of the first reset transistor M4 in the light-emitting stage t3 of the current driving cycle, thereby improving the stability of the gate voltage of the driving transistor M3. It is understood that the reset transistor may also include a second reset transistor M7, which can improve the performance and lifespan of the second reset transistor M7 and reduce its leakage current in the light-emitting stage t3 of the current driving cycle. This will not be described in detail in this embodiment of the invention.

[0055] Optional, |V2|<|V3|.

[0056] For example, when the reset signal voltage V1 is negative during the reset phase, to reduce the source-drain voltage and electric field stress of the reset transistor, the reset signal voltage V2 during the buffer phase increases compared to V1, but its absolute value decreases. When the reset signal voltage V1 is positive during the reset phase, to reduce the source-drain voltage and electric field stress of the reset transistor, the reset signal voltage V2 during the buffer phase decreases compared to V1, and its absolute value also decreases. Similarly, compared to the reset signal voltage V3 in the first phase, the absolute value of the reset signal voltage V2 in the first buffer phase also decreases, which can reduce the electric field stress of the reset transistor, thus improving the performance and lifespan of the reset transistor, and reducing the leakage current of the reset transistor.

[0057] Optionally, in the first stage, the potential difference between the second terminal of the reset transistor and the first terminal of the reset transistor is ΔV1; in the first buffer stage, the potential difference between the second terminal of the reset transistor and the first terminal of the reset transistor is ΔV2; |ΔV2|<|ΔV1|.

[0058] Specifically, in the first buffer stage, the absolute value of the potential difference ΔV2 between the second terminal of the reset transistor and the first terminal of the reset transistor is smaller. At this time, the source-drain voltage of the reset transistor is smaller, which can effectively reduce the electric field stress of the reset transistor, reduce the leakage current of the reset transistor, and improve the stability of the driving module and / or the light-emitting element.

[0059] Optional, Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 7 V1 = V3.

[0060] For example, consider a reset transistor including a first reset transistor M4, where all transistors are P-type transistors. The voltage V3 of the first reset signal Vref1 in the first stage t31 is equal to the voltage V1 of the first reset signal Vref1 in the reset stage t1. The voltage of the first reset signal Vref1 changes only in the first buffer stage t011, and the voltage of the first reset signal Vref1 in the reset stage t1 and the first stage t31 is consistent. On the one hand, V1 = V3 simplifies timing and reduces coupling between signal lines, thereby improving signal stability.

[0061] Figure 8 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 7 and Figure 8 The light-emitting phase t3 of the pixel circuit overlaps with the reset phase t1 of other row pixel circuits, and the first phase t31 of the pixel circuit may overlap with the reset phase t1 of other row pixel circuits. In one embodiment, the scan signals received by the same row pixel circuit are the same, and the timing of the same row pixel circuit is the same, that is, the reset phase, data writing phase, light-emitting phase, and buffering phase of the same row pixel circuit are the same. The scan signals received by different rows of pixel circuits are different, and the timing of different rows of pixel circuits is different, that is, the reset phase, data writing phase, and light-emitting phase of different rows of pixel circuits may be different. In a display frame F0, the first reset signal Vref1 may go through one or more first buffering phases t011. The first buffering phases t011 of different rows of pixel circuits may overlap or not overlap, as long as the first buffering phase t011 of the pixel circuit does not overlap with the reset phase t1 of the same row pixel circuit and other row pixel circuits. This embodiment of the invention does not limit this.

[0062] On the other hand, V1 = V3 ensures that the gate of the driving transistor M3 in other row pixel circuits writes the first reset signal Vref1 with the required voltage V1 during the reset phase t1, avoiding the overlap of the first phase t31 of the pixel circuit with the reset phase t1 of other row pixel circuits, which would cause abnormal potential of the first reset signal Vref1 received by the gate of the driving transistor in other pixel circuits during the reset phase. If the potential of the first reset signal Vref1 is abnormal, the driving transistor M3 may not be fully turned on, and during the data writing phase, the data signal Vdata may not be fully written to the gate of the driving transistor M3.

[0063] It is understandable that the reset transistor may also include a second reset transistor M7. V1 = V3 can prevent the first stage of the pixel circuit from overlapping with the reset stage of other row pixel circuits, which would cause the potential of the second reset signal Vref2 received by other light-emitting elements LEDs during the reset stage to be abnormal and unable to completely clear the electrical signal of the previous driving cycle (the previous display frame F0).

[0064] Optionally, a blank phase tb is included between two adjacent frames of the display panel; the buffer phase includes a second buffer phase t012; the blank phase tb includes the second buffer phase t012.

[0065] For example, Figure 9 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 9 Taking the reset transistor, including the first reset transistor M4, and all transistors being P-type transistors, as an example, before the blank phase tb, the display panel is in the data refresh phase ts. Each row of pixel circuits sequentially performs a reset phase and a data writing phase, causing each pixel circuit in the display panel to write its corresponding data signal, and the display panel displays the image of display frame F0. In one embodiment, the data writing phase of the pixel circuit coincides with the reset phase of the next row of pixel circuits. During the blank phase tb, scan signals Scan1-Scan2401 are all high-level signals, and the reset transistors and data writing transistors of all pixel circuits are in the off state. The storage capacitors of the pixel circuits can store and hold the data signal, allowing the display panel to continue displaying display frame F0. During the blank phase tb, the data signal can also be cleared, allowing the display panel to accurately display image information in the next display frame F0.

[0066] This embodiment of the invention, by setting a second buffer stage t012 in the blank stage tb, and changing the voltage of the first reset signal Vref1 in the blank stage tb, can effectively reduce the source-drain voltage of the first reset transistor M4, thereby reducing the electric field stress of the first reset transistor M4 and preventing the first reset transistor M4 from being under high voltage stress for a long time, which would affect the performance and lifespan of the first reset transistor M4. It can also prevent the second buffer stage t012 from overlapping with the reset stage t1 or data writing stage t2 of any pixel circuit. While alleviating the electric field pressure on the first reset transistor M4, the pixel circuit can also effectively clear the residual data signal from the previous driving cycle (the previous display frame F0), allowing the display panel to display accurately. It is understood that the reset transistor may also include a second reset transistor M7, which will not be described in detail here.

[0067] It should be noted that the figure is only an example of a display panel including 2400 rows of pixel circuits and 2401 scan signals. In other optional embodiments, the display panel may also include other rows of pixel circuits and other numbers of scan signals. This embodiment of the invention does not limit this.

[0068] Optionally, the reset transistor includes a first reset transistor M4 and a second reset transistor M7; the reset signal includes a first reset signal Vref1 and a second reset signal Vref2; the first terminal of the first reset transistor M4 receives the first reset signal Vref1, and the second terminal of the first reset transistor M4 is electrically connected to the driving module; the first terminal of the second reset transistor M7 receives the second reset signal Vref2, and the second terminal of the second reset transistor M7 is electrically connected to the light-emitting element LED; during the reset phase, the first reset signal Vref1 and the second reset signal Vref2 are different.

[0069] For example, Figure 10 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 10Taking P-type transistors as an example, during the reset phase, the first reset transistor M4 controls the driving transistor M3 to be fully turned on before the data signal is written. When the driving module includes the P-type driving transistor M3, the first reset signal Vref1 is a low-voltage negative signal during the reset phase. To ensure the full conduction of the driving transistor M3, the potential of the first reset signal Vref1 is relatively small. During the reset phase, the second reset transistor M7 controls the light-emitting element LED to not emit light. The second reset signal Vref2 is generally a negative signal during the reset phase, but the voltage of the second reset signal Vref2 should not be too low to avoid reverse breakdown of the light-emitting element LED. By setting the first reset signal Vref1 and the second reset signal Vref2 to be different during the reset phase, the driving transistor M3 can be fully turned on during the reset phase, and the light-emitting element LED can be turned off. The pixel circuit can effectively clear the electrical signals in the previous driving cycle.

[0070] Optionally, during the buffering phase, the first reset signal Vref1 and the second reset signal Vref2 are different. During the reset phase, both the first reset signal Vref1 and the second reset signal Vref2 are modified. The modification of the first reset signal Vref1 aims to reduce the voltage difference between the first reset signal Vref1 and the gate of the driving transistor M3. The modification of the second reset signal Vref2 aims to reduce the voltage difference between the second reset signal Vref2 and the anode of the light-emitting element LED. Since their initial signals are different, their purposes for modification are different, and the modified signals are also different, this effectively reduces the electric field stress and leakage current of the first reset transistor M4 and the second reset transistor M7, improving the stability of the pixel circuit.

[0071] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 11 The display device includes the display panel provided in any embodiment of the present invention. The display device provided in the embodiments of the present invention can be a mobile phone as shown in the figure, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on these categories.

[0072] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a reset module; The driving module is used to selectively provide driving current to the light-emitting element; The reset module includes a reset transistor; the first terminal of the reset transistor receives a reset signal, and the second terminal of the reset transistor is electrically connected to the driving module and / or the light-emitting element. The operation of the pixel circuit includes a buffering phase and a reset phase; in the reset phase, the reset transistor is turned on; in the buffering phase, the reset transistor is turned off. Wherein, the voltage of the reset signal received by the reset transistor in the reset phase is V1, and the voltage of the reset signal received by the reset transistor in the buffer phase is V2, where V1≠V2; The operation of the pixel circuit further includes a light-emitting stage; the buffering stage includes a first buffering stage; the light-emitting stage includes a first stage and the first buffering stage; In the first stage, the potential difference between the second terminal of the reset transistor and the first terminal of the reset transistor is ΔV1. In the first buffer stage, the potential difference between the second terminal of the reset transistor and the first terminal of the reset transistor is ΔV2; |ΔV2|<|ΔV1|.

2. The display panel of claim 1, wherein, |V2|<|V1|.

3. The display panel of claim 1, wherein, The driving module is used to provide driving current to the light-emitting element during the light-emitting stage; The voltage of the reset signal received by the reset transistor in the first stage is V3; V3 ≠ V2.

4. The display panel according to claim 3, characterized in that, |V2|<|V3|.

5. The display panel according to claim 3, characterized in that, V1=V3.

6. The display panel according to claim 1, characterized in that, The display panel includes a blank phase between two adjacent frames; the buffer phase includes a second buffer phase; the blank phase includes the second buffer phase.

7. The display panel according to claim 1, characterized in that, The reset transistor includes a first reset transistor and a second reset transistor; the reset signal includes a first reset signal and a second reset signal; The first terminal of the first reset transistor receives the first reset signal, and the second terminal of the first reset transistor is electrically connected to the driving module. The first terminal of the second reset transistor receives the second reset signal, and the second terminal of the second reset transistor is electrically connected to the light-emitting element; During the reset phase, the first reset signal is different from the second reset signal.

8. The display panel according to claim 7, characterized in that, During the buffering phase, the first reset signal is different from the second reset signal.

9. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-8.

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