A multi-stage light emitting branched nanowire light emitting device and a preparation method thereof

Abstract

The application discloses a kind of multistage branch nanowire light emitting devices and preparation method thereof, including at least one tree structure nanowire grown in the active region of CMOS device or silicon substrate, the tree structure nanowire includes stem nanowire and at least one branch nanowire connected on the stem nanowire, and the branch nanowire contains multiple light emitting regions.Solve the technical bottleneck of pixel particle miniaturization, so that a single chip can reduce the serious particle feeling of VR picture, grid, brightness contrast is not enough and other serious problems affecting the realism of picture.Therefore, the display device manufactured by the semiconductor of the application has the advantages of super high pixel density, small volume, light weight, low power consumption, high luminous brightness, portability, color temperature stability, long service life, full color / single color can be realized, etc.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor light-emitting devices, and particularly relates to a multi-stage light-emitting branched nanowire light-emitting device and a preparation method thereof. BACKGROUND

[0002] With the application and development of artificial intelligence in modern society, information acquisition, storage, transmission, processing and output are increasingly important. In terms of information acquisition, visual information is the main way for humans to obtain information about the external world. At present, liquid crystal displays (LCDs) and organic electroluminescent displays (OLEDs) dominate the market and are mainly used in mobile phones, televisions, computers and other fields. However, people's pursuit of display performance is endless, especially in recent years with the application of virtual reality (VR), augmented reality (AR) and large-screen display. However, there are still many problems to be solved in display, and the core problem is that the display screen built-in VR does not have high display precision. Most of the existing VR devices use LCD screens or OLED screens, which have certain problems in pixel particle miniaturization. Liquid crystal particles are sufficient for existing medium and long distance applications, but they are not fine enough in VR design with super-close distance and enlarged pixels. OLEDs have difficulty in further miniaturization due to their inherent principles, so the VR screen we see may have serious particles, grid, low brightness contrast, and seriously affect the realism of the picture. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a multi-stage light-emitting branched nanowire light-emitting device and a preparation method thereof to solve the technical bottleneck of pixel particle miniaturization, so that a single chip can reduce the problems of serious particle feeling, grid, low brightness contrast and other serious problems that seriously affect the realism of the picture in VR picture.

[0004] The present application adopts the following technical solutions:

[0005] In a first aspect, the embodiments of the present application provide a multi-stage branched nanowire light-emitting device, which includes at least one tree structure nanowire grown on an active region of a CMOS device or a silicon substrate, the tree structure nanowire includes a trunk nanowire and at least one branch nanowire connected to the trunk nanowire, and the branch nanowire contains a plurality of light-emitting regions.

[0006] The application is based on direct integration of Si-based CMOS devices or common silicon substrates and multi-stage luminescent dendritic structure nanowires. This design realizes multiple light-emitting points by designing different quantum wells or quantum dots and their combination through the multi-layer branch nanowires of the dendritic structure nanowires, realizes pixel particle miniaturization, and obtains high-precision nanowire light-emitting devices. The application does not require massive transfer technology, and does not require additional leads or solder joints for the connection of the array and the circuit, thereby breaking through the problem of device and circuit integration, and also having the advantages of super-high pixel points, high brightness, high contrast, small volume, low power consumption, independent driving, and being conducive to portable use.

[0007] The light-emitting of the NLED comes from the nanowires with small size, and in the case that the process meets the requirements, the direction of the branch nanowires can be designed to realize fine display. That is, the smallest pixel particle that can be realized is more fine than the current popular Micro-LED, and the high-brightness characteristics also bring better contrast and better image effect. In terms of energy consumption, since the NLED is low in power consumption by nature, when applied to VR headsets and other devices, it also has very outstanding energy consumption performance, and the endurance and heating performance are also more outstanding.

[0008] The dendritic structure nanowires can be grown in the active area of the CMOS device to realize the high integration of the driving circuit, the control circuit and the light-emitting array, and can also be grown on a common silicon substrate and interconnected with other control circuits. The CMOS device substrate is preferably a Si(100) substrate.

[0009] Optionally, the light-emitting region contains at least one light-emitting wavelength, and the light-emitting region can be designed according to the actual pixel color distribution and the demand.

[0010] Optionally, the CMOS device contains two or more Si(100) MOS devices, and at least one MOS device is an independent control unit. The MOS device can be an N-channel enhancement type, an N-channel depletion type, a P-channel enhancement type or a P-channel depletion type, and the MOS device contains a source, a drain and a gate.

[0011] Optionally, the active area of the MOS device grows a single or multiple dendritic structure nanowires. For a MOS containing multiple dendritic structure nanowires, adjacent dendritic structure nanowires in one MOS control unit can be homogenous or heterogeneous materials, and the dendritic structure nanowires of adjacent MOS control units can be arranged and distributed in a homogenous or heterogeneous material. Through the design of the nanowire material of the application, a single-color or multi-color full-color light-emitting array is realized, and the colors can cover multiple color systems such as red, orange, yellow, green, cyan, blue, purple and white.

[0012] Optionally, the tree-structure nanowire and the silicon substrate are heterogeneous materials. The tree-structure nanowire material adopts a semiconductor material system, and realizes the super-long actual service life, stable light-emitting efficiency and stable light-emitting color of the light-emitting array. Moreover, the tree-structure nanowire and the silicon substrate are heterogeneous materials, which breaks through the limitation of single color of the light-emitting array on the silicon substrate.

[0013] Optionally, the trunk nanowire and the branch nanowire can be homogeneous or heterogeneous materials. The branch nanowire at each level and the branch nanowire can be homogeneous or heterogeneous materials. The color of the light-emitting array is adjusted.

[0014] Optionally, the light-emitting region is arranged radially or axially along the nanowire. Through controllable synthesis of the nanowire, the number of light-emitting regions can reach more than 50, which is much higher than the number of light-emitting of the thin film light-emitting array, and realizes the adjustable and high brightness of the nanowire light-emitting array.

[0015] Optionally, the light-emitting region of the present application is a PN junction and a structure containing a sandwich, such as a p-i-n junction. The PN junction can be a homojunction, a single heterojunction (SH) or a double heterojunction (DH).

[0016] Optionally, the PN junction region of the nanowire is a quantum well, a quantum dot or a combination of quantum well and quantum dot.

[0017] Optionally, each branch of the branch nanowire can be controlled in segments, partial segments or as a whole.

[0018] In the second aspect, the present application also provides a preparation method of the above-mentioned multi-level branch nanowire light-emitting device, at least comprising: preparation of nanowire on a silicon substrate and construction of a CMOS circuit; the sequence of the two steps can be adjusted according to actual working conditions.

[0019] The preparation of nanowire on the silicon substrate comprises:

[0020] Growth of nanowire on a Si(111) substrate or a Si(100) substrate.

[0021] In some embodiments of the present application, the specific process of the construction of the CMOS circuit is as follows:

[0022] 1) deposition of a first layer of photoresist;

[0023] 2) mask, exposure and etching to form an opening structure;

[0024] 3) removal of the first layer of photoresist;

[0025] 4) filling of the first insulating medium in the opening to form a shallow trench isolation structure;

[0026] 5) deposition of a first insulating layer, a first conductive layer and a second layer of photoresist in sequence.

[0027] 6) Mask, exposure, etch to form gate of MOS device;

[0028] 7) Strip second photoresist layer;

[0029] 8) Deposit third photoresist layer;

[0030] 9) Mask, exposure, lithography to form regions of desired doping for source and drain of MOS device;

[0031] 10) Perform ion implantation to form source and drain of MOS device;

[0032] 11) Strip third photoresist layer;

[0033] 12) Deposit fourth photoresist layer;

[0034] 13) Mask, exposure, lithography to expose source or drain of MOS device (where no dendritic nanowire array is to be formed);

[0035] 14) Deposit second conductive layer and etch to form metal contact;

[0036] 15) Remove fourth photoresist layer;

[0037] 16) Deposit fifth photoresist layer

[0038] 17) Mask, exposure, lithography to expose source or drain of MOS device (where dendritic nanowire array is to be formed);

[0039] 18) Deposit third conductive layer and etch to form metal contact;

[0040] 19) Remove fifth photoresist layer.

[0041] In some embodiments of the present application, the dendritic nanowires can be grown vertically on the CMOS, including but not limited to the following:

[0042] 1) Deposit first photoresist layer;

[0043] 2) Mask, exposure, etch to form opening structure;

[0044] 3) Deposit mask material;

[0045] 4) Strip first photoresist layer, leaving mask material only in the original opening structure;

[0046] 5) Nanowires grow in the areas without mask material (areas without mask material correspond to source or drain of MOS device);

[0047] 6) Strip mask material.

[0048] Or, the tree structure nanowire is formed by the constrained channel directional growth of the tree structure nanowire on a silicon substrate, and the formation process is as follows:

[0049] 1) depositing a first layer of photoresist;

[0050] 2) forming an opening structure by masking, exposing and etching;

[0051] 3) depositing a mask material;

[0052] 4) depositing a second layer of photoresist;

[0053] 5) forming at least one constrained channel by masking, exposing and etching in the mask material area;

[0054] 6) removing the second layer of photoresist.

[0055] The first insulating medium and the mask material are SiO2, SiO x , Si3N4 and SiN x .

[0056] The first layer of insulating layer is silicon dioxide, high-k material, two-dimensional material or a mixed layer therebetween. The first layer of conductive layer is a metal gate material such as TiN and TaN or doped polysilicon.

[0057] The second and third layers of conductive layer are metal conductive materials such as Cu, Al, Ti and Au.

[0058] In some embodiments of the present application, the tree structure nanowire growth method is etching, hydrothermal self-assembly, epitaxial growth including MOCVD, LPCVD, MBE and the like. The main stem nanowire array is normally grown first, and then the hierarchical nanowire nucleation points of the main stem nanowire are subjected to catalytic droplet sputtering to grow hierarchical nanowires at the nucleation points.

[0059] The nanowire material of the present application is a semiconductor of Si, Ge, oxide, II-IV group or III-V group material.

[0060] The present application has the following beneficial effects:

[0061] The multi-stage branched nanowire is integrated in a silicon substrate to form a nanowire light-emitting device, which overcomes the problem of low display precision of a display screen built in virtual reality (VR), and proposes a technical structure of the branched nanowire light-emitting array of each stage "branch" of the independent control on the silicon substrate, solves the technical bottleneck of pixel particle miniaturization, and makes a single chip reduce the serious particle feeling, grid, insufficient brightness contrast and other problems that seriously affect the realism of the picture of the VR picture. Therefore, the display device manufactured by the semiconductor technology has the advantages of super high pixel density, small volume, light weight, low power consumption, high luminous brightness, portability, stable color temperature, long service life, full color / single color realization and the like. Moreover, the high integration of the CMOS integrated circuit and the light-emitting array greatly simplifies the system of the nanowire display device, reduces the production cost, and has commercialization prospects. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 It is a schematic diagram of the integration and growth of the CMOS device active area and the whole metal electrode of the multiple independent tree structure nanowire in the embodiment of the application; wherein (a) is a side view, and (b) is a top view;

[0063] Figure 2 It is a schematic diagram of the simultaneous growth of the silicon substrate of the multiple independent tree structure nanowire array (each segment of the branched nanowire can be controlled in segments, partial segments or the whole) in the embodiment of the application;

[0064] Figure 3 It is a schematic diagram of the growth of the silicon substrate of the tree structure nanowire array in the embodiment of the application;

[0065] Figure 4 It is a schematic diagram of the radial structure of the tree structure nanowire in the embodiment of the application; wherein (a) is a side view, and (b), (c), (d) and (e) are top views of different light-emitting area structures;

[0066] Figure 5 It is a schematic diagram of the axial structure of the tree structure nanowire in the embodiment of the application;

[0067] Figure 6a It is a schematic diagram of the mask processing of the silicon substrate in the embodiment of the application;

[0068] Figure 6b It is a schematic diagram of the preparation of the pattern for doping of the source area and the drain area of the MOS transistor in the embodiment of the application;

[0069] Figure 6c It is a schematic diagram of the preparation of the MOS transistor in the embodiment of the application;

[0070] Figure 6d It is a schematic diagram of the growth of the nanowire on the MOS and the filling of the protective layer in the embodiment of the application;

[0071] Figure 6e Schematic diagram of the fabrication of a nanowire array electrode according to an embodiment of the present invention.

[0072] Among them, there are silicon substrate 1, doped region 2, source region 3, drain region 4, gate dielectric layer / shallow trench isolation structure 5, gate electrode 6, electrode 7, filling material 8, tree-structured nanowires 9, ITO transparent electrode 10, n-type region 11, light-emitting layer 12 / 13 / 14, and p-type region 15. DETAILED DESCRIPTION

[0073] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0074] The drawings are for illustrative purposes only and should not be construed as limiting this patent. To better illustrate the embodiments, some components in the drawings may be omitted, enlarged, or reduced in size, and do not represent actual product dimensions. Those skilled in the art will understand that some well-known structures and their descriptions may be omitted from the drawings. The positional relationships depicted in the drawings are for illustrative purposes only and should not be construed as limiting this patent.

[0075] like Figures 1-2 As shown, a CMOS-integrated, AC-driven, actively addressed NLED micro-display device includes a light-emitting component and a CMOS device. The CMOS device includes four types of MOS cells: A, B, C, and D. As is common knowledge in the art, the MOS device includes a source region 3, a drain region 4, and a gate region consisting of a gate dielectric layer / shallow trench isolation structure 5 and a gate electrode 6. Both the source region 3 and the drain region 4 are active regions as described herein; the nano-LED tree-like nanowires / nano-LED tree-like light-emitting array is grown in either the source region 3 or the drain region 4. The gate dielectric layer / shallow trench isolation structure 5 serves as an isolation layer for each MOS group in the MOS circuit.

[0076] Among them, the size of MOS can be adjusted according to the existing integration process, and each MOS can be independently controlled by its gate, so that the nanowire integrated with it becomes an independent pixel point, and each pixel can be an LED of a different color and has the function of being driven and emitting light beams independently by AC voltage.

[0077] Figure 1 In the present invention, the A-type and B-type MOS are NMOS with N-channels, while the C-type and D-type MOS are PMOS with P-channels. The N-type substrate is a Si (100) substrate doped with pentavalent elements such as arsenic, phosphorus, and antimony, while the P-type substrate can be a Si (100) substrate doped with trivalent elements such as boron.

[0078] Figure 2MOS light-emitting unit, which can be a class B / class C MOS device and a dendritic nano-wire array self-assembled and grown in the active region of the MOS device, and each segment of the branch nano-wire can be controlled in segments, partial segments or as a whole. Figure 3 The figure is a schematic diagram of growth of the dendritic nano-wire array. The MOS device adopts a (100) crystal plane of a silicon substrate 1. The nano-wire light-emitting array can be made of AlGaAs, InGaAsP, GaP, GaAsP, AlGaInP, InGaN, GaN, SiC or other materials containing single or multiple quantum wells, quantum dots or pure single material structures. The nano-wire surface is wrapped with a passivation layer, which separates the nano-wire and the nano-wire, the nano-wire and other materials, and protects the device from the external environment. Figure 2 In the figure, the filling material 8 can encapsulate and protect the device. The electrode 7 is a metal material, which is a metal electrode of the device, and the electrode 10 is a transparent ITO material, which is a connection part of the branch of the dendritic nano-wire and the electrode 7. By controlling the voltage of the electrode at the top of the multi-stage branch nano-wire, the V DS Different, form V DS1 , V DS2 , V DS3 , V DSx , etc., through V G and V DSx to realize independent control of the multi-stage branch nano-wire of the dendritic nano-wire, and to realize multi-stage control effect. It should be noted that the B unit is two independent branch nano-wires, which can be extended to two dendritic nano-wire arrays.

[0079] For the above-mentioned dendritic nano-wire 9, there can be the following five cases:

[0080] 1) The contact interface between the source or drain on the surface of the CMOS device and the single (multiple) dendritic nano-wire in the region is of the first type, which is p-type material;

[0081] 2) The contact interface between the source or drain on the surface of the CMOS device and the single (multiple) dendritic nano-wire in the region is of the second type, which is n-type material;

[0082] 3) The contact interface between the source or drain on the surface of the CMOS device and the single (multiple) dendritic nano-wire in the region is of the third type, which is p-n type material;

[0083] 4) The contact interface between the source or drain on the surface of the CMOS device and the single (multiple) dendritic nano-wire in the region is of the fourth type, which is n-p type material;

[0084] 5) The single contact interface between the source or drain of the CMOS device surface and the multiple tree-structured nanowires in the region is of the same p, same n, p-n, n-p type material, which is the fifth type.

[0085] The entire nanowire light emitting array can be arranged and combined by the above five types or the derived types of the five types.

[0086] The branch nanowires of the tree-structured nanowires contain at least one light emitting region, and in some preferred schemes, contain more than two light emitting regions. The light emitting region of the present application refers to the light emitting region of the nanowire, which can be the entire branch nanowire light emitting or the local branch nanowire light emitting. Regardless of the overall region light emitting or the local region light emitting, it can be composed of one or more light emitting regions. Each light emitting region is generally a carrier radiation recombination light emitting (based on the recombination of electrons and holes to realize light emitting); the carrier radiation recombination light emitting can be realized based on the intrinsic material light emitting of the nanowire material or the PN junction and the structure containing the interlayer of the nanowire, thus, the present application is called the intrinsic light emitting region of the nanowire, or the PN junction region of the nanowire.

[0087] The material for realizing the light emitting of the present application includes inorganic materials and organic materials. The inorganic material is generally Si, Ge, oxide, III-V semiconductor material, etc. The organic electroluminescent material can be divided into two categories of small molecules and high molecules according to the different molecular weights of the organic light emitting material. The small molecule OLED material takes organic dyes or pigments as the light emitting material, and the high molecule OLED material takes conjugated or non-conjugated high molecules (polymers) as the light emitting material, and the typical high molecule light emitting material is PPV and its derivatives.

[0088] The above-mentioned PN junction and the structure containing the interlayer can be composed of a single or multiple quantum well or quantum dot structure.

[0089] In the embodiment of the present application, the InGaN / GaN material is taken as an example to describe the manufacturing process of the semiconductor device as shown in Figure 3 , Figure 4

[0090] Figure 4 The radial PN light emitting structure of (a) is composed of n-type GaN (n-type region 11), InGaN / GaN quantum well (light emitting layer 12) and p-type GaN (p-type region 15) grown from inside to outside, and the growth mode is to grow the core nanowire of the n-type GaN trunk in the hole formed by the source region patterning, and then grow the quantum well and the p-type GaN on the surface of the core nanowire of the trunk in turn to form the radial pn structure. The overall trunk nanowire is subjected to repeated branch nanowire growth. Figure 4 (b), (c), (d), (e) show different quantum well structure diagrams.

[0091] ​Figure 5 The axial pn structure is composed of n-type GaN (n-type region 11) grown from bottom to top, InGaN / GaN quantum dots (light emitting layer 12), and p-type GaN (p-type region 15), and the growth mode is to grow a core nanowire of n-type GaN trunk in a hole formed by source region patterning, and then grow quantum dots and n-type GaN successively above the nanowire to form an axial pn structure. The overall trunk nanowire is subjected to repeated branch nanowire growth.

[0092] The tree-structure nanowire light emitting array integrated in a silicon substrate disclosed in the present application can be manufactured by many methods. The following is a description of the manufacturing method of the tree-structure nanowire light emitting array disclosed in the present application as shown in Figure 1 One example of the manufacturing method of the nanowire light emitting array of the Si (100) substrate as shown in Figures 6a-6e The manufacturing process of the nanowire light emitting array as shown in Figure 1 is described.

[0093] (1) A photoresist layer is deposited on a provided Si (100) substrate, and then mask, exposure, and etching are performed to form an opening structure, and then an insulating medium is filled in the formed opening to form a gate dielectric layer / shallow trench isolation structure 5, and the remaining photoresist is removed. The insulating medium is preferably SiO2.

[0094] (3) Next, a photoresist layer is deposited, and then mask, exposure, and photolithography are performed to form a pattern for doping the source region and the drain region of the MOS transistor, and then ion implantation is performed to form the source region 3 and the drain region 4 of the MOS circuit, as shown in Figure 6b . An insulating medium layer is deposited, and the photoresist is removed. Then, a photoresist layer is again deposited, and then mask, exposure, and etching are performed to form the gate electrode of the MOS circuit, and then the remaining photoresist is removed, as shown in Figure 6c . The insulating medium layer is a one-layer or two-layer structure formed by SiO2 and high-k material. The gate electrode 6 is a metal such as Ti / Au.

[0095] (4) A photoresist layer is deposited, and then mask, exposure, and etching are performed to form a hole array on the source region 3, and a tree-structure nanowire light emitting array is grown successively by epitaxial process (preferably MBE). After the nanowire array is grown, a transparent organic material is filled, and the formed structure is as shown in Figure 6d .

[0096] (5) A photoresist layer is deposited, and then mask, exposure, and etching are performed to expose the top region of the source region and the drain region, a metal layer is deposited, and the metal is etched to form an electrode 10, as shown in Figure 6e .

[0097] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the application embrace any and all variations of the present application that fall within the scope of the general inventive concept as defined by the appended claims and their equivalents. The specification and examples are to be considered exemplary only, with the true scope and spirit of the application indicated by the claims.

[0098] It is to be understood that the application is not limited to the precise construction herein described and as shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is to be defined by the claims appended hereto.

Claims

1. A multi-stage branched nanowire light emitting device, characterized by, The application relates to a tree-shaped nano-wire grown on a CMOS device active region or a silicon substrate, the tree-shaped nano-wire comprising a trunk nano-wire and at least one branch nano-wire connected to the trunk nano-wire, the branch nano-wire containing at least one light-emitting region; each section of the branch nano-wire is controlled in a segmented, partially segmented or integral manner. The electrode is a metal material, as a metal electrode of the device, the electrode is a transparent ITO material, as a branch of the tree structure nanowire connected with the electrode, by controlling the voltage of the electrode at the top of the multi-stage branch nanowire, the V DS Different, form V DS1 , V DS2 , V DS3 , V DSx , through V G And V DSx Realize the independent control of the multi-stage branch nanowire of the tree structure nanowire, and can realize the multi-stage control effect.

2. The multi-stage branched nanowire light emitting device of claim 1, wherein, The light-emitting region comprises at least one light-emitting wavelength.

3. The multistage branched nanowire light emitting device of claim 1, wherein, The CMOS device comprises two or more Si(100) MOS devices, and at least one MOS device is an independent control unit.

4. The multistage branched nanowire light emitting device of claim 1, wherein, The active region of the MOS device is grown with single or multiple tree-shaped nano-wires.

5. The multistage branched nanowire light emitting device of claim 1, wherein, The tree-shaped nano-wire comprises at least one non-silicon semiconductor material.

6. The multistage branched nanowire light emitting device of claim 1, wherein, The light-emitting region is arranged in a radial or axial direction along the growth direction of the branch nano-wire.

7. The multistage branched nanowire light emitting device of claim 1, wherein, The light-emitting region is a PN junction and a structure comprising a sandwich, and the PN junction is a homojunction, a single heterojunction (SH) or a double heterojunction (DH).

8. The multistage branched nanowire light emitting device of claim 7, wherein, The PN junction region of the nano-wire is a quantum well, a quantum dot or a combination of quantum well and quantum dot.

9. The fabrication method of multi-stage branched nanowire light-emitting devices according to any one of claims 1-8, wherein, The application further relates to a method for preparing a tree-shaped nano-wire on a substrate and constructing a CMOS circuit, and the preparation of the tree-shaped nano-wire on the silicon substrate comprises the following steps: The application further relates to a method for preparing a tree-shaped nano-wire on a substrate and constructing a CMOS circuit, and the preparation of the tree-shaped nano-wire on the silicon substrate comprises the following steps: Growing a tree-shaped nano-wire on a silicon substrate. ​

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