A method for correcting sampling synchronization of multiple digital oscilloscopes

Abstract

The application discloses a kind of sampling synchronization correction methods of multiple digital oscilloscopes, including master-slave equipment synchronous sampling, the correction of master-slave equipment sampling synchronization and trigger synchronization three steps;In the master-slave equipment synchronous sampling part, master equipment crystal oscillator provides source clock and exports synchronous clock signal to slave equipment, guarantee the clock homology of master-slave equipment;In the correction part of master-slave equipment sampling synchronization, in trigger interface connection signal generator, the delay time ΔT of master-slave equipment sampling clock is estimated by comparing signal transmission path and internal counter of master-slave equipment clk ;In trigger synchronization part, using master-slave mode, slave equipment establishes trigger system by FIFO read-write enable signal and intermediate control signal FIFO_MID generated by master equipment, realizes the read-write operation of trigger data, then makes delay processing to acquisition data, compensates the determinacy delay of edge detection and the indeterminacy delay of transmission path, finally, timing adjustment is carried out to slave trigger signal FIFO_MID to complete trigger synchronization.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of digital oscilloscopes, more specifically, to a sampling synchronization correction method for multiple digital oscilloscopes. BACKGROUND

[0002] A digital oscilloscope (DSO) is a high-speed and high-precision measuring instrument widely used in various complex electronic measurement fields. With the continuous progress of electronic technology, electronic devices are becoming smaller and smaller, and the testing environment is becoming more and more complex. Therefore, there is an increasing demand for improving the adaptability of test instruments in different testing environments. In order to meet this demand, portable and small-sized digital oscilloscopes have become a trend, which can reduce the size and weight of the device, making it more convenient to carry and use. However, due to space limitations, such small digital oscilloscopes are usually designed with fewer channels, which may have certain limitations in testing scenarios that require simultaneous measurement of multiple signals. In order to improve the testing capability of small digital oscilloscopes and ensure the accuracy and reliability of the measurement results, we need to design a method that can synchronize multiple digital oscilloscopes and can be quickly and simply corrected during use, which can ensure the accuracy and reliability of the measurement results, so that the digital oscilloscope can play the best effect in various applications. SUMMARY

[0003] The present application aims to overcome the shortcomings of the prior art and provide a sampling synchronization method for multiple digital oscilloscopes, which realizes the synchronization of multiple device data acquisition, storage, and display through clock synchronization and trigger synchronization, achieving high-precision synchronization triggering of multiple devices.

[0004] To achieve the above-mentioned application purpose, the present application is a sampling synchronization method for multiple digital oscilloscopes, characterized in that it comprises the following steps:

[0005] (1) Set the total number of M digital oscilloscopes in the system that need to be synchronized, take one of the digital oscilloscopes as the master device, and the remaining M-1 digital oscilloscopes as the slave devices, both the master and slave devices are designed with bidirectional input and output clock interfaces A and B, and trigger interfaces A and B;

[0006] (2) Connect the clock interface B and trigger interface B of the master device with the clock interface A and trigger interface A of the slave device 1 respectively using coaxial connection lines, connect the clock interface B and trigger interface B of the slave device 1 with the clock interface A and trigger interface A of the slave device 2 respectively, and so on to connect the M digital oscilloscopes, forming a multi-machine serial data acquisition system;

[0007] (3) Perform the synchronization sampling process of the master and slave devices;

[0008] (3.1) The internal circuit design of the master and slave devices is the same. The internal crystal oscillator of the master device provides a 10MHz clock source for the clock chip, and at the same time, it outputs a separate 10MHz synchronous clock signal.

[0009] (3.2) The 10MHz synchronous clock signal is transmitted to the clock interface B through the FPGA clock programming control circuit in the master device. This interface is connected to the slave device clock interface A through a coaxial cable.

[0010] (3.3) The 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit continuously adjusts the phase of the crystal oscillator of the slave device to make it equal to the phase of the 10MHz synchronous clock signal. The adjusted crystal oscillator provides a 10MHz clock source for the clock chip of the slave device.

[0011] (3.4) The master and slave devices generate the sampling clock of the ADC through the same clock chip with their own clock source and start data acquisition. The analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC along the same path.

[0012] (4) Perform the correction process for master-slave device sampling synchronization;

[0013] (4.1) Estimate the clock delay ΔTclk between the master and slave devices;

[0014] (4.1.1) The transmission and connection of the master and slave device clock signals remain unchanged. Two coaxial connecting lines of equal length are used to connect the trigger interface B of the master and slave devices to the signal generator. The signal generator can generate a 10MHz test signal and transmit it to the counter inside the device. The FPGA internal routing tool is used to make the distance from the trigger interface B of the master and slave devices to their respective counters equal. The transmission time of the test signal to the counter is recorded as T0.

[0015] (4.1.2) Taking the master crystal oscillator as the reference, the transmission delay time of the clock signal from the master crystal oscillator to the master FIFO is T1, and the transmission delay time to the slave FIFO is T2. The transmission paths from the master and slave crystal oscillators to the sampling ADC are the same, that is, the delay time ΔTclk of the sampling clock of the master and slave devices is equal to the transmission delay time of the synchronous clock signal between the master and slave crystal oscillators.

[0016] (4.1.3) Start the internal counter of the master and slave devices. The master device starts counting when it detects the data stored in the FIFO and stops counting after detecting the test signal from the trigger interface B. The counting time of the master device is Tm = T1 - T0 = N1t.

[0017] (4.1.4) The counting starts when the device detects data stored in the FIFO and ends when it detects a test signal from the trigger interface B. The counting time of the slave device is Ts = T2 - T0 = N2t.

[0018] (4.1.5) According to (4.1.2) to (4.1.4), the delay time ΔTclk of the sampling clock of the master and slave devices is T2-T1=(N2-N1)t;

[0019] (4.2) Master-slave sampling clock skew correction;

[0020] Let ΔTclk_min be the phase difference between the most recent rising edge of the master and slave sampling clocks, T be the sampling clock period, and N be the maximum number of complete sampling clock periods contained in ΔTclk, i.e., ΔTclk = ΔTclk_min + NT. Delay the phase difference of the ADC sampling clock of the slave device until the sampling clock phases of the master and slave devices are consistent. At this point, the sampling clock synchronization of the master and slave devices is completed.

[0021] (5) Triggering synchronization of master and slave devices;

[0022] (5.1) Connect the trigger interface B of the master device to the trigger interface A of the slave device 1 using a coaxial cable. Set the trigger source of the master device to its own analog channel mode and the trigger source of the slave device to the external trigger channel mode. Set the master and slave devices to the same trigger depth.

[0023] (5.2) Set the master device trigger conditions. The FPGA of the master device generates FIFO read / write enable signals to control data storage and reading according to the trigger conditions.

[0024] (5.2.1) The master device generates the intermediate control signal FIFO_MID together with the FIFO read and write enable signal. The specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high; when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low; otherwise, it remains unchanged.

[0025] (5.2.2) FIFO_MID enters the slave device through the coaxial connection cable of the master-slave device trigger interface. The FPGA of the slave device generates a FIFO read / write enable signal to control the data storage and reading of the slave device according to FIFO_MID. When the FPGA of the slave device detects the rising edge of FIFO_MID, it pulls up the FIFO write enable signal of the slave device. At this time, it starts to write the acquired data to the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth. Then it pulls up the FIFO read enable signal of the slave device. At this time, the FIFO performs both data writing and reading operations.

[0026] When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the acquired data into the post-trigger memory area. This continues until the post-trigger memory area is full. Then, the slave device write enable is pulled low and the read enable is pulled high to retrieve the acquired data after it is full for subsequent processing, thus completing the slave device triggering process.

[0027] (5.3) Trigger point offset correction;

[0028] The FPGA of the device performs delay processing on the acquired data to compensate for the delay of edge detection and transmission path. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position.

[0029] (5.4) Adjust the timing of the control signal FIFO_MID between the master and slave to keep it away from the metastable range of the slave processing clock;

[0030] The delay of the control signal FIFO_MID is independently adjusted by calling the FPGA's internal IDELAYE2 resource. The optimal delay value is determined by the following steps: delay the FIFO_MID signal until it is just away from the metastable range, and the data transmission goes from misaligned to aligned as the starting point delay0. Then increase the delay value until the data goes from aligned to misaligned as the ending point delay1. The optimal delay value is (delay0+delay1) / 2. The timing adjustment of the control signal FIFO_MID is completed, and the master-slave device trigger synchronization is completed.

[0031] (6) After the master device and slave device 1 are synchronized, slave device 1 is similar to the master device. It completes the synchronization and calibration process according to steps (3), (4), and (5). Then, the synchronization and calibration of all digital oscilloscopes are completed in the same way.

[0032] The objective of this invention is achieved as follows:

[0033] This invention discloses a sampling synchronization correction method for multiple digital oscilloscopes. The method mainly includes three steps: master-slave device synchronous sampling, master-slave device sampling synchronization correction, and trigger synchronization. In the master-slave device synchronous sampling section, the master device's crystal oscillator provides the source clock and outputs a synchronization clock signal to the slave device, ensuring clock homogeneity between the master and slave devices. In the master-slave device sampling synchronization correction section, a signal generator is connected to the trigger interface. By comparing the signal transmission path with the internal counters of the master and slave devices, the clock delay time ΔT between the master and slave devices is directly estimated. clkIn the trigger synchronization section, a master-slave approach is used. The slave device establishes a trigger system through the FIFO read / write enable signal and the intermediate control signal FIFO_MID generated by the master device to perform read and write operations on the trigger data. Then, the acquired data is delayed to compensate for the deterministic delay of edge detection and the indeterminate delay of the transmission path. Finally, the timing of the slave trigger signal FIFO_MID is adjusted to complete the trigger synchronization. The serially connected digital oscilloscopes sequentially complete the sampling clock synchronization and trigger synchronization, ultimately achieving sampling synchronization of multiple digital oscilloscopes.

[0034] Meanwhile, the sampling synchronization correction method for multiple digital oscilloscopes of the present invention also has the following beneficial effects:

[0035] (1) This sampling synchronization correction method connects a signal generator to the trigger interface and compares the signal transmission path with the internal counters of the master and slave devices to achieve clock synchronization correction between the master and slave devices, ensuring the consistency of sampling and triggering times of multiple digital oscilloscopes. Compared with traditional multi-machine synchronization correction methods, the clock delay analysis of this method is more intuitive and simple, and it provides higher synchronization accuracy. It can accurately eliminate sampling errors caused by clock and trigger inconsistencies, providing users with more accurate and reliable data.

[0036] (2) This sampling synchronous calibration process supports multiple digital oscilloscopes to be connected in series simultaneously, avoiding the cumbersome process of connecting and calibrating each digital oscilloscope in turn, resulting in higher calibration efficiency. Users can also update the calibration data according to the different lengths of the connecting cables, allowing users to expand the number of channels according to actual needs. This feature expands the application range of digital oscilloscopes in high-speed multi-signal testing scenarios, solving the limitations of relatively small number of channels and inconsistent cable lengths, realizing a wider range of signal acquisition and analysis, and meeting the needs of complex experiments or tests.

[0037] (3) The multi-machine synchronization function provides an important foundation for the subsequent development of multi-machine data merging. Users can merge the sampled data from multiple oscilloscopes at intervals, similar to the TIADC solution, to increase the maximum sampling rate of the digital oscilloscope and further improve its acquisition performance. Attached Figure Description

[0038] Figure 1 This is a flowchart of a sampling synchronization correction method for multiple digital oscilloscopes according to the present invention;

[0039] Figure 2 This is a diagram showing the connection of multiple digital oscilloscopes;

[0040] Figure 3 This is the clock circuit structure diagram of the device;

[0041] Figure 4 This is a schematic diagram of the clock signal transmission path delay;

[0042] Figure 5 This is a schematic diagram of the master-slave device sampling clock correction. Detailed Implementation

[0043] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0044] Example

[0045] Figure 1 This is a flowchart of a sampling synchronization correction method for multiple digital oscilloscopes according to the present invention.

[0046] In this embodiment, as Figure 1 As shown, the present invention provides a sampling synchronization correction method for multiple digital oscilloscopes, comprising the following steps:

[0047] S1. Suppose there are M digital oscilloscopes in the system that need to be sampled synchronously. One of the digital oscilloscopes is designated as the master device, and the remaining M-1 digital oscilloscopes are designated as slave devices. Both the master and slave devices are designed with clock interfaces A and B with bidirectional input and output functions, as well as trigger interfaces A and B.

[0048] S2. Connect the clock interface B and trigger interface B of the master device to the clock interface A and trigger interface A of slave device 1 using coaxial cables. Connect the clock interface B and trigger interface B of slave device 1 to the clock interface A and trigger interface A of slave device 2, and so on, connecting M digital oscilloscopes to form a multi-machine serial data acquisition system. The connection method is as follows: Figure 2 As shown;

[0049] S3. Perform the synchronous sampling process between master and slave devices;

[0050] S3.1 The internal circuit design of the master and slave devices is the same. The internal crystal oscillator of the master device provides a 10MHz clock source for the clock chip, and at the same time, it outputs a separate 10MHz synchronous clock signal.

[0051] The S3.2 10MHz synchronous clock signal is transmitted to clock interface B through the FPGA clock programming control circuit in the master device. This interface is connected to the slave device clock interface A via a coaxial cable.

[0052] The S3.3 10MHz synchronous clock signal is transmitted to the slave device's clock circuit via the FPGA clock programming control circuit within the slave device. This circuit consists of a voltage optimization circuit, a phase-locked loop controller, and a voltage-controlled oscillator (VCO). This structure forms a phase-locked loop that continuously adjusts the phase of the slave device's crystal oscillator to make it equal in phase with the 10MHz synchronous clock signal. The adjusted crystal oscillator provides a 10MHz clock source for the slave device's clock chip. The clock circuit design structure diagram and the clock signal transmission path within the slave device under acquisition mode are shown below. Figure 3 As shown;

[0053] S3.4 The master and slave devices generate the sampling clock of the ADC through the same clock chip using their respective clock sources, and start data acquisition. The analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC along the same path.

[0054] S4. Perform the correction process for master-slave device sampling synchronization;

[0055] S4.1 Estimate the clock delay ΔTclk between the master and slave devices;

[0056] S4.1.1, Estimating device connection methods and signal transmission path delays during the process, such as... Figure 4 As shown, the transmission and connection of the master and slave device clock signals remain unchanged. Two coaxial cables of equal length are used to connect the trigger interface B of the master and slave devices to the signal generator. The signal generator can generate a 10MHz test signal and transmit it to the counter inside the device. The FPGA internal routing tool is used to make the distance from the trigger interface B of the master and slave devices to their respective counters equal. The transmission time of the test signal to the counter is recorded as T0.

[0057] S4.1.2. Taking the master crystal oscillator as the reference, the transmission delay time of the clock signal from the master crystal oscillator to the master FIFO is T1, and the transmission delay time to the slave FIFO is T2. The transmission paths from the master and slave crystal oscillators to the sampling ADC are the same, that is, the delay time ΔTclk of the sampling clock of the master and slave devices is equal to the transmission delay time of the synchronous clock signal between the master and slave crystal oscillators.

[0058] S4.1.3 Start the internal counter of the master and slave devices. The master device starts counting when it detects data stored in the FIFO and stops counting after detecting the test signal from the trigger interface B. The counting time of the master device is Tm = T1 - T0 = N1t.

[0059] S4.1.4 The slave device starts counting when it detects data stored in the FIFO and ends counting when it detects a test signal from the trigger interface B. The slave counting time is Ts = T2 - T0 = N2t.

[0060] S4.1.5 According to (4.1.2)~(4.1.4), the delay time ΔTclk of the sampling clock of the master and slave devices is T2-T1=(N2-N1)t;

[0061] S4.2 Master-slave sampling clock skew correction;

[0062] A schematic diagram of master-slave device sampling clock correction is shown below. Figure 5 As shown in the figure, ΔTdata represents the data transmission delay difference. A positive value indicates a greater data transmission delay on the slave device, while a negative value indicates the opposite. Let ΔTclk_min be the phase difference between the most recent rising edges of the master and slave sampling clocks, T be the sampling clock period, and N be the maximum number of complete sampling clock periods contained in ΔTclk, i.e., ΔTclk = ΔTclk_min + NT. To ensure that the sampling points M1 and S1 of the master and slave devices are at the same position of the input signal, the sampling clocks must be adjusted. Considering the data transmission delay, the phase difference ΔT that needs to be corrected between the master and slave sampling clocks is ΔTclk_min - Δtdata. However, the difference between the estimated value and the true value also depends on the device manufacturing process, so the estimation error can be superimposed on ΔTdata.

[0063] The sampling clock phase adjustment can be performed within the HMC7044 clock chip or the ADC. The HMC7044 provides an analog adjustment scheme for the output clock, with an adjustment step of 25ps and a maximum adjustment of 600ps. This design uses the ADC to adjust the clock delay in steps of 1.13ps (maximum 289ps) for coarse adjustment and 19fs (maximum 4.9ps) for fine adjustment. Considering all factors, the ADC's internal adjustment scheme with higher adjustment accuracy is selected to delay the phase difference of the ADC sampling clock of the slave device until the sampling clock phases of the master and slave devices are consistent. At this point, the sampling clock synchronization of the master and slave devices is completed.

[0064] S5, Triggered synchronization between master and slave devices;

[0065] S5.1 Connect the trigger interface B of the master device to the trigger interface A of the slave device 1 using a coaxial cable. Set the trigger source of the master device to its own analog channel mode and the trigger source of the slave device to the external trigger channel mode. Set the master and slave devices to the same trigger depth.

[0066] S5.2 Set the master device trigger conditions. The FPGA of the master device generates FIFO read / write enable signals to control data storage and retrieval based on the trigger conditions.

[0067] S5.2.1 The master device generates the intermediate control signal FIFO_MID together with the FIFO read / write enable signal. The specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high; when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low; otherwise, it remains unchanged.

[0068] S5.2.2 FIFO_MID enters the slave device through the coaxial connection cable of the master-slave device trigger interface. The FPGA of the slave device generates a FIFO read / write enable signal to control the data storage and reading of the slave device based on FIFO_MID. When the FPGA of the slave device detects the rising edge of FIFO_MID, it pulls up the FIFO write enable signal of the slave device. At this time, it starts writing the acquired data to the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth. Then it pulls up the FIFO read enable signal of the slave device. At this time, the FIFO performs both writing and reading operations of the acquired data.

[0069] When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the acquired data into the post-trigger memory area. This continues until the post-trigger memory area is full. Then, the slave device write enable is pulled low and the read enable is pulled high to retrieve the acquired data after it is full for subsequent processing, thus completing the slave device triggering process.

[0070] S5.3 Trigger point offset correction;

[0071] The slave control signal has a certain delay compared to the master control signal, including the deterministic timing delay caused by edge detection and the uncertain delay caused by the transmission path. Since the clock circuit synchronization is designed before the triggering process, the sampling points of the master and slave devices are already synchronized. Therefore, the delay of the slave trigger signal means that the trigger point will enter the FIFO earlier than the trigger signal. This will cause the master and slave device trigger points to deviate and the slave trigger point to shift relative to the normal situation. Therefore, these delays must be corrected to ensure that the master and slave device trigger points are synchronized and appear at the ideal trigger position.

[0072] The FPGA of the device performs delay processing on the acquired data to compensate for the delay of edge detection and transmission path. The timing delay is fixed and known. The timing clock is 320MHz, and the delay brought by each timing is 1 / 320MHz = 3.125ns. The number of timings is two timings for the master to detect one edge and the slave to detect one edge. Therefore, only two timing operations are needed for the slave to acquire data. The uncertain delay caused by the transmission path is adjusted by the IDELAYE2 statement integrated in the FPGA. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position.

[0073] S5.4 Adjust the timing of the control signal FIFO_MID between the master and slave to keep it away from the metastable range of the slave processing clock;

[0074] When the total transmission delay of the slave trigger signal is close to the processing clock cycle, it may not meet the setup and hold time requirements of the slave processing clock, leading to metastability. Once metastability occurs, the signal may only take effect after one or even multiple cycles. This will cause timing disorder of the trigger signal in the acquisition mode, resulting in incorrect read / write control of the FIFO. This will be displayed on the waveform as a different trigger point position each time the power is turned on. To keep the transmitted signal away from the metastable range of the slave processing clock, an appropriate timing delay is required.

[0075] The delay of the control signal FIFO_MID is independently adjusted by calling the FPGA's internal IDELAYE2 resource. The optimal delay value is determined by the following steps: delay the FIFO_MID signal until it is just away from the metastable range, and the data transmission goes from misaligned to aligned as the starting point delay0. Then increase the delay value until the data goes from aligned to misaligned as the ending point delay1. The optimal delay value is (delay0+delay1) / 2. The timing adjustment of the control signal FIFO_MID is completed, and the master-slave device trigger synchronization is completed.

[0076] S6. After the master device and slave device 1 are synchronized, slave device 1 is similar to the master device. It completes the synchronization and calibration process according to steps (3), (4), and (5). Then, the synchronization and calibration of all digital oscilloscopes are completed in the same way.

[0077] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for synchronously correcting the sampling of multiple digital oscilloscopes, characterized in that, Includes the following steps: (1) Assume that there are M digital oscilloscopes in the system that need to be sampled synchronously. One of the digital oscilloscopes is used as the master device, and the remaining M-1 digital oscilloscopes are used as slave devices. Both the master and slave devices are designed with clock interfaces A and B with bidirectional input and output functions, as well as trigger interfaces A and B. (2) Connect the clock interface B and trigger interface B of the master device to the clock interface A and trigger interface A of the slave device 1 respectively using coaxial cable. Connect the clock interface B and trigger interface B of the slave device 1 to the clock interface A and trigger interface A of the slave device 2 respectively. Connect M digital oscilloscopes in this way to form a multi-machine serial data acquisition system. (3) Perform the synchronous sampling process between master and slave devices; (3.1) The internal circuit design of the master and slave devices is the same. The internal crystal oscillator of the master device provides a 10MHz clock source for the clock chip, and at the same time, it outputs a separate 10MHz synchronous clock signal. (3.2) The 10MHz synchronous clock signal is transmitted to the clock interface B through the FPGA clock programming control circuit in the master device. This interface is connected to the slave device clock interface A through a coaxial cable. (3.3) The 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit continuously adjusts the phase of the crystal oscillator of the slave device to make it equal to the phase of the 10MHz synchronous clock signal. The adjusted crystal oscillator provides a 10MHz clock source for the clock chip of the slave device. (3.4) The master and slave devices generate the sampling clock of the ADC through the same clock chip with their own clock source and start data acquisition. The analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC along the same path. (4) Perform the calibration process for master-slave device sampling synchronization; (4.1) Estimate the clock delay ΔT between the master and slave devices. clk ; (4.1.1) The transmission and connection of the master and slave device clock signals remain unchanged. Two coaxial cables of equal length are used to connect the trigger interface B of the master and slave devices to the signal generator. The signal generator can generate a 10MHz test signal and transmit it to the counter inside the device. The FPGA internal routing tool is used to make the distance from the trigger interface B of the master and slave devices to their respective counters equal. The transmission time of the test signal to the counter is recorded as T0. (4.1.2) Taking the master crystal oscillator as the reference, the transmission delay time of the clock signal from the master crystal oscillator to the master FIFO is T1, and the transmission delay time to the slave FIFO is T2. The transmission paths from the master and slave crystal oscillators to the sampling ADC are the same, that is, the delay time ΔT of the sampling clock of the master and slave devices is the same. clk This is equal to the transmission delay time of the synchronous clock signal between the master and slave device crystal oscillators; (4.1.3) Start the internal counter of the master and slave devices. The master device starts counting when it detects the data stored in the FIFO and stops counting after detecting the test signal from the trigger interface B. The counting time of the master device is Tm=T1-T0=N1t. (4.1.4) The slave device starts counting when it detects data stored in the FIFO and ends counting when it detects the test signal from the trigger interface B. The slave counting time is Ts=T2-T0=N2t. (4.1.5) According to (4.1.2)~(4.1.4), the delay time ΔT of the sampling clock of the master and slave devices clk =T2-T1=(N2-N1)t; (4.2) Master-slave sampling clock skew correction; Let ΔT clk_min The phase difference between the most recent rising edges of the master and slave sampling clocks, where T is the sampling clock period and N is ΔT. clk The maximum number of complete sampling clock cycles included, i.e., ΔT clk =ΔT clk_min +NT delays the phase difference of the ADC sampling clock of the slave device until the sampling clock phases of the master and slave devices are consistent, thus completing the sampling clock synchronization of the master and slave devices; (5) Triggering synchronization of master and slave devices; (5.1) Connect the trigger interface B of the master device to the trigger interface A of the slave device 1 using a coaxial cable. Set the trigger source of the master device to its own analog channel mode and the trigger source of the slave device to the external trigger channel mode. Set the master and slave devices to the same trigger depth. (5.2) Set the master device trigger conditions. The FPGA of the master device generates FIFO read / write enable signals to control data storage and reading according to the trigger conditions. (5.2.1) The master device generates the intermediate control signal FIFO_MID together with the FIFO read and write enable signal. The specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high; when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low; otherwise, it remains unchanged. (5.2.2) FIFO_MID enters the slave device through the coaxial connection cable of the master-slave device trigger interface. The FPGA of the slave device generates a FIFO read / write enable signal to control the data storage and reading of the slave device according to FIFO_MID. When the FPGA of the slave device detects the rising edge of FIFO_MID, it pulls up the FIFO write enable signal of the slave device. At this time, it starts to write the acquired data to the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth. Then it pulls up the FIFO read enable signal of the slave device. At this time, the FIFO performs both data writing and reading operations. When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the acquired data into the post-trigger memory area. This continues until the post-trigger memory area is full. Then, the slave device write enable is pulled low and the read enable is pulled high to retrieve the acquired data after it is full for subsequent processing, thus completing the slave device triggering process. (5.3) Trigger point offset correction; The FPGA of the device performs delay processing on the acquired data to compensate for the delay of edge detection and transmission path. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position. (5.4) Adjust the timing of the control signal FIFO_MID between the master and slave to keep it away from the metastable range of the slave processing clock; The delay of the control signal FIFO_MID is independently adjusted by calling the FPGA's internal IDELAYE2 resource. The optimal delay value is determined by the following steps: delay the FIFO_MID signal until it is just away from the metastable range, and the data transmission goes from misaligned to aligned as the starting point delay0. Then increase the delay value until the data goes from aligned to misaligned as the ending point delay1. The optimal delay value is (delay0+delay1) / 2. The timing adjustment of the control signal FIFO_MID is completed, and the master-slave device trigger synchronization is completed. (6) After the master device and slave device 1 are synchronized, slave device 1 has the same function as the master device. Follow steps (3), (4), and (5) to complete the synchronization and calibration process. Then, follow this process to complete the synchronization calibration of all digital oscilloscopes.

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