A bandgap reference circuit with high-order temperature compensation

Abstract

The present invention provides a bandgap reference circuit with high-order temperature compensation, in which a high-order curvature compensation circuit 4 generates a subthreshold leakage current. Under the action of the subthreshold leakage current, the voltages at the source terminals of two transistors in a circuit 1 that generates a current proportional to the temperature are equalized, thereby suppressing changes in Vref. In addition, a bias current is copied to the resistor of the high-order curvature compensation circuit 4 through a current mirror. The characteristic that the gate voltage of the output transistor of the high-order curvature compensation circuit 4 increases linearly with increasing temperature is utilized to adjust the resistance value of the resistor of the high-order curvature compensation circuit 4 itself, so that when the bandgap reference circuit with high-order temperature compensation is operating normally, the output transistor of the high-order curvature compensation circuit 4 is always in the subthreshold region, thereby improving the temperature coefficient of the bandgap reference circuit with high-order temperature compensation.

Description

Technical Field

[0001] The invention belongs to the technical field of power supply circuits, and in particular relates to a bandgap reference circuit with high-order temperature compensation. Background Art

[0002] With the rapid development of integrated circuit technology, bandgap reference circuits have become an indispensable basic circuit module in almost all analog and mixed-analog circuit systems. In the field of integrated circuit design, especially analog circuit design, most circuits require a suitable and stable bias to ensure stable operation in the desired state. The performance characteristics of the circuit directly affect the performance characteristics of the analog and mixed-analog circuit systems. This requires that the bandgap reference be insensitive to changes in power supply voltage, process temperature, and process errors.

[0003] Figure 1 A traditional first-order bandgap reference circuit is given. The emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1. The emitter-base voltage of the PNP transistor Q3 is The band gap uses the current mirror circuit composed of M1~M4 transistors to make the voltage of A and B nodes equal, generating a current flowing through the resistor R1 with a value of The PTAT current, where is the Boltzmann constant, is the absolute temperature, Is the electron charge. Then the reference voltage is output through the current mirror M5 , , where Has a negative temperature coefficient, has a positive temperature coefficient, so it is reasonable to adjust 、 and The size of the bandgap reference voltage with zero temperature coefficient can be obtained within a certain temperature range. .

[0004] However, the voltages at nodes A and B are not completely equal, and there is a mismatch between the current mirrors M1, M2, and M5, and due to the emitter-base voltage of the PNP transistor The temperature nonlinearity makes the first-order bandgap reference voltage have a high temperature coefficient, which restricts the application of the first-order bandgap reference circuit in scenarios such as high-precision systems. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a bandgap reference circuit with high-order temperature compensation.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] The present invention provides a bandgap reference circuit with high-order temperature compensation, comprising: a circuit 1 for generating a current in direct proportion to temperature, a circuit 2 for generating a current in negative proportion to temperature, a reference voltage generating circuit 3, a high-order curvature compensation circuit 4, and an auxiliary circuit 5 for improving the power supply rejection ratio;

[0008] The circuit 1 for generating a current in direct proportion to temperature is used to generate a first proportional current in direct proportion to absolute temperature;

[0009] The circuit 2 for generating a current inversely proportional to the temperature is used to generate a second proportional current inversely proportional to the absolute temperature;

[0010] The reference voltage generating circuit 3 is used to add the voltages generated by the first proportional current and the second proportional current according to a preset ratio to obtain and output a reference voltage with a zero temperature coefficient, so as to reduce the temperature coefficient of the bandgap reference circuit with high-order temperature compensation;

[0011] The high-order curvature compensation circuit 4 is used to generate a subthreshold leakage current. Under the influence of the subthreshold leakage current and the circuit 1 that generates a current proportional to the temperature, the high-order curvature compensation circuit 4 adjusts its own resistance value to keep the bandgap reference circuit with high-order temperature compensation in the subthreshold region, thereby reducing the deviation of the reference voltage within the operating temperature range.

[0012] The auxiliary circuit 5 for improving the power supply rejection ratio adopts a common source and common gate structure to increase the gain, thereby improving the power supply rejection ratio of the bandgap reference circuit with high-order temperature compensation.

[0013] Optionally, the bandgap reference circuit with high-order temperature compensation further includes: a startup circuit 6;

[0014] The startup circuit 6 is used to start the circuit 1 that generates a current that is directly proportional to the temperature and the circuit 2 that generates a current that is negatively proportional to the temperature when power is turned on.

[0015] Optionally, the circuit 1 that generates a current that is directly proportional to the temperature is connected to the startup circuit 6 and the high-order curvature compensation circuit 4; the auxiliary circuit 5 that improves the power supply rejection ratio is connected to the high-order curvature compensation circuit 4 and the reference voltage generating circuit 3; the circuit 2 that generates a current that is negatively proportional to the temperature is connected to the reference voltage generating circuit 3 and the auxiliary circuit 5 that improves the power supply rejection ratio; the reference voltage generating circuit 3 is connected to the circuit 2 that generates a current that is negatively proportional to the temperature.

[0016] Optionally, the startup circuit 6 includes: a first PMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a twenty-first PMOS transistor M21, a twenty-third NMOS transistor M23, a twenty-fourth NMOS transistor M24, a twenty-fifth NMOS transistor M25, and a twenty-sixth NMOS transistor M26;

[0017] Among them, the source of the first PMOS transistor M1, the gate of the second NMOS transistor M2, the gate of the third NMOS transistor M3, the gate of the fourth NMOS transistor M4, the gate of the fifth NMOS transistor M5, the source of the twenty-first PMOS transistor M21, the gate of the twenty-third NMOS transistor M23, the gate of the twenty-fourth NMOS transistor M24, the gate of the twenty-fifth NMOS transistor M25, and the gate of the twenty-sixth NMOS transistor M26 are connected to the external power supply VDD, the source of the second NMOS transistor M2 is connected to the drain of the third NMOS transistor M3, and the gate of the third NMOS transistor The source of the transistor M3 is connected to the drain of the fourth NMOS transistor M4, the source of the fourth NMOS transistor M4 is connected to the drain of the fifth NMOS transistor M5, the source of the fifth NMOS transistor M5 is connected to the external ground line GND, the source of the twenty-third NMOS transistor M23 is connected to the drain of the twenty-fourth NMOS transistor M24, the source of the twenty-fourth NMOS transistor M24 is connected to the drain of the twenty-fifth NMOS transistor M25, the source of the twenty-fifth NMOS transistor M25 is connected to the drain of the twenty-sixth NMOS transistor M26, and the source of the twenty-sixth NMOS transistor M26 is connected to the external ground line GND.

[0018] Optionally, the circuit 1 for generating a current proportional to the temperature includes: a sixth PMOS transistor M6, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a twelfth NMOS transistor M12, a third resistor R3, a first PNP transistor Q1, a second PNP transistor Q2, and a third PNP transistor Q3;

[0019] In the circuit 1 for generating a current proportional to temperature, the source of the sixth PMOS transistor M6 is connected to the source of the ninth PMOS transistor M9, the source of the tenth PMOS transistor M10, the source of the eleventh PMOS transistor M11, and the external power supply VDD; the drain of the sixth PMOS transistor M6 is connected to the drain of the seventh NMOS transistor M7, the gate of the seventh NMOS transistor M7, the gate of the eighth NMOS transistor M8, the drain of the eleventh PMOS transistor M11, and the gate of the twelfth NMOS transistor M12; the source of the seventh NMOS transistor M7 is connected to the emitter of the first PNP transistor Q1, and the eighth NMOS transistor M8 is connected to the emitter of the first PNP transistor Q2. The source of the transistor M8 is connected to the emitter of the second PNP transistor Q2, the collector and base of the first PNP transistor Q1, the collector and base of the second PNP transistor Q2, the collector and base of the third PNP transistor Q3, and the external ground GND are connected; the gate and drain of the ninth PMOS transistor M9 are connected to the gate of the tenth PMOS transistor M10, the drain of the tenth PMOS transistor M10, the gate of the eleventh PMOS transistor M11, and the drain of the twelfth NMOS transistor M12 are connected; a first end of the third resistor R3 is connected to the source of the twelfth NMOS transistor M12, and a second end is connected to the emitter of the third PNP transistor Q3.

[0020] Optionally, the circuit 2 for generating a current in negative proportion to the temperature includes: a twenty-second PMOS transistor M22, a thirty-first PMOS transistor M31, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth NMOS transistor M29, and a thirtieth NMOS transistor M30;

[0021] The source of the twenty-second PMOS transistor M22, the source of the thirty-first PMOS transistor M31, and the source of the twenty-seventh PMOS transistor M27 are connected to the external power supply VDD, the gate of the twenty-second PMOS transistor M22, the gate and drain of the thirty-first PMOS transistor M31, and the drain of the twenty-eighth NMOS transistor M28 are connected to the gate of the twenty-first PMOS transistor M21, the drain of the twenty-second PMOS transistor M22, the gate and drain of the twenty-ninth NMOS transistor M29, and the drain of the twenty-seventh PMOS transistor M27 are connected to the gate of the twenty-eighth NMOS transistor M28, the source of the twenty-eighth NMOS transistor M28 is connected to the drain of the thirtieth NMOS transistor M30, the gate of the thirtieth NMOS transistor M30 is connected to the output reference voltage Vref, and the source of the twenty-ninth NMOS transistor M29, the source of the thirtieth NMOS transistor M30, and the external ground line GND are connected.

[0022] Optionally, the reference voltage generating circuit 3 includes: a thirty-second PMOS transistor M32, a fourth PNP transistor Q4, and a fifth resistor R5;

[0023] Among them, the source of the thirty-second PMOS transistor M32 is connected to the external power supply VDD, the gate and drain of the thirty-second PMOS transistor M32, the emitter of the fourth PNP transistor Q4, and one end of the fifth resistor R5 are connected to the gate of the thirty-first PMOS transistor M31, the other end of the fifth resistor R5 is connected to the output reference voltage Vref, and the collector and base of the fourth PNP transistor Q4 are connected to the external ground line GND.

[0024] Optionally, the high-order curvature compensation circuit 4 includes: a thirteenth PMOS transistor M13, a twentieth NMOS transistor M20, a first resistor R1 and a second resistor R2;

[0025] Among them, the source of the thirteenth PMOS transistor M13 is connected to the external power supply VDD, one end of the first resistor R1 is connected to the drain of the thirteenth PMOS transistor M13, and the other end is connected to the gate of the twentieth NMOS transistor M20 and one end of the second resistor R2, and the other end of the second resistor R2 and the source of the twentieth NMOS transistor M20 are connected to the external ground line GND.

[0026] Optionally, the auxiliary circuit 5 for improving the power supply rejection ratio includes: a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, and a fourth resistor R4;

[0027] Among them, the gate of the fourteenth PMOS transistor M14 is connected to the gate of the fifteenth PMOS transistor M15, the source of the fourteenth PMOS transistor M14, the source of the fifteenth PMOS transistor M15, and the source of the sixteenth PMOS transistor M16 are connected to the external power supply VDD, the drain of the fourteenth PMOS transistor M14, the gate and drain of the eighteenth NMOS transistor M18 are connected to the gate of the nineteenth NMOS transistor M19, the gate of the seventeenth PMOS transistor M17 is connected to the drain of the nineteenth NMOS transistor M19, the drain of the fifteenth PMOS transistor M15, the gate of the sixteenth PMOS transistor M16 are connected to the source of the seventeenth PMOS transistor M17, the source of the eighteenth NMOS transistor M18 and the source of the nineteenth NMOS transistor M19 are connected to the external ground line GND, the drain of the seventeenth PMOS transistor M17 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the output reference voltage Vref.

[0028] The present invention provides a bandgap reference circuit with high-order temperature compensation, comprising: a circuit 1 for generating a current in direct proportion to temperature, a circuit 2 for generating a current in inverse proportion to temperature, a reference voltage generating circuit 3, a high-order curvature compensation circuit 4, and an auxiliary circuit 5 for improving the power supply rejection ratio; the circuit 1 for generating a current in direct proportion to temperature is used to generate a first proportional current in direct proportion to absolute temperature; the circuit 2 for generating a current in inverse proportion to temperature is used to generate a second proportional current in inverse proportion to absolute temperature; the reference voltage generating circuit 3 is used to convert the voltage generated by the first proportional current and the second proportional current into a voltage in a preset ratio. The high-order curvature compensation circuit 4 generates a subthreshold leakage current, and under the action of the subthreshold leakage current and the circuit 1 that generates a current that is proportional to the temperature, the high-order curvature compensation circuit 4 adjusts its own resistance value to keep the bandgap reference circuit with high-order temperature compensation in the subthreshold region, thereby reducing the deviation of the reference voltage within the operating temperature range; the auxiliary circuit 5 for improving the power supply rejection ratio adopts a common source and common gate structure to increase the gain, thereby improving the power supply rejection ratio of the bandgap reference circuit with high-order temperature compensation. In the present invention, a high-order curvature compensation circuit 4 generates a subthreshold leakage current. This subthreshold leakage current equalizes the voltages at the source terminals of two transistors in circuit 1, which generates a current proportional to temperature, thereby suppressing variations in Vref. Furthermore, a bias current is copied to the resistor of the high-order curvature compensation circuit 4 via a current mirror. By utilizing the characteristic that the gate voltage of the output transistor of the high-order curvature compensation circuit 4 increases linearly with increasing temperature, the resistance of the resistor of the high-order curvature compensation circuit 4 is adjusted, ensuring that the output transistor of the high-order curvature compensation circuit 4 remains in the subthreshold region during normal operation of the bandgap reference circuit with high-order temperature compensation. Due to the presence of a weak inversion layer, the leakage current is non-zero. Therefore, a current with a partial negative temperature coefficient is injected into the transistors in the reference voltage generation circuit 3 to improve the temperature coefficient of the bandgap reference circuit with high-order temperature compensation. Furthermore, an adjustable cascode technique is employed, which increases the gain from the input to the output while maintaining the gain from the power supply to the output constant, thereby improving the power supply rejection ratio (PSRR).

[0029] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is the circuit diagram of a traditional first-order bandgap reference circuit;

[0031] Figure 2 A circuit diagram of a bandgap reference circuit with high-order temperature compensation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0033] In order to solve the problem that the first-order bandgap reference voltage has a high temperature coefficient in the prior art, the reference Figure 2 The embodiment of the present invention provides a bandgap reference circuit with high-order temperature compensation, comprising: a circuit 1 for generating a current that is directly proportional to temperature, a circuit 2 for generating a current that is negatively proportional to temperature, a reference voltage generating circuit 3, a high-order curvature compensation circuit 4, and an auxiliary circuit 5 for improving the power supply rejection ratio;

[0034] The circuit 1 for generating a current proportional to temperature is used to generate a first proportional current proportional to the absolute temperature;

[0035] The circuit 2 for generating a current inversely proportional to the temperature is used to generate a second proportional current inversely proportional to the absolute temperature;

[0036] The reference voltage generating circuit 3 is used to add the voltages generated by the first proportional current and the second proportional current according to a preset ratio to obtain and output a reference voltage with a zero temperature coefficient, thereby reducing the temperature coefficient of the bandgap reference circuit with high-order temperature compensation;

[0037] The high-order curvature compensation circuit 4 is used to generate a subthreshold leakage current. Under the influence of the subthreshold leakage current and the circuit 1 that generates a current proportional to the temperature, the high-order curvature compensation circuit 4 adjusts its own resistance value to keep the bandgap reference circuit with high-order temperature compensation in the subthreshold region, thereby reducing the deviation of the reference voltage within the operating temperature range.

[0038] The auxiliary circuit 5 for improving the power supply rejection ratio adopts a common source and common gate structure to increase the gain, thereby improving the power supply rejection ratio of the bandgap reference circuit with high-order temperature compensation.

[0039] The present invention provides a bandgap reference circuit with high-order temperature compensation, comprising: a circuit 1 for generating a current in direct proportion to temperature, a circuit 2 for generating a current in inverse proportion to temperature, a reference voltage generating circuit 3, a high-order curvature compensation circuit 4, and an auxiliary circuit 5 for improving the power supply rejection ratio; the circuit 1 for generating a current in direct proportion to temperature is used to generate a first proportional current in direct proportion to absolute temperature; the circuit 2 for generating a current in inverse proportion to temperature is used to generate a second proportional current in inverse proportion to absolute temperature; the reference voltage generating circuit 3 is used to convert the voltage generated by the first proportional current and the second proportional current into a voltage in a preset ratio. The high-order curvature compensation circuit 4 generates a subthreshold leakage current, and under the action of the subthreshold leakage current and the circuit 1 that generates a current that is proportional to the temperature, the high-order curvature compensation circuit 4 adjusts its own resistance value to keep the bandgap reference circuit with high-order temperature compensation in the subthreshold region, thereby reducing the deviation of the reference voltage within the operating temperature range; the auxiliary circuit 5 for improving the power supply rejection ratio adopts a common source and common gate structure to increase the gain, thereby improving the power supply rejection ratio of the bandgap reference circuit with high-order temperature compensation. In the present invention, a high-order curvature compensation circuit 4 generates a subthreshold leakage current. This subthreshold leakage current equalizes the voltages at the source terminals of two transistors in circuit 1, which generates a current proportional to temperature, thereby suppressing variations in Vref. Furthermore, a bias current is copied to the resistor of the high-order curvature compensation circuit 4 via a current mirror. By utilizing the characteristic that the gate voltage of the output transistor of the high-order curvature compensation circuit 4 increases linearly with increasing temperature, the resistance of the resistor of the high-order curvature compensation circuit 4 is adjusted, ensuring that the output transistor of the high-order curvature compensation circuit 4 remains in the subthreshold region during normal operation of the bandgap reference circuit with high-order temperature compensation. Due to the presence of a weak inversion layer, the leakage current is non-zero. Therefore, a current with a partial negative temperature coefficient is injected into the transistors in the reference voltage generation circuit 3 to improve the temperature coefficient of the bandgap reference circuit with high-order temperature compensation. Furthermore, an adjustable cascode technique is employed, which increases the gain from the input to the output while maintaining the gain from the power supply to the output constant, thereby improving the power supply rejection ratio (PSRR).

[0040] Optionally, the bandgap reference circuit with high-order temperature compensation further includes: a startup circuit 6; the startup circuit 6 is used to start the circuit 1 that generates a current that is directly proportional to the temperature and the circuit 2 that generates a current that is negatively proportional to the temperature when powered on.

[0041] In this embodiment of the present invention, startup circuit 6 provides a startup function after power-on, preventing the MOS transistor from being in the off state after power-on, enabling the normal operation of the bandgap reference circuit with high-order temperature compensation. By adding a regulated cascode structure, the circuit gain is effectively increased, improving the power supply rejection ratio (PSRR).

[0042] Optionally, the circuit 1 that generates a current that is directly proportional to the temperature is connected to the startup circuit 6 and the high-order curvature compensation circuit 4; the auxiliary circuit 5 that improves the power supply rejection ratio is connected to the high-order curvature compensation circuit 4 and the reference voltage generating circuit 3; the circuit 2 that generates a current that is negatively proportional to the temperature is connected to the reference voltage generating circuit 3 and the auxiliary circuit 5 that improves the power supply rejection ratio; the reference voltage generating circuit 3 is connected to the circuit 2 that generates a current that is negatively proportional to the temperature.

[0043] Optionally, the startup circuit 6 includes: a first PMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a twenty-first PMOS transistor M21, a twenty-third NMOS transistor M23, a twenty-fourth NMOS transistor M24, a twenty-fifth NMOS transistor M25, and a twenty-sixth NMOS transistor M26;

[0044] Among them, the source of the first PMOS transistor M1, the gate of the second NMOS transistor M2, the gate of the third NMOS transistor M3, the gate of the fourth NMOS transistor M4, the gate of the fifth NMOS transistor M5, the source of the twenty-first PMOS transistor M21, the gate of the twenty-third NMOS transistor M23, the gate of the twenty-fourth NMOS transistor M24, the gate of the twenty-fifth NMOS transistor M25, and the gate of the twenty-sixth NMOS transistor M26 are connected to the external power supply VDD, the source of the second NMOS transistor M2 is connected to the drain of the third NMOS transistor M3, and the gate of the third NMOS transistor The source of the transistor M3 is connected to the drain of the fourth NMOS transistor M4, the source of the fourth NMOS transistor M4 is connected to the drain of the fifth NMOS transistor M5, the source of the fifth NMOS transistor M5 is connected to the external ground line GND, the source of the twenty-third NMOS transistor M23 is connected to the drain of the twenty-fourth NMOS transistor M24, the source of the twenty-fourth NMOS transistor M24 is connected to the drain of the twenty-fifth NMOS transistor M25, the source of the twenty-fifth NMOS transistor M25 is connected to the drain of the twenty-sixth NMOS transistor M26, and the source of the twenty-sixth NMOS transistor M26 is connected to the external ground line GND.

[0045] Optionally, the circuit 1 for generating a current proportional to temperature includes: a sixth PMOS transistor M6, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a twelfth NMOS transistor M12, a third resistor R3, a first PNP transistor Q1, a second PNP transistor Q2, and a third PNP transistor Q3;

[0046] In the circuit 1 for generating a current proportional to temperature, the source of the sixth PMOS transistor M6 is connected to the source of the ninth PMOS transistor M9, the source of the tenth PMOS transistor M10, the source of the eleventh PMOS transistor M11, and the external power supply VDD; the drain of the sixth PMOS transistor M6 is connected to the drain of the seventh NMOS transistor M7, the gate of the seventh NMOS transistor M7, the gate of the eighth NMOS transistor M8, the drain of the eleventh PMOS transistor M11, and the gate of the twelfth NMOS transistor M12; the source of the seventh NMOS transistor M7 is connected to the emitter of the first PNP transistor Q1, and the eighth NMOS transistor M8 is connected to the emitter of the first PNP transistor Q2. The source of the transistor M8 is connected to the emitter of the second PNP transistor Q2, the collector and base of the first PNP transistor Q1, the collector and base of the second PNP transistor Q2, the collector and base of the third PNP transistor Q3, and the external ground GND are connected; the gate and drain of the ninth PMOS transistor M9 are connected to the gate of the tenth PMOS transistor M10, the drain of the tenth PMOS transistor M10, the gate of the eleventh PMOS transistor M11, and the drain of the twelfth NMOS transistor M12 are connected; a first end of the third resistor R3 is connected to the source of the twelfth NMOS transistor M12, and a second end is connected to the emitter of the third PNP transistor Q3.

[0047] Optionally, the circuit 2 for generating a current in negative proportion to the temperature includes: a twenty-second PMOS transistor M22, a thirty-first PMOS transistor M31, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth NMOS transistor M29, and a thirtieth NMOS transistor M30;

[0048] The source of the twenty-second PMOS transistor M22, the source of the thirty-first PMOS transistor M31, and the source of the twenty-seventh PMOS transistor M27 are connected to the external power supply VDD, the gate of the twenty-second PMOS transistor M22, the gate and drain of the thirty-first PMOS transistor M31, and the drain of the twenty-eighth NMOS transistor M28 are connected to the gate of the twenty-first PMOS transistor M21, the drain of the twenty-second PMOS transistor M22, the gate and drain of the twenty-ninth NMOS transistor M29, and the drain of the twenty-seventh PMOS transistor M27 are connected to the gate of the twenty-eighth NMOS transistor M28, the source of the twenty-eighth NMOS transistor M28 is connected to the drain of the thirtieth NMOS transistor M30, the gate of the thirtieth NMOS transistor M30 is connected to the output reference voltage Vref, and the source of the twenty-ninth NMOS transistor M29, the source of the thirtieth NMOS transistor M30, and the external ground line GND are connected.

[0049] Optionally, the reference voltage generating circuit 3 includes: a thirty-second PMOS transistor M32, a fourth PNP transistor Q4, and a fifth resistor R5;

[0050] Among them, the source of the thirty-second PMOS transistor M32 is connected to the external power supply VDD, the gate and drain of the thirty-second PMOS transistor M32, the emitter of the fourth PNP transistor Q4, and one end of the fifth resistor R5 are connected to the gate of the thirty-first PMOS transistor M31, the other end of the fifth resistor R5 is connected to the output reference voltage Vref, and the collector and base of the fourth PNP transistor Q4 are connected to the external ground line GND.

[0051] Optionally, the high-order curvature compensation circuit 4 includes: a thirteenth PMOS transistor M13, a twentieth NMOS transistor M20, a first resistor R1 and a second resistor R2;

[0052] Among them, the source of the thirteenth PMOS transistor M13 is connected to the external power supply VDD, one end of the first resistor R1 is connected to the drain of the thirteenth PMOS transistor M13, and the other end is connected to the gate of the twentieth NMOS transistor M20 and one end of the second resistor R2, and the other end of the second resistor R2 and the source of the twentieth NMOS transistor M20 are connected to the external ground line GND.

[0053] Optionally, the auxiliary circuit 5 for improving the power supply rejection ratio includes: a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, and a fourth resistor R4;

[0054] Among them, the gate of the fourteenth PMOS transistor M14 is connected to the gate of the fifteenth PMOS transistor M15, the source of the fourteenth PMOS transistor M14, the source of the fifteenth PMOS transistor M15, and the source of the sixteenth PMOS transistor M16 are connected to the external power supply VDD, the drain of the fourteenth PMOS transistor M14, the gate and drain of the eighteenth NMOS transistor M18 are connected to the gate of the nineteenth NMOS transistor M19, the gate of the seventeenth PMOS transistor M17 is connected to the drain of the nineteenth NMOS transistor M19, the drain of the fifteenth PMOS transistor M15, the gate of the sixteenth PMOS transistor M16 are connected to the source of the seventeenth PMOS transistor M17, the source of the eighteenth NMOS transistor M18 and the source of the nineteenth NMOS transistor M19 are connected to the external ground line GND, the drain of the seventeenth PMOS transistor M17 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the output reference voltage Vref.

[0055] Figure 2 The circuit diagram of the bandgap reference circuit with high-order temperature compensation provided by the embodiment of the present invention. In this embodiment, reference Figure 2 The working principle of the bandgap reference circuit with high-order temperature compensation is explained in detail:

[0056] The high-order curvature compensation circuit 4 generates a PTAT current and uses a current mirror circuit composed of transistors M8, M9, M10, and M12 to make the voltages at the source terminals of M8 and M12 equal, generating a current flowing through the resistor R3 of size The PTAT current is , are the base-emitter voltages of bipolar transistors Q1 and Q2, respectively. Furthermore, the curvature compensation circuit of the bandgap reference circuit consists of M13, M20, R1, and R2. The PTAT current generated by the bandgap reference circuit is copied to resistors R1 and R2 via the current mirror M13. The gate voltage of M20 increases linearly with increasing temperature. By adjusting the resistance values ​​of R1 and R2, M20 is always in the subthreshold region when the circuit is operating normally. Due to the presence of the weak inversion layer, the leakage current is not zero, the drain current of M20 under subthreshold conditions is:

[0057]

[0058] In the above formula is with proportional to the fixed current value, Indicates the width-to-length ratio of the current MOS tube (M20). is the current gate-source voltage of the MOS tube, is a non-ideal constant, Positive temperature coefficient.

[0059] Finally, the output reference voltage Vref is 1.25V, and its expression is:

[0060]

[0061] In the above formula 、 and are the base-emitter voltages of transistors Q2, Q3, and Q4, respectively; k is the Boltzmann constant; T is the temperature; q is the electron charge; is the saturation current of transistor Q4, is the PTAT current generated by the bandgap reference circuit, N is the ratio of the number of transistors Q3 to Q2, To adjust the current, the purpose is to improve The temperature coefficient of the transistor Q4 is improved by injecting a current with a negative temperature coefficient. .

[0062] Bandgap reference circuits with high-order temperature compensation need to improve their ability to suppress power supply noise, which requires improving the power supply rejection ratio (PSRR), which is the ratio of the gain from input to output to the gain from power supply to output. , where is the gain from input to output, is the power supply to output gain. To improve the reference core's power supply rejection ratio (PSRR), the present invention employs a regulated cascode technique. This significantly increases the circuit's gain despite increasing the output impedance (Rout). This increases the input-to-output gain while maintaining a constant power supply to output gain, thereby improving the PSRR.

[0063] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0064] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0065] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0066] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A bandgap reference circuit with high-order temperature compensation, characterized in that: include: A circuit for generating a current that is directly proportional to temperature (1), a circuit for generating a current that is negatively proportional to temperature (2), a reference voltage generating circuit (3), a high-order curvature compensation circuit (4), and an auxiliary circuit for improving power supply rejection ratio (5); The circuit (1) for generating a current in direct proportion to temperature is used to generate a first proportional current in direct proportion to absolute temperature; The circuit (2) for generating a current in negative proportion to the temperature is used to generate a second proportional current in inverse proportion to the absolute temperature; The reference voltage generating circuit (3) is used to add the voltages generated by the first proportional current and the second proportional current according to a preset ratio, obtain a reference voltage with a zero temperature coefficient and output it, so as to reduce the temperature coefficient of the bandgap reference circuit with high-order temperature compensation; The high-order curvature compensation circuit (4) is used to generate a subthreshold leakage current, and under the action of the subthreshold leakage current and the circuit (1) that generates a current that is proportional to the temperature, the circuit adjusts its own resistance value to keep the bandgap reference circuit with high-order temperature compensation in the subthreshold region, thereby reducing the deviation value of the reference voltage within the operating temperature range; The auxiliary circuit (5) for improving the power supply rejection ratio adopts a common source and common gate structure to increase the gain, thereby improving the power supply rejection ratio of the bandgap reference circuit with high-order temperature compensation.

2. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The bandgap reference circuit with high-order temperature compensation further includes: a startup circuit (6); The startup circuit (6) is used to start the circuit (1) that generates a current in direct proportion to the temperature and the circuit (2) that generates a current in negative proportion to the temperature when power is turned on.

3. The bandgap reference circuit with high-order temperature compensation according to claim 2, wherein: The circuit (1) for generating a current that is directly proportional to the temperature is connected to the startup circuit (6) and the high-order curvature compensation circuit (4); the auxiliary circuit (5) for improving the power supply rejection ratio is connected to the high-order curvature compensation circuit (4) and the reference voltage generating circuit (3); the circuit (2) for generating a current that is negatively proportional to the temperature is connected to the reference voltage generating circuit (3) and the auxiliary circuit (5) for improving the power supply rejection ratio; the reference voltage generating circuit (3) is connected to the circuit (2) for generating a current that is negatively proportional to the temperature.

4. The bandgap reference circuit with high-order temperature compensation according to claim 2, wherein: The startup circuit (6) includes: a first PMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a fourth NMOS transistor (M4), a fifth NMOS transistor (M5), a twenty-first PMOS transistor (M21), a twenty-third NMOS transistor (M23), a twenty-fourth NMOS transistor (M24), a twenty-fifth NMOS transistor (M25), and a twenty-sixth NMOS transistor (M26); Among them, the source of the first PMOS transistor (M1), the gate of the second NMOS transistor (M2), the gate of the third NMOS transistor (M3), the gate of the fourth NMOS transistor (M4), the gate of the fifth NMOS transistor (M5), the source of the twenty-first PMOS transistor (M21), the gate of the twenty-third NMOS transistor (M23), the gate of the twenty-fourth NMOS transistor (M24), the gate of the twenty-fifth NMOS transistor (M25), and the gate of the twenty-sixth NMOS transistor (M26) are connected to the external power supply (VDD), the source of the second NMOS transistor (M2) is connected to the drain of the third NMOS transistor (M3), and the gate of the third NMOS transistor (M4) is connected to the drain of the third NMOS transistor (M4). The source of the second NMOS transistor (M3) is connected to the drain of the fourth NMOS transistor (M4), the source of the fourth NMOS transistor (M4) is connected to the drain of the fifth NMOS transistor (M5), the source of the fifth NMOS transistor (M5) is connected to the external ground line (GND), the source of the twenty-third NMOS transistor (M23) is connected to the drain of the twenty-fourth NMOS transistor (M24), the source of the twenty-fourth NMOS transistor (M24) is connected to the drain of the twenty-fifth NMOS transistor (M25), the source of the twenty-fifth NMOS transistor (M25) is connected to the drain of the twenty-sixth NMOS transistor (M26), and the source of the twenty-sixth NMOS transistor (M26) is connected to the external ground line (GND).

5. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The circuit (1) for generating a current in direct proportion to temperature comprises: a sixth PMOS transistor (M6), a ninth PMOS transistor (M9), a tenth PMOS transistor (M10), an eleventh PMOS transistor (M11), a seventh NMOS transistor (M7), an eighth NMOS transistor (M8), a twelfth NMOS transistor (M12), a third resistor (R3), a first PNP transistor (Q1), a second PNP transistor (Q2), and a third PNP transistor (Q3); In the circuit (1) for generating a current in direct proportion to temperature, the source of the sixth PMOS transistor (M6) is connected to the source of the ninth PMOS transistor (M9), the source of the tenth PMOS transistor (M10), the source of the eleventh PMOS transistor (M11) and the external power supply (VDD); the drain of the sixth PMOS transistor (M6) is connected to the drain of the seventh NMOS transistor (M7), the gate of the seventh NMOS transistor (M7), the gate of the eighth NMOS transistor (M8), the drain of the eleventh PMOS transistor (M11) and the gate of the twelfth NMOS transistor (M12); the source of the seventh NMOS transistor (M7) is connected to the emitter of the first PNP transistor (Q1), the gate of the eighth NMOS transistor (M8) is connected to the emitter of the eighth NMOS transistor (M9). The source of the transistor (M8) is connected to the emitter of the second PNP transistor (Q2), the collector and base of the first PNP transistor (Q1), the collector and base of the second PNP transistor (Q2), the collector and base of the third PNP transistor (Q3) and an external ground (GND) are connected, the gate and drain of the ninth PMOS transistor (M9) are connected to the gate of the tenth PMOS transistor (M10), the drain of the tenth PMOS transistor (M10), the gate of the eleventh PMOS transistor (M11) and the drain of the twelfth NMOS transistor (M12) are connected, and the first end of the third resistor (R3) is connected to the source of the twelfth NMOS transistor (M12), and the second end is connected to the emitter of the third PNP transistor (Q3).

6. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The circuit (2) for generating a current in negative proportion to temperature comprises: a twenty-second PMOS transistor (M22), a thirty-first PMOS transistor (M31), a twenty-seventh PMOS transistor (M27), a twenty-eighth NMOS transistor (M28), a twenty-ninth NMOS transistor (M29) and a thirtieth NMOS transistor (M30); The source of the twenty-second PMOS transistor (M22), the source of the thirty-first PMOS transistor (M31), and the source of the twenty-seventh PMOS transistor (M27) are connected to the external power supply (VDD), the gate of the twenty-second PMOS transistor (M22), the gate and drain of the thirty-first PMOS transistor (M31), and the drain of the twenty-eighth NMOS transistor (M28) are connected to the gate of the twenty-first PMOS transistor (M21), and the drain of the twenty-second PMOS transistor (M22), the gate and drain of the twenty-ninth NMOS transistor (M31) are connected to the gate of the twenty-first PMOS transistor (M21). The gate and drain of the S transistor (M29), the drain of the twenty-seventh PMOS transistor (M27) and the gate of the twenty-eighth NMOS transistor (M28) are connected, the source of the twenty-eighth NMOS transistor (M28) is connected to the drain of the thirtieth NMOS transistor (M30), the gate of the thirtieth NMOS transistor (M30) is connected to the output reference voltage (Vref), and the source of the twenty-ninth NMOS transistor (M29), the source of the thirtieth NMOS transistor (M30) and the external ground (GND) are connected.

7. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The reference voltage generating circuit (3) comprises: a thirty-second PMOS transistor (M32), a fourth PNP transistor (Q4), and a fifth resistor (R5); The source of the thirty-second PMOS transistor (M32) is connected to an external power supply (VDD), the gate and drain of the thirty-second PMOS transistor (M32), the emitter of the fourth PNP transistor (Q4), and one end of the fifth resistor (R5) are connected to the gate of the thirty-first PMOS transistor (M31), the other end of the fifth resistor (R5) is connected to an output reference voltage (Vref), and the collector and base of the fourth PNP transistor (Q4) are connected to an external ground line (GND).

8. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The high-order curvature compensation circuit (4) comprises: a thirteenth PMOS transistor (M13), a twentieth NMOS transistor (M20), a first resistor (R1) and a second resistor (R2); The source of the thirteenth PMOS transistor (M13) is connected to the external power supply (VDD), one end of the first resistor (R1) is connected to the drain of the thirteenth PMOS transistor (M13), and the other end is connected to the gate of the twentieth NMOS transistor (M20) and one end of the second resistor (R2), and the other end of the second resistor (R2) and the source of the twentieth NMOS transistor (M20) are connected to the external ground (GND).

9. The bandgap reference circuit with high-order temperature compensation according to claim 1, wherein: The auxiliary circuit (5) for improving the power supply rejection ratio comprises: a fourteenth PMOS transistor (M14), a fifteenth PMOS transistor (M15), a sixteenth PMOS transistor (M16), a seventeenth PMOS transistor (M17), an eighteenth NMOS transistor (M18), a nineteenth NMOS transistor (M19) and a fourth resistor (R4); The gate of the fourteenth PMOS transistor (M14) is connected to the gate of the fifteenth PMOS transistor (M15), the source of the fourteenth PMOS transistor (M14), the source of the fifteenth PMOS transistor (M15), and the source of the sixteenth PMOS transistor (M16) are connected to the external power supply (VDD), the drain of the fourteenth PMOS transistor (M14), the gate and drain of the eighteenth NMOS transistor (M18) are connected to the gate of the nineteenth NMOS transistor (M19), and the gate of the seventeenth PMOS transistor (M17) is connected to the gate of the seventeenth PMOS transistor (M17). The gate of the first PMOS transistor (M15) and the drain of the second PMOS transistor (M16) are connected to the drain of the ninth NMOS transistor (M19), the drain of the first PMOS transistor (M15) and the gate of the sixth PMOS transistor (M16) are connected to the source of the seventh PMOS transistor (M17), the source of the eighth NMOS transistor (M18) and the source of the ninth NMOS transistor (M19) are connected to the external ground line (GND), the drain of the seventh PMOS transistor (M17) is connected to one end of the fourth resistor (R4), and the other end of the fourth resistor (R4) is connected to the output reference voltage (Vref).

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