Pixel driving circuit and its driving method, display device

Abstract

A pixel driving circuit and its driving method, and a display device, wherein the pixel driving circuit is configured to drive a light-emitting element to emit light, comprising: a node control sub-circuit configured to provide an initial signal to a first node under the control of a reset signal terminal, and to provide an initial signal to a fourth node under the control of a second control terminal, and to provide a second node signal to the first node and a data signal to a third node under the control of a scan signal terminal, and to adjust the signal of the first node or the second node under the control of the first control terminal; a driving sub-circuit configured to provide a driving current to the second node under the control of the first node and the third node; and an emission control sub-circuit configured to provide a first power supply signal to the third node and a second node signal to the fourth node under the control of the emission control terminal; wherein, during the data writing stage and the emission stage, the signals of the scan signal terminal and the first control terminal are inverted signals.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit and a driving method thereof, and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, the flexible display with OLED or QLED as light-emitting device and controlled by Thin Film Transistor (TFT) has become the mainstream product in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light-emitting element to emit light, comprising a node control sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit; the working process of the pixel driving circuit comprises an initialization stage, a data writing stage and a light-emitting stage;

[0005] The node control sub-circuit is electrically connected with a first power supply end, a reset signal end, an initial signal end, a first control end, a second control end, a scanning signal end, a data signal end, a first node, a second node, a third node and a fourth node respectively, and is configured to provide the signal of the initial signal end to the first node under the control of the reset signal end, provide the signal of the initial signal end to the fourth node under the control of the second control end, provide the signal of the second node to the first node and the signal of the data signal end to the third node under the control of the scanning signal end, and adjust the signal of the first node or the second node under the control of the first control end;

[0006] The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide a driving current to the second node under the control of the first node and the third node;

[0007] The light-emitting control sub-circuit is electrically connected with a light-emitting control end, a first power supply end, a second node, a third node and a fourth node respectively, and is configured to provide the signal of the first power supply end to the third node and the signal of the second node to the fourth node under the control of the light-emitting control end.

[0008] The light emitting element is electrically connected with the fourth node and the second power supply terminal, respectively;

[0009] In the data writing stage and the light emitting stage, the signals of the scan signal terminal and the first control terminal are inverse signals of each other.

[0010] In some possible implementation manners, the node control sub-circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a writing sub-circuit and an energy storage sub-circuit.

[0011] The first reset sub-circuit is electrically connected with the reset signal terminal, the initial signal terminal and the first node, respectively, and is configured to provide the signal of the initial signal terminal to the first node under the control of the reset signal terminal.

[0012] The second reset sub-circuit is electrically connected with the second control terminal, the initial signal terminal and the fourth node, respectively, and is configured to provide the signal of the initial signal terminal to the fourth node under the control of the second control terminal.

[0013] The compensation sub-circuit is electrically connected with the first control terminal, the scan signal terminal, the first node and the second node, respectively, and is configured to provide the signal of the second node to the first node under the control of the scan signal terminal, and adjust the signals of the first node or the second node under the control of the first control terminal.

[0014] The writing sub-circuit is electrically connected with the scan signal terminal, the data signal terminal and the third node, respectively, and is configured to provide the signal of the data signal terminal to the third node under the control of the scan signal terminal.

[0015] The energy storage sub-circuit is electrically connected with the first node and the first power supply terminal, respectively, and is configured to store the voltage difference between the first node and the first power supply terminal.

[0016] In some possible implementation manners, the first reset sub-circuit comprises two first transistors connected in series, and the second reset sub-circuit comprises a seventh transistor.

[0017] The control electrode of the first transistor is electrically connected with the reset signal terminal, the first electrode of the first transistor is electrically connected with the initial signal terminal, and the second electrode of the first transistor is electrically connected with the first electrode of the second transistor.

[0018] The control electrode of the second transistor is electrically connected with the reset signal terminal, and the second electrode of the second transistor is electrically connected with the first node.

[0019] The control electrode of the seventh transistor is electrically connected with the second control terminal, the first electrode of the seventh transistor is electrically connected with the initial signal terminal, and the second electrode of the seventh transistor is electrically connected with the fourth node.

[0020] In some possible implementation manners, the compensation sub-circuit comprises two second transistors and an eighth transistor connected in series;

[0021] The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second node, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor;

[0022] The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first electrode of the eighth transistor;

[0023] The control electrode of the eighth transistor is electrically connected with the first control end, and the second electrode of the eighth transistor is electrically connected with the first node and the first electrode of the eighth transistor respectively.

[0024] In some possible implementation manners, the compensation sub-circuit comprises two second transistors and an eighth transistor connected in series;

[0025] The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second electrode of the eighth transistor, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor;

[0026] The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first node;

[0027] The control electrode of the eighth transistor is electrically connected with the first control end, and the first electrode of the eighth transistor is electrically connected with the second node and the second electrode of the eighth transistor respectively.

[0028] In some possible implementation manners, the write sub-circuit comprises a fourth transistor, and the energy storage sub-circuit comprises a capacitor;

[0029] The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the third node;

[0030] The first end of the capacitor is connected with the first power supply end, and the second end of the capacitor is electrically connected with the first node.

[0031] In some possible implementation manners, the drive sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor;

[0032] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node;

[0033] The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the third node.

[0034] The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0035] In some possible implementation manners, the node control sub-circuit comprises two first transistors connected in series, two second transistors connected in series, a fourth transistor, a seventh transistor, an eighth transistor and a capacitor, the driving sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor.

[0036] The control electrode of the first first transistor is electrically connected with the reset signal end, the first electrode of the first first transistor is electrically connected with the initial signal end, and the second electrode of the first first transistor is electrically connected with the first electrode of the second first transistor.

[0037] The control electrode of the second first transistor is electrically connected with the reset signal end, and the second electrode of the second first transistor is electrically connected with the first node.

[0038] The control electrode of the first second transistor is electrically connected with the scanning signal end, the first electrode of the first second transistor is electrically connected with the second node, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor.

[0039] The control electrode of the second second transistor is electrically connected with the scanning signal end, and the second electrode of the second second transistor is electrically connected with the first electrode of the eighth transistor.

[0040] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0041] The control electrode of the fourth transistor is electrically connected with the scanning signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the third node.

[0042] The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the third node.

[0043] The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0044] The control electrode of the seventh transistor is electrically connected to the second control terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0045] The control terminal of the eighth transistor is electrically connected to the first control terminal, and the second terminal of the eighth transistor is electrically connected to the first node and the first terminal of the eighth transistor, respectively.

[0046] The first terminal of the capacitor is connected to the first power supply terminal, and the second terminal of the capacitor is electrically connected to the first node.

[0047] In some possible implementations, the node control sub-circuit includes: two first transistors connected in series, two second transistors connected in series, a fourth transistor, a seventh transistor, an eighth transistor, and a capacitor; the driving sub-circuit includes: a third transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0048] The control electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0049] The control electrode of the second first transistor is electrically connected to the reset signal terminal, and the second electrode of the second first transistor is electrically connected to the first node.

[0050] The control electrode of the first second transistor is electrically connected to the scan signal terminal, the first electrode of the first second transistor is electrically connected to the second electrode of the eighth transistor, and the second electrode of the first second transistor is electrically connected to the first electrode of the second second transistor.

[0051] The control electrode of the second transistor is electrically connected to the scan signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0052] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node.

[0053] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0054] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the third node.

[0055] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0056] The control electrode of the seventh transistor is electrically connected to the second control terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0057] The control terminal of the eighth transistor is electrically connected to the first control terminal, and the first terminal of the eighth transistor is electrically connected to the second node and the second terminal of the eighth transistor, respectively.

[0058] The first terminal of the capacitor is connected to the first power supply terminal, and the second terminal of the capacitor is electrically connected to the first node.

[0059] In some possible implementations, the second transistor and the eighth transistor are of the same transistor type;

[0060] The width of the channel region of the eighth transistor is approximately 1 micrometer to 3 micrometers, and the length of the channel region of the eighth transistor is approximately 3 micrometers to 9 micrometers.

[0061] In some possible implementations, during the initialization phase, the signals of the scanning signal terminal and the first control terminal are inverted signals.

[0062] In some possible implementations, the second control terminal switches from an active level signal to an inactive level signal earlier than the light-emitting signal terminal switches from an inactive level signal to an active level signal.

[0063] In some possible implementations, the signal at the second control terminal is a reset signal terminal or a scan signal terminal.

[0064] In some possible implementations, the light-emitting element includes an organic light-emitting diode;

[0065] The anode of the organic light-emitting diode is electrically connected to the fourth node, and the cathode of the organic light-emitting element is electrically connected to the second power supply terminal.

[0066] Secondly, this disclosure also provides a display device, including: the aforementioned pixel driving circuits arranged in an array.

[0067] In some possible implementations, the scan signal terminal of the pixel driving circuit in the i-th row is the same as the reset signal terminal of the pixel driving circuit in the (i+1)-th row, where i is a positive integer greater than or equal to 1 and less than M, and M is the total number of rows of the pixel driving circuit.

[0068] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0069] Under the control of the reset signal terminal, the node control sub-circuit provides the initial signal terminal signal to the first node, and under the control of the second control terminal, it provides the initial signal terminal signal to the fourth node. Under the control of the scan signal terminal, the node control sub-circuit provides the second node signal to the first node and the data signal terminal signal to the third node. Under the control of the first control terminal, the node control sub-circuit adjusts the signal of the first node or the second node.

[0070] Under the control of the first and third nodes, the driving sub-circuit provides driving current to the second node;

[0071] Under the control of the light-emitting control terminal, the light-emitting control sub-circuit provides the signal from the first power supply terminal to the third node and the signal from the second node to the fourth node.

[0072] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0073] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0074] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0075] Figure 2 A schematic diagram of the structure of a node control sub-circuit provided for an exemplary embodiment;

[0076] Figure 3 An equivalent circuit diagram of a first reset sub-circuit provided for an exemplary embodiment;

[0077] Figure 4 An equivalent circuit diagram of a second reset sub-circuit provided for an exemplary embodiment;

[0078] Figure 5 An equivalent circuit diagram of a write sub-circuit provided for an exemplary embodiment;

[0079] Figure 6 An equivalent circuit diagram of an energy storage sub-circuit provided for an exemplary embodiment;

[0080] Figure 7 An equivalent circuit diagram of a compensation sub-circuit provided for an exemplary embodiment;

[0081] Figure 8 An equivalent circuit diagram of the compensation sub-circuit provided for another exemplary embodiment;

[0082] Figure 9An equivalent circuit diagram of a driving sub-circuit provided for an exemplary embodiment;

[0083] Figure 10 An equivalent circuit diagram of a light-emitting control sub-circuit provided for an exemplary embodiment;

[0084] Figure 11 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment;

[0085] Figure 12 An equivalent circuit diagram of a pixel driving circuit provided for another exemplary embodiment;

[0086] Figure 13 The operating timing of a pixel driving circuit Figure 1 ;

[0087] Figure 14 The operating timing of a pixel driving circuit Figure 2 ;

[0088] Figure 15 This is the simulation timing diagram of the pixel driving circuit;

[0089] Figure 16 A comparison diagram of multiple pixel driving circuits;

[0090] Figure 17 This diagram illustrates the rate of change of the drive current of multiple pixel driving circuits as a function of the channel region size of the eighth transistor. Figure 1 ;

[0091] Figure 18 This diagram illustrates the rate of change of the drive current of multiple pixel driving circuits as a function of the channel region size of the eighth transistor. Figure 2 . Detailed Implementation

[0092] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0093] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0094] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0095] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0096] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0097] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0098] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0099] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0100] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0101] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0102] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0103] An OLED display device includes multiple pixel units, at least one pixel unit including a pixel driving circuit and a light-emitting element, wherein the pixel driving element can drive the light-emitting element to emit light. Some transistors in the pixel driving circuit have high threshold voltage sensitivity; even slight changes can cause threshold voltage drift, resulting in poor display performance of the OLED display device. Simulation results show that the high threshold voltage sensitivity of some transistors is due to the self-capacitance jumps caused by the transistors turning on and off. The self-capacitance of a transistor is a device-specific property and cannot be changed.

[0104] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 1As shown, the pixel driving circuit provided in this embodiment is configured to drive a light-emitting element to emit light, including: a node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The node control sub-circuit is electrically connected to a first power supply terminal VDD, a reset signal terminal Reset, an initial signal terminal INIT, a first control terminal S1, a second control terminal S2, a scan signal terminal Gate, a data signal terminal Data, a first node N1, a second node N2, a third node N3, and a fourth node N4. It is configured to provide the initial signal terminal INIT to the first node N1 under the control of the reset signal terminal Reset, provide the initial signal terminal INIT to the fourth node N4 under the control of the second control terminal S2, provide the signal of the second node N2 to the first node N1 under the control of the scan signal terminal Gate, and provide the data signal terminal Data to the third node N3. Under the control of the first control terminal S1, it adjusts the signal of the first node N1 or the second node N2. The driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide driving current to the second node N2 under the control of the first node N1 and the third node N3. The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to provide the signal of the first power supply terminal VDD to the third node N3 and the signal of the second node N2 to the fourth node N4 under the control of the light-emitting signal terminal EM.

[0105] In one exemplary embodiment, the operation of the pixel driving circuit may include an initialization stage, a data writing stage, and a light emission stage; wherein, in the data writing stage and the light emission stage, the signals of the scanning signal terminal Gate and the first control terminal S1 are inverse signals.

[0106] In one exemplary embodiment, the light-emitting element is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0107] In one exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0108] The pixel driving circuit provided in this embodiment is configured to drive a light-emitting element to emit light, including: a node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit; the node control sub-circuit is electrically connected to a first power supply terminal, a reset signal terminal, an initial signal terminal, a first control terminal, a second control terminal, a scan signal terminal, a data signal terminal, a first node, a second node, a third node, and a fourth node, respectively, and is configured to provide the initial signal terminal signal to the first node under the control of the reset signal terminal, provide the initial signal terminal signal to the fourth node under the control of the second control terminal, provide the second node signal to the first node under the control of the scan signal terminal, and provide the data signal terminal signal to the third node, and adjust the signal of the first node or the second node under the control of the first control terminal; the driving sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to provide a driving current to the second node under the control of the first node and the third node; the light-emitting control sub-circuit is electrically connected to the light-emitting control terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the first power supply terminal signal to the third node and the second node signal to the fourth node under the control of the light-emitting control terminal; the light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively. In the data writing and light emission stages of this disclosure, the signals of the scanning signal terminal Gate and the first control terminal S1 are inverse signals. The node control sub-circuit is connected to the first control terminal and, under the control of the first control terminal, adjusts the signal of the first node or the second node. This can reduce the threshold voltage sensitivity of some transistors, reduce the threshold voltage drift of some transistors, and improve the display effect of the OLED display device.

[0109] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0110] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0111] In one exemplary embodiment, the anode of the organic light-emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light-emitting element is electrically connected to the second power supply terminal VSS.

[0112] Figure 2 A schematic diagram of a node control sub-circuit provided for an exemplary embodiment. (See diagram below.) Figure 2As shown, in an exemplary embodiment, the node control sub-circuit in the pixel driving circuit may include: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a write sub-circuit, and an energy storage sub-circuit. The first reset sub-circuit is electrically connected to the reset signal terminal Reset, the initial signal terminal INIT, and the first node N1, and is configured to provide the initial signal terminal INIT to the first node N1 under the control of the reset signal terminal Reset. The second reset sub-circuit is electrically connected to the second control terminal S2, the initial signal terminal INIT, and the fourth node N4, and is configured to provide the initial signal terminal INIT to the fourth node N4 under the control of the second control terminal S2. The compensation sub-circuit is electrically connected to the first control terminal S1, the scan signal terminal Gate, the first node N1, and the second node N2. The connection is configured to provide the signal of the second node N2 to the first node N1 under the control of the scanning signal terminal Gate, and to adjust the signal of the first node N1 or the second node N2 under the control of the first control terminal S1; the write sub-circuit is electrically connected to the scanning signal terminal Gate, the data signal terminal Data and the third node N3 respectively, and is configured to provide the signal of the data signal terminal Data to the third node N3 under the control of the scanning signal terminal Gate; the energy storage sub-circuit is electrically connected to the first node N1 and the first power supply terminal VDD respectively, and is configured to store the voltage difference between the first node N1 and the first power supply terminal VDD.

[0113] Figure 3 An equivalent circuit diagram of a first reset sub-circuit provided for an exemplary embodiment. (e.g.) Figure 3 As shown, in one exemplary embodiment, the first reset sub-circuit may include two first transistors T1 connected in series. The control electrode of the first first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first first transistor T1 is electrically connected to the first electrode of the second first transistor T1; the control electrode of the second first transistor T1 is electrically connected to the reset signal terminal Reset, and the second electrode of the second first transistor T1 is electrically connected to the first node N1.

[0114] In one exemplary embodiment, the first reset sub-circuit includes two first transistors connected in series, which can reduce the leakage current of the pixel driving circuit, prevent the pixel driving circuit from malfunctioning when one of the first transistors fails to work properly, and improve the reliability of the pixel driving circuit.

[0115] The first transistor is a reset transistor. When the reset signal is at a valid level, the first transistor T1 transmits an initialization voltage to the first node N1 to initialize the charge of the first node N1. Here, the valid level signal refers to the signal that turns the transistor on.

[0116] Figure 3 An exemplary structure of the first reset circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first reset circuit is not limited to this; the first reset circuit may also include a first transistor, as long as it performs its function.

[0117] Figure 4 An equivalent circuit diagram of a second reset sub-circuit provided for an exemplary embodiment. (See diagram below.) Figure 4 As shown, in one exemplary embodiment, the second reset circuit may include a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the second control terminal S2, the first terminal of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4.

[0118] The seventh transistor is a reset transistor. When the signal at the second control terminal S2 is an effective level signal, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light-emitting element so as to initialize or release the accumulated charge in the first electrode of the light-emitting element.

[0119] Figure 4 An exemplary structure of the second reset circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second reset circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0120] Figure 5 An equivalent circuit diagram of a write sub-circuit is provided for one exemplary embodiment. For example... Figure 5 As shown, in one exemplary embodiment, the write sub-circuit may include a fourth transistor T4. The control terminal of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the third node N3.

[0121] The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When the signal at the scanning signal terminal is an effective level signal, the fourth transistor T4 enables the data voltage at the data signal terminal to be input to the pixel driving circuit.

[0122] Figure 5 An exemplary structure of the write sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the write sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0123] Figure 6 An equivalent circuit diagram of an energy storage sub-circuit provided for an exemplary embodiment. For example... Figure 6As shown, in one exemplary embodiment, the energy storage sub-circuit includes a capacitor C. A first terminal of capacitor C is connected to a first power supply terminal VDD, and a second terminal of capacitor C is electrically connected to a first node N1.

[0124] Figure 7 An equivalent circuit diagram of a compensation sub-circuit provided for an exemplary embodiment. For example... Figure 7 As shown, in one exemplary embodiment, the compensation sub-circuit may include two second transistors T2 and an eighth transistor T8 connected in series. The control electrode of the first second transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the first second transistor T2 is electrically connected to the second node N2, and the second electrode of the first second transistor T2 is electrically connected to the first electrode of the second second transistor T2. The control electrode of the second second transistor T2 is electrically connected to the scan signal terminal Gate, and the second electrode of the second second transistor T2 is electrically connected to the first electrode of the eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first control terminal S1, and the second electrode of the eighth transistor T8 is electrically connected to both the first node N1 and the first electrode of the eighth transistor T8.

[0125] Figure 8 An equivalent circuit diagram of a compensation sub-circuit provided for another exemplary embodiment. (e.g.) Figure 8 As shown, in one exemplary embodiment, the compensation sub-circuit may include two second transistors T2 and an eighth transistor T8 connected in series. The control electrode of the first second transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the first second transistor T2 is electrically connected to the second electrode of the eighth transistor T8, and the second electrode of the first second transistor T2 is electrically connected to the first electrode of the second second transistor T2; the control electrode of the second second transistor T2 is electrically connected to the scan signal terminal Gate, and the second electrode of the second second transistor T2 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the first control terminal S1, and the first electrode of the eighth transistor T8 is electrically connected to both the second node N2 and the second electrode of the eighth transistor T8.

[0126] Figure 7 and Figure 8 The difference is that, Figure 7 The eighth transistor is located between the second transistor and the first node. Figure 8 The eighth transistor is located between the second transistor and the second node.

[0127] In one exemplary embodiment, such as Figure 7 and Figure 8 As shown, the connection between the first and second terminals of the eighth transistor makes it functionally equivalent to a wire. When the signal at the scan signal terminal Gate is at an active level, the second transistor T2 connects the first node N1 and the second node N2.

[0128] In one exemplary embodiment, the compensation sub-circuit includes two first transistors connected in series, which can reduce the leakage current of the pixel driving circuit, prevent the pixel driving circuit from malfunctioning when one of the second transistors fails to work properly, and improve the reliability of the pixel driving circuit.

[0129] Figure 7 and Figure 8 An exemplary structure of the compensator sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the compensator sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0130] Figure 9 An equivalent circuit diagram of a driver sub-circuit provided for an exemplary embodiment. (e.g.) Figure 9 As shown, in one exemplary embodiment, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0131] The third transistor T3 can be called the driving transistor. The third transistor T3 determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between its control terminal and the first terminal.

[0132] Figure 10 An equivalent circuit diagram of a light-emitting control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 9 As shown, in one exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0133] The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (LEDs). When the signal at the light-emitting signal terminal EM is at an active level, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0134] Figure 10 An exemplary structure of the light-emitting control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to this, and any implementation that achieves its function is acceptable.

[0135] Figure 11 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment. (e.g.) Figure 11 As shown, a node control sub-circuit in a pixel driving circuit provided by an exemplary embodiment may include: two first transistors T1 connected in series, two second transistors T2 connected in series, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8 and a capacitor; the driving sub-circuit may include: a third transistor T3; and the light emission control sub-circuit may include: a fifth transistor T5 and a sixth transistor T6. The control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first terminal of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T1; the control electrode of the second transistor T1 is electrically connected to the reset signal terminal Reset, and the second terminal of the second transistor T1 is electrically connected to the first node N1; the control electrode of the first transistor T2 is electrically connected to the scan signal terminal Gate, the first terminal of the first transistor T2 is electrically connected to the second node N2, and the second terminal of the first transistor T2 is electrically connected to the first terminal of the second transistor T2; the control electrode of the second transistor T2 is electrically connected to the scan signal terminal Gate, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the eighth transistor T8; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first node N1; the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N1; the first terminal of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N1; the second terminal of the third transistor T3 is connected to the second node N2; the second terminal of the fourth transistor T4 is connected to the second node N3; the second terminal of the third transistor T4 is connected to the second node N1; the second terminal of the third transistor T3 is connected to the second node N3; the second terminal of the fourth transistor T4 is connected to the second node N1; the second terminal of the third transistor The first terminal of the fourth transistor T4 is electrically connected to the data signal terminal (Data), and the second terminal of the fourth transistor T4 is electrically connected to the third node N3. The control terminal of the fifth transistor T5 is electrically connected to the light emission signal terminal (EM), and the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal (VDD). The second terminal of the fifth transistor T5 is electrically connected to the third node N3. The control terminal of the sixth transistor T6 is electrically connected to the light emission signal terminal (EM), and the first terminal of the sixth transistor T6 is electrically connected to the second node N2. The second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The control terminal of the seventh transistor T7 is electrically connected to the second control terminal (S2), and the first terminal of the seventh transistor T7 is electrically connected to the initial signal terminal (INIT). The second terminal of the seventh transistor T7 is electrically connected to the fourth node N4. The control terminal of the eighth transistor T8 is electrically connected to the first control terminal (S1), and the second terminal of the eighth transistor T8 is electrically connected to both the first node N1 and the first terminal of the eighth transistor T8. The first terminal of capacitor C is connected to the first power supply terminal (VDD), and the second terminal of capacitor C is connected to the first node N1.

[0136] Figure 12 An equivalent circuit diagram of a pixel driving circuit provided for another exemplary embodiment. (e.g.) Figure 12As shown, a node control sub-circuit in a pixel driving circuit provided by an exemplary embodiment may include: two first transistors T1 connected in series, two second transistors T2 connected in series, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8 and a capacitor; the driving sub-circuit may include: a third transistor T3; and the light emission control sub-circuit may include: a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first terminal of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T1; the control electrode of the second transistor T1 is electrically connected to the reset signal terminal Reset, and the second terminal of the second transistor T1 is electrically connected to the first node N1; the control electrode of the first transistor T2 is electrically connected to the scan signal terminal Gate, the first terminal of the first transistor T2 is electrically connected to the second terminal of the eighth transistor T8, and the second terminal of the first transistor T2 is electrically connected to the first terminal of the second transistor T2; the control electrode of the second transistor T2 is electrically connected to the scan signal terminal Gate, and the second terminal of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 ... The control terminal of the fifth transistor T5 is electrically connected to the light emission signal terminal EM, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3; the control terminal of the sixth transistor T6 is electrically connected to the light emission signal terminal EM, the first terminal of the sixth transistor T6 is electrically connected to the second node N2, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the control terminal of the seventh transistor T7 is electrically connected to the second control terminal S2, the first terminal of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4; the control terminal of the eighth transistor T8 is electrically connected to the first control terminal S1, and the first terminal of the eighth transistor T8 is electrically connected to both the second node N2 and the second terminal of the eighth transistor T8; the first terminal of capacitor C is connected to the first power supply terminal VDD, and the second terminal of capacitor C is connected to the first node N1.

[0137] Figure 11 and Figure 12 The difference lies in the position of the eighth transistor, T8. Figure 11 The eighth transistor T8 is located between the second transistor T2 and the first node N1. Figure 12The eighth transistor is located between the second transistor T2 and the second node N2.

[0138] In one exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be P-type transistors or N-type transistors. The second transistor T2 and the eighth transistor T8 are of the same transistor type. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0139] In one exemplary embodiment, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0140] In one exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be low-temperature polysilicon transistors.

[0141] In one exemplary embodiment, some transistors may be oxide transistors, and some transistors may be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0142] In one exemplary embodiment, the width of the channel region of the eighth transistor is approximately 1 micrometer to 3 micrometers, and the length of the channel region of the eighth transistor is approximately 3 micrometers to 9 micrometers. Exemplarily, the width of the channel region of the eighth transistor may be approximately 2 micrometers, and the length of the channel region of the eighth transistor may be approximately 3 micrometers.

[0143] In one exemplary embodiment, during the initialization phase, the signals of the scan signal terminal Gate and the first control terminal S1 can be the same or can be inverse signals.

[0144] In one exemplary embodiment, the moment when the signal at the light-emitting signal terminal EM changes from an invalid level signal to an effective level signal can be the same moment as the moment when the signal at the scanning signal terminal Gate changes from an effective level signal to an invalid level signal, or it can be later than the moment when the signal at the scanning signal terminal Gate changes from an effective level signal to an invalid level signal.

[0145] When the signal of the light-emitting signal terminal EM changes from an invalid level signal to an effective level signal at the same time as the signal of the scanning signal terminal Gate changes from an effective level signal to an invalid level signal, and when the signals of the scanning signal terminal Gate and the first control terminal S1 are the same, the first control terminal S1 can be the light-emitting signal terminal EM. In this case, the signal line connected to the first control terminal S1 can be the same signal line connected to the light-emitting signal terminal EM, which can reduce the number of signal lines connected to the pixel driving signal and achieve a narrow bezel.

[0146] During the initialization phase, when the signals of the scan signal terminal Gate and the first control terminal S1 are inverted signals, the scan signal terminal Gate and the first control terminal S1 will remain inverted signals throughout the entire operation of the pixel driving circuit.

[0147] In one exemplary embodiment, the reset signal terminal Reset is an active level signal during the initialization phase, the scan signal terminal Gate is an active level signal during the data writing phase, and the light emission signal terminal EM and the first control terminal S1 are active level signals during the light emission phase.

[0148] In one exemplary embodiment, during the data writing stage and the light emission signal terminal, the scan signal terminal Gate and the first control terminal S1 are inverted signals. That is, the moment when the signal of the first control terminal S1 changes from an invalid level signal to an effective level signal is the same moment when the signal of the scan signal terminal Gate changes from an effective level signal to an invalid level signal. In other words, the conduction of the eighth transistor T8 occurs after the conduction of the second transistor T2.

[0149] Taking the second transistor T2 and the eighth transistor T8 as P-type transistors as an example, the effective level signal is a low level signal and the ineffective level signal is a high level signal. When the signal at the scan signal terminal Gate changes from an effective level signal to an ineffective level signal, the signal at the control terminal of the second transistor T2 changes from a low level signal to a high level signal. At this time, due to the effect of the self-capacitance of the second transistor T2, the voltage coupling between the first and second terminals of the second transistor T2 increases. After this, the signal at the first control terminal S1 changes from an ineffective level signal to an effective level signal, that is, the signal at the control terminal of the eighth transistor T8 changes from a high level signal to a low level signal. Due to the effect of the self-capacitance of the eighth transistor T8, the voltage between the first and second terminals of the second transistor T2 is reduced, that is, the effect of the self-capacitance of the second transistor T2 is canceled, and the threshold voltage sensitivity of the second transistor is reduced.

[0150] Taking the second transistor T2 and the eighth transistor T8 as N-type transistors as an example, the effective level signal is a high level signal and the ineffective level signal is a low level signal. When the signal at the scan signal terminal Gate changes from an effective level signal to an ineffective level signal, the signal at the control terminal of the second transistor T2 changes from a high level signal to a low level signal. At this time, due to the effect of the self-capacitance of the second transistor T2, the voltage coupling between the first and second terminals of the second transistor T2 is reduced. After this, the signal at the first control terminal S1 changes from an ineffective level signal to an effective level signal, that is, the signal at the control terminal of the eighth transistor T8 changes from a low level to a high level signal. Due to the effect of the self-capacitance of the eighth transistor T8, the voltage between the first and second terminals of the second transistor T2 is increased, that is, the effect of the self-capacitance of the second transistor T2 is canceled, and the threshold voltage sensitivity of the second transistor is reduced.

[0151] In one exemplary embodiment, the second control terminal S2 switches from an active level signal to an inactive level signal earlier than the time when the light-emitting signal terminal EM switches from an inactive level signal to an active level signal. This earlier switch ensures that the light-emitting element emits light normally.

[0152] In one exemplary embodiment, the second control terminal S2 can be a reset signal terminal Reset or a scan signal terminal Gate. The second control terminal S2 can be a reset signal terminal Reset or a scan signal terminal Gate, which can reduce the number of signal lines connected to the pixel driving signal and achieve a narrow bezel.

[0153] Figure 13 The operating timing of a pixel driving circuit Figure 1 , Figure 14 The operating timing of a pixel driving circuit Figure 2 , Figure 15 This is the simulation timing diagram for the pixel driving circuit. Figure 13 and Figure 14 This explanation uses the example of the light-emitting signal EM transitioning from an invalid level to an active level later than the scan signal Gate transitioning from an active level to an invalid level, and the signal at the first control terminal S1 and the signal at the scan signal Gate being inverse signals to each other throughout the operation of the pixel driving circuit. Figure 13 This explanation uses the second control terminal S2 as the reset signal terminal Reset as an example. Figure 14 This explanation will be based on the example of the second control terminal S2 being the scanning signal terminal Gate. Figure 17 This explanation is based on the example where the first control terminal S1 is the light-emitting signal terminal EM and the second control terminal S2 is the scanning signal terminal Gate.

[0154] The following is through Figure 13 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure, because... Figure 11 and Figure 12 The first and second terminals of the eighth transistor T8 are connected, meaning the eighth transistor T8 is equivalent to the first segment of the wire. Figure 11 and Figure 12 The working process is the same. Taking the first transistor T1 to the eighth transistor T8 as P-type transistors as an example, Figure 11 and Figure 12 The pixel driving circuit includes first transistors T1 to eighth transistors T8, a capacitor C, and eight signal terminals (Data signal terminal, Gate signal terminal, Reset signal terminal, EM signal terminal, INIT signal terminal, first control terminal S1, second control terminal S2, first power supply terminal VDD, and second power supply terminal VSS). In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0155] In the first stage, P1, also known as the initialization stage, the signals at the EM and Gate terminals are both high, while the signals at the first control terminal S1, the Reset terminal, and the second control terminal S2 are low. When the Reset terminal is low, the first transistor T1 is turned on, the INIT terminal provides the signal to the first node N1, the seventh transistor T7 is turned on, and the initial voltage of the INIT terminal is provided to the fourth node N4, initializing (resetting) the first terminal of the light-emitting element L, clearing its internal pre-stored voltage, and completing the initialization process to ensure that the light-emitting element L does not emit light. When the first control terminal S1 is low, the eighth transistor T8 is turned on, the Gate terminal and the EM terminal are high, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. During this stage, the light-emitting element L does not emit light.

[0156] The second stage, P2, is called the data writing stage or threshold compensation stage. During this stage, the Reset signal, the EM signal, the first control terminal S1, and the second control terminal S2 are all high-level signals, while the Gate signal is low-level. The Data signal outputs a data voltage. Because the first node N1 is low-level, the third transistor T3 is turned on. The Gate signal is also low-level, turning on the second transistor T2 and the fourth transistor T4. The second transistor T2 and the fourth transistor T4 cause the data voltage output from the Data signal to be supplied to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, the turned-on second transistor T2, the fourth node N4, and the eighth transistor T8. The difference between the data voltage output from the Data signal and the threshold voltage of the third transistor T3 is charged into capacitor C until the voltage at the first node N1 is Vd - |Vth|, where Vd is the data voltage output from the Data signal and Vth is the threshold voltage of the third transistor T3. When the reset signal terminal (Reset) and the second control terminal (S2) are both high, the first transistor (T1) and the seventh transistor (T7) are disconnected. When the light-emitting signal terminal (EM) is high, the fifth transistor (T5) and the sixth transistor (T6) are disconnected. During this stage, the light-emitting element (L) does not emit light.

[0157] In the third stage, P3, also known as the light-emitting stage, the signals at the first control terminal S1 and the light-emitting signal terminal EM are both low-level signals, while the signals at the reset signal terminal Reset, the scan signal terminal Gate, and the second control terminal S2 are high-level signals. With the reset signal terminal Reset and the second control terminal S2 low-level signals, the first transistor T1 and the seventh transistor T7 are off. With the scan signal terminal Gate high-level signal, the signals at the second transistor T2, the fourth transistor T4, and the first control terminal S1 are low-level signals, and the eighth transistor T8 is turned on. The signal at the control electrode of the eighth transistor T8 changes from high to low level. Due to the effect of the capacitance of the eighth transistor T8, the voltage increase caused by the coupling between the first and second electrodes of the second transistor T2 when the control electrode signal of the second transistor T2 changes from low to high level is reduced. This effectively cancels out the effect of the capacitance of the second transistor T2, thus reducing its threshold voltage sensitivity. The signal at the light-emitting signal terminal EM is a low-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting element L to emit light.

[0158] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0159] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0160] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0161] The following is through Figure 14 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure, because... Figure 11 and Figure 12 The first and second terminals of the eighth transistor T8 are connected, meaning the eighth transistor T8 is equivalent to the first segment of the wire. Figure 11 and Figure 12 The working process is the same. Taking the first transistor T1 to the eighth transistor T8 as P-type transistors as an example, Figure 11 and Figure 12 The pixel driving circuit includes first transistors T1 to eighth transistors T8, a capacitor C, and eight signal terminals (Data signal terminal, Gate signal terminal, Reset signal terminal, EM signal terminal, INIT signal terminal, first control terminal S1, second control terminal S2, first power supply terminal VDD, and second power supply terminal VSS). In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0162] In the first stage, P1, also known as the initialization stage, the signals at the EM (light-emitting signal terminal), Gate (scanning signal terminal), and S2 (second control terminal) are all high-level signals, while the signals at the Reset (reset signal terminal) and S1 (first control terminal) are low-level signals. When the Reset signal is low, the first transistor T1 is turned on, and the INIT signal is supplied to the first node N1. When the second control terminal S2 is high, the seventh transistor T7 is turned off, S1 is low, the eighth transistor T8 is turned on, and the signals at the Gate and EM (light-emitting signal terminals) are high. During this stage, the second transistor T2, fourth transistor T4, fifth transistor T5, and sixth transistor T6 are also active. The light-emitting element L does not emit light during this stage.

[0163] The second stage, P2, is called the data writing stage or threshold compensation stage. The Reset signal, the EM signal, and the first control terminal S1 are all high-level signals, while the Gate signal and the second control terminal S2 are low-level signals. The Data signal outputs the data voltage. During this stage, since the first node N1 is low, the third transistor T3 is turned on. The second control terminal S2 is low, turning on the seventh transistor T7. The initial voltage of the INIT signal is provided to the fourth node N2, initializing (resetting) the first electrode of the light-emitting element L, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the light-emitting element L does not emit light. The Gate signal is low, turning on the second transistor T2 and the fourth transistor T4. The second transistor T2 and the fourth transistor T4 cause the data voltage output from the data signal terminal Data to be supplied to the first node N1 via the third node N3, the conducting third transistor T3, the second node N2, the conducting second transistor T2, the fourth node N4, and the eighth transistor T8. The difference between the data voltage output from the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into capacitor C until the voltage at the first node N1 is Vd - |Vth|, where Vd is the data voltage output from the data signal terminal Data and Vth is the threshold voltage of the third transistor T3. The reset signal terminal Reset and the second control terminal S2 are both high-level signals, and the first transistor T1 and the seventh transistor T7 are disconnected. The light-emitting signal terminal EM is also high-level, and the fifth transistor T5 and the sixth transistor T6 are disconnected. During this stage, the light-emitting element L does not emit light.

[0164] In the third stage, P3, also known as the light-emitting stage, the signals at the first control terminal S1 and the light-emitting signal terminal EM are both low-level signals, while the signals at the reset signal terminal Reset, the scan signal terminal Gate, and the second control terminal S2 are high-level signals. With the reset signal terminal Reset and the second control terminal S2 low-level signals, the first transistor T1 and the seventh transistor T7 are off. With the scan signal terminal Gate high-level signal, the signals at the second transistor T2, the fourth transistor T4, and the first control terminal S1 are low-level signals, and the eighth transistor T8 is turned on. The signal at the control electrode of the eighth transistor T8 changes from high to low level. Due to the effect of the capacitance of the eighth transistor T8, the voltage increase caused by the coupling between the first and second electrodes of the second transistor T2 when the control electrode signal of the second transistor T2 changes from low to high level is reduced. This effectively cancels out the effect of the capacitance of the second transistor T2, thus reducing its threshold voltage sensitivity. The signal at the light-emitting signal terminal EM is a low-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting element L to emit light.

[0165] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0166] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0167] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0168] In one exemplary embodiment, the operation of the pixel driving circuit may include at least one first stage and at least one second stage. Figure 13 to Figure 14 The operation of the pixel driving circuit is explained using a first stage and a second stage as an example. Figure 15 This explanation uses three first phases and three second phases as examples, and this disclosure does not impose any limitations on them.

[0169] Because the first and second terminals of the eighth transistor T8 are connected, during the light-emitting phase, Figure 11 and Figure 12 The voltage of the first node of the provided pixel driving circuit is the same as the voltage of the first node of a pixel driving circuit that includes only the first to seventh transistors, i.e. Figure 11 and Figure 12 The provided pixel driving circuit has the same flicker level as the pixel driving circuit that only includes the first to seventh transistors, so adding the eighth transistor will not cause poor display brightness.

[0170] Figure 16 This is a comparison diagram of multiple pixel driving circuits. Figure 16 The horizontal axis represents the threshold voltage drift of the second transistor, and the vertical axis represents the rate of change of the drive current. The rate of change of the drive current is equal to the ratio of the difference between the drive current when the threshold voltage of the second transistor does not drift and the drive current when the threshold voltage of the second transistor drifts, to the drive current when the threshold voltage of the second transistor does not drift. The rate of change of the drive current can represent the sensitivity of the threshold voltage of the second transistor. Figure 16 The A in the text refers to Figure 11 The pixel driving circuit shown, B refers to Figure 12 The pixel driving circuit shown, C refers to a pixel driving circuit that includes only the first to seventh transistors.

[0171] like Figure 16 As shown, for the same second transistor's threshold voltage drift, the rate of change of the driving current in pixel driving circuit A is less than that in pixel driving circuit B, and the rate of change of the driving current in pixel driving circuit B is less than that in pixel driving circuit D. This means the threshold voltage sensitivity of the second transistor in pixel driving circuit A is less than that in pixel driving circuit B, and the threshold voltage sensitivity of pixel driving circuit B is less than that in pixel driving circuit D. Therefore, the display effect of the display device with pixel driving circuit A is stronger than that of the display device with pixel driving circuit B.

[0172] because Figure 11 The threshold voltage sensitivity of the provided pixel driving circuit is relatively low. Figure 11 The dimensions of the channel region of the eighth transistor in the provided pixel driving circuit are analyzed. Figure 17 This diagram illustrates the rate of change of the drive current of multiple pixel driving circuits as a function of the channel region size of the eighth transistor. Figure 1 . Figure 17 The horizontal axis represents the threshold voltage drift of the second transistor, and the vertical axis represents the rate of change of the drive current. Figure 17In this context, A1 refers to the width W1 micrometers of the channel region of the eighth transistor, the length L of the channel region of the eighth transistor is 3 micrometers, and the width-to-length ratio W / L of the channel region of the eighth transistor is 1 / 3. Figure 11 In the pixel driving circuit shown, A2 refers to the eighth transistor's channel region having a width W of 2 micrometers and a channel region length L of 3 micrometers. The width-to-length ratio W / L of the eighth transistor's channel region is equal to 2 / 3. Figure 11 In the pixel driving circuit shown, A3 refers to the eighth transistor's channel region having a width W of 3 micrometers and a channel region length L of 3 micrometers. The width-to-length ratio W / L of the eighth transistor's channel region is equal to 3 / 3. Figure 11 The pixel driving circuit shown, C refers to a pixel driving circuit that includes only the first to seventh transistors. For example... Figure 17 As shown, Figure 17 In pixel driving circuits A1, A2, and A3, the channel region length L of the eighth transistor is the same. As the width W of the channel region of the eighth transistor increases, the rate of change of the driving current of the pixel driving circuit decreases, meaning the sensitivity of the threshold voltage of the second transistor decreases. That is, for... Figure 11 In the pixel driving circuit shown, when the width-to-length ratio of the channel region of the eighth transistor is about 1 / 3 to 3 / 3, and the length L of the channel region of the eighth transistor is the same, the larger the width W of the channel region of the eighth transistor, the smaller the sensitivity of the threshold voltage of the second transistor, and the better the improvement of the sensitivity of the threshold voltage of the second transistor.

[0173] Figure 18 This diagram illustrates the rate of change of the drive current of multiple pixel driving circuits as a function of the channel region size of the eighth transistor. Figure 2 . Figure 18 The horizontal axis represents the threshold voltage drift of the second transistor, and the vertical axis represents the rate of change of the drive current. Figure 18 In this context, A4 refers to the width W of the channel region of the eighth transistor being 2 micrometers, the length L of the channel region being 3 micrometers, and the width-to-length ratio W / L of the channel region being equal to 2 / 3. Figure 11 In the pixel driving circuit shown, A5 refers to the eighth transistor's channel region having a width W of 2 micrometers and a channel region length L of 6 micrometers. The width-to-length ratio W / L of the eighth transistor's channel region is equal to 2 / 6. Figure 11 In the pixel driving circuit shown, A6 refers to the eighth transistor's channel region having a width W of 2 micrometers and a channel region length L of 9 micrometers. The width-to-length ratio W / L of the eighth transistor's channel region is equal to 2 / 9. Figure 11 The pixel driving circuit shown, C refers to a pixel driving circuit that includes only the first to seventh transistors. For example...Figure 18 As shown, Figure 18 In pixel driving circuits A4, A5, and A6, the width W of the channel region of the eighth transistor is the same. As the length L of the channel region of the eighth transistor increases, the rate of change of the driving current of the pixel driving circuit decreases, meaning the sensitivity of the threshold voltage of the second transistor decreases. Figure 11 In the pixel driving circuit shown, when the width-to-length ratio of the channel region of the eighth transistor is approximately 2 / 3 to 2 / 9, and the width W of the channel region of the eighth transistor is the same, the larger the length L of the channel region of the eighth transistor, the smaller the sensitivity of the threshold voltage of the second transistor, and the better the improvement in the sensitivity of the threshold voltage of the second transistor.

[0174] This disclosure also provides a method for driving a pixel driving circuit. The method for driving a pixel driving circuit may include the following steps:

[0175] Step 100: Under the control of the reset signal terminal, the node control sub-circuit provides the initial signal terminal signal to the first node, and under the control of the second control terminal, provides the initial signal terminal signal to the fourth node. Under the control of the scan signal terminal, the node control sub-circuit provides the second node signal to the first node and provides the data signal terminal signal to the third node. Under the control of the first control terminal, the node control sub-circuit adjusts the signal of the first node or the second node.

[0176] Step 200: Under the control of the first node and the third node, the driving sub-circuit provides driving current to the second node;

[0177] Step 300: Under the control of the light-emitting control terminal, the light-emitting control sub-circuit provides the signal from the first power supply terminal to the third node and the signal from the second node to the fourth node.

[0178] The pixel driving circuit is the same as the pixel driving circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0179] This disclosure also provides a display device, including: an array of pixel driving circuits.

[0180] The pixel driving circuit is the same as the pixel driving circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0181] In one exemplary embodiment, the display device can be a monitor, television, mobile phone, tablet computer, navigator, digital photo frame, wearable display product, or any product or component with display function.

[0182] In one exemplary embodiment, the signal at the scan signal terminal of the pixel driving circuit in the i-th row is the same as the signal at the reset signal terminal of the pixel driving circuit in the (i+1)-th row, where i is a positive integer greater than or equal to 1 and less than M, and M is the total number of rows of the pixel driving circuit.

[0183] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0184] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0185] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit configured to drive a light emitting element to emit light, comprising: The node control sub-circuit, the light-emitting control sub-circuit and the driving sub-circuit; The working process of the pixel driving circuit comprises an initialization stage, a data writing stage and a light-emitting stage; The node control sub-circuit is electrically connected with the first power supply end, the reset signal end, the initial signal end, the first control end, the second control end, the scanning signal end, the data signal end, the first node, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the initial signal end to the first node under the control of the reset signal end, provide the signal of the initial signal end to the fourth node under the control of the second control end, provide the signal of the second node to the first node and the signal of the data signal end to the third node under the control of the scanning signal end, and adjust the signal of the first node or the second node under the control of the first control end; The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide the driving current to the second node under the control of the first node and the third node; The light-emitting control sub-circuit is electrically connected with the light-emitting signal end, the first power supply end, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the first power supply end to the third node and the signal of the second node to the fourth node under the control of the light-emitting signal end; The light-emitting element is electrically connected with the fourth node and the second power supply end respectively; In the data writing stage and the light-emitting stage, the signals of the scanning signal end and the first control end are inverse signals of each other. The node control sub-circuit comprises a compensation sub-circuit, which is electrically connected with the first control end, the scanning signal end, the first node and the second node respectively, and is configured to provide the signal of the second node to the first node under the control of the scanning signal end and adjust the signal of the first node or the second node under the control of the first control end. The compensation sub-circuit comprises two series-connected second transistors and eighth transistors.

2. The pixel driving circuit according to claim 1, wherein The node control sub-circuit comprises a first reset sub-circuit, a second reset sub-circuit, a writing sub-circuit and an energy storage sub-circuit; The first reset sub-circuit is electrically connected with the reset signal end, the initial signal end and the first node respectively, and is configured to provide the signal of the initial signal end to the first node under the control of the reset signal end; The second reset sub-circuit is electrically connected with the second control end, the initial signal end and the fourth node respectively, and is configured to provide the signal of the initial signal end to the fourth node under the control of the second control end, The writing sub-circuit is electrically connected with the scanning signal end, the data signal end and the third node respectively, and is configured to provide the signal of the data signal end to the third node under the control of the scanning signal end; The energy storage sub-circuit is electrically connected with the first node and the first power supply end respectively, and is configured to store the voltage difference between the first node and the first power supply end.

3. The pixel driving circuit of claim 2, wherein, The first reset sub-circuit comprises two series-connected first transistors, and the second reset sub-circuit comprises a seventh transistor; The control electrode of the first first transistor is electrically connected with the reset signal end, the first electrode of the first first transistor is electrically connected with the initial signal end, and the second electrode of the first first transistor is electrically connected with the first electrode of the second first transistor; The control electrode of the second first transistor is electrically connected with the reset signal end, and the second electrode of the second first transistor is electrically connected with the first node. The control electrode of the seventh transistor is electrically connected with the second control end, the first electrode of the seventh transistor is electrically connected with the initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node.

4. The pixel driving circuit of claim 2, wherein, The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second node, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor. The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first electrode of the eighth transistor. The control electrode of the eighth transistor is electrically connected with the first control end, and the second electrode of the eighth transistor is electrically connected with the first node and the first electrode of the eighth transistor respectively.

5. The pixel driving circuit of claim 2, wherein, The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second electrode of the eighth transistor, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor. The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first node. The control electrode of the eighth transistor is electrically connected with the first control end, and the first electrode of the eighth transistor is electrically connected with the second node and the second electrode of the eighth transistor respectively.

6. The pixel driving circuit of claim 2, wherein, The write sub-circuit comprises a fourth transistor, and the energy storage sub-circuit comprises a capacitor. The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the third node. The first end of the capacitor is connected with the first power supply end, and the second end of the capacitor is electrically connected with the first node.

7. The pixel driving circuit of claim 1, wherein, The drive sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is connected with the second node, and the second electrode of the third transistor is connected with the third node. The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the third node. The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

8. The pixel driving circuit of claim 1, wherein, The node control sub-circuit comprises two series-connected first transistors, two series-connected second transistors, a fourth transistor, a seventh transistor, an eighth transistor and a capacitor, the drive sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control electrode of the first first transistor is electrically connected with the reset signal end, the first electrode of the first first transistor is electrically connected with the initial signal end, and the second electrode of the first first transistor is electrically connected with the first electrode of the second first transistor. The control electrode of the second first transistor is electrically connected with the reset signal end, and the second electrode of the second first transistor is electrically connected with the first node. The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second node, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor; The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first electrode of the eighth transistor; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is connected with the second node, and the second electrode of the third transistor is connected with the third node The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the third node; The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the third node; The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the fourth node; The control electrode of the seventh transistor is electrically connected with the second control end, the first electrode of the seventh transistor is electrically connected with the initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node; The control electrode of the eighth transistor is electrically connected with the first control end, and the second electrode of the eighth transistor is electrically connected with the first node and the first electrode of the eighth transistor respectively; The first end of the capacitor is connected with the first power supply end, and the second end of the capacitor is connected with the first node.

9. The pixel driving circuit of claim 1, wherein, The node control sub-circuit comprises two first transistors connected in series, two second transistors connected in series, a fourth transistor, a seventh transistor, an eighth transistor and a capacitor, the driving sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor; The control electrode of the first first transistor is electrically connected with the reset signal end, the first electrode of the first first transistor is electrically connected with the initial signal end, and the second electrode of the first first transistor is electrically connected with the first electrode of the second first transistor; The control electrode of the second first transistor is electrically connected with the reset signal end, and the second electrode of the second first transistor is electrically connected with the first node; The control electrode of the first second transistor is electrically connected with the scan signal end, the first electrode of the first second transistor is electrically connected with the second electrode of the eighth transistor, and the second electrode of the first second transistor is electrically connected with the first electrode of the second second transistor; The control electrode of the second second transistor is electrically connected with the scan signal end, and the second electrode of the second second transistor is electrically connected with the first node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is connected with the second node, and the second electrode of the third transistor is connected with the third node The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the third node; The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the third node; A control electrode of the sixth transistor is electrically connected with the light-emitting signal terminal, a first electrode of the sixth transistor is electrically connected with the second node, and a second electrode of the sixth transistor is electrically connected with the fourth node; A control electrode of the seventh transistor is electrically connected with the second control terminal, a first electrode of the seventh transistor is electrically connected with the initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node; A control electrode of the eighth transistor is electrically connected with the first control terminal, and a first electrode of the eighth transistor is electrically connected with the second node and a second electrode of the eighth transistor respectively; A first terminal of the capacitor is electrically connected with the first power terminal, and a second terminal of the capacitor is electrically connected with the first node.

10. The pixel driving circuit according to claim 8 or 9, wherein, The second transistor and the eighth transistor are of the same type. The width of the channel region of the eighth transistor is about 1-3 microns, and the length of the channel region of the eighth transistor is about 3-9 microns.

11. The pixel driving circuit of claim 1, 8 or 9, wherein, In the initialization stage, the signals of the scan signal terminal and the first control terminal are inverse signals of each other.

12. The pixel driving circuit according to any one of claims 1, 8 or 9, wherein, The second control terminal converts from the active level signal to the inactive level signal earlier than the light-emitting signal terminal converts from the inactive level signal to the active level signal.

13. The pixel driving circuit of claim 12, wherein, The second control terminal is a reset signal terminal or a scan signal terminal.

14. The pixel driving circuit of claim 1, wherein, The light-emitting element includes an organic light-emitting diode. The anode of the organic light-emitting diode is electrically connected with the fourth node, and the cathode of the organic light-emitting element is electrically connected with the second power terminal.

15. A display device comprising: The pixel driving circuit is arranged in an array.

16. The display device of claim 15, wherein, The signals of the scan signal terminal of the i-th row of pixel driving circuits and the reset signal terminal of the i+1-th row of pixel driving circuits are the same, i is a positive integer greater than or equal to 1 and less than M, and M is the total number of rows of pixel driving circuits.

17. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1-14, the method comprising: Under the control of the reset signal terminal, the node control sub-circuit provides the signal of the initial signal terminal to the first node, under the control of the second control terminal, the node control sub-circuit provides the signal of the initial signal terminal to the fourth node, under the control of the scan signal terminal, the node control sub-circuit provides the signal of the second node to the first node and provides the signal of the data signal terminal to the third node, and under the control of the first control terminal, the node control sub-circuit adjusts the signals of the first node or the second node; Under the control of the first node and the third node, the driving sub-circuit provides a driving current to the second node; Under the control of the light-emitting signal terminal, the light-emitting control sub-circuit provides the signal of the first power terminal to the third node and provides the signal of the second node to the fourth node.

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