Amplification circuit and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to an amplification circuit and a memory, comprising: a pull-up module, an input end of which is coupled with a first node, one output end of which is coupled with a bit line, and another output end of which is coupled with a complementary bit line; a pull-up control module, an input end of which is used for receiving a first control signal, and an output end of which is coupled with the pull-up module, and the pull-up control module is configured to drive the potential of the bit line or the complementary bit line of the pull-up module based on the first control signal; a pull-down module, an input end of which is coupled with a second node, one output end of which is coupled with the bit line, and another output end of which is coupled with the complementary bit line; and a pull-down control module, an input end of which is used for receiving a second control signal, and an output end of which is coupled with the pull-down module, and the pull-down control module is configured to drive the potential of the bit line or the complementary bit line of the pull-down module based on the second control signal; the embodiment of the present disclosure improves the efficiency of the sensing amplification circuit in amplifying the voltage difference between the bit line and the complementary bit line through a new sensing amplification circuit structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to an amplifier circuit and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) stores data through the charge in cell capacitors. Cell capacitors couple bit lines and complementary bit lines. In DRAM, when performing read, write or refresh operations, the amplifier circuit needs to read and amplify the voltage difference between the bit lines and complementary bit lines.

[0003] In traditional DRAM circuit structures, the sensing amplification (SA) circuit is used to amplify the voltage difference between the bit line and the complementary bit line. The sensing amplification circuit consists of two PMOS transistors and two NMOS transistors.

[0004] As DRAM process dimensions continue to shrink, the power consumption of traditional sensing amplifier circuit structures will increase, making it increasingly difficult for them to meet the market's high-performance requirements for DRAM. Therefore, it is necessary to improve the performance of sensing amplifier circuits by changing their structure. Summary of the Invention

[0005] This disclosure provides an amplifier circuit and a memory, which improves the efficiency of amplifying the voltage difference between the bit line and the complementary bit line through a new sensing amplifier circuit structure.

[0006] This disclosure provides an amplifier circuit coupled to a bit line and a complementary bit line, comprising: a pull-up module, with its input coupled to a first node, one output coupled to the bit line, and another output coupled to the complementary bit line; the first node being used to receive a high level required for potential pull-up; a pull-up control module, with its input for receiving a first control signal and its output coupled to the pull-up module; the pull-up control module being configured to drive the pull-up module to pull up the potential of the bit line or the complementary bit line based on the first control signal; a pull-down module, with its input coupled to a second node, one output coupled to the bit line, and another output coupled to the complementary bit line; the second node being used to receive a low level required for potential pull-down; and a pull-down control module, with its input for receiving a second control signal and its output coupled to the pull-down module; the pull-down control module being configured to drive the pull-down module to pull down the potential of the bit line or the complementary bit line based on the second control signal; wherein one of the first control signal and the second control signal is provided by the bit line, and the other is provided by the complementary bit line.

[0007] Additionally, the pull-up module includes: a first P-type transistor and a second P-type transistor; the pull-down module includes: a first N-type transistor and a second N-type transistor; the drain-coupled bit line of the first P-type transistor is coupled to the source of the first node, and the gate is connected to the pull-up control module; the drain-coupled complementary bit line of the second P-type transistor is coupled to the source of the first node, and the gate is connected to the pull-up control module; the drain-coupled bit line of the first N-type transistor is coupled to the source of the second node, and the gate is connected to the pull-down control module; the drain-coupled complementary bit line of the second N-type transistor is coupled to the source of the second node, and the gate is connected to the pull-down control module.

[0008] In addition, the first P-type transistor and the second P-type transistor are tunneling field-effect transistors; in addition, the first N-type transistor and the second N-type transistor are tunneling field-effect transistors; the power consumption of the sensing amplifier circuit is reduced by leveraging the advantages of TFETs such as low operating voltage, low subthreshold swing, and high switching current ratio.

[0009] Additionally, the pull-up control module includes a first pull-up inverter and a second pull-up inverter; the pull-down control module includes a first pull-down inverter and a second pull-down inverter; the input terminal of the first pull-up inverter is connected to the gate of the first P-type transistor, and the output terminal is connected to the gate of the second P-type transistor; the input terminal of the second pull-up inverter is connected to the bit line, and the output terminal is connected to the input terminal of the first pull-up inverter; the input terminal of the first pull-down inverter is connected to the gate of the second N-type transistor, and the output terminal is connected to the gate of the first N-type transistor; the input terminal of the second pull-down inverter is connected to the complementary bit line, and the output terminal is connected to the input terminal of the first pull-up inverter.

[0010] Additionally, the pull-up control module includes a pull-up inverter; the pull-down control module includes a pull-down inverter; the input terminal of the pull-up inverter is connected to the gate of the second P-type transistor via a complementary bit line, and the output terminal of the pull-up inverter is connected to the gate of the first P-type transistor; the input terminal of the pull-down inverter is connected to the gate of the first N-type transistor via a bit line, and the output terminal of the pull-down inverter is connected to the gate of the second N-type transistor.

[0011] In addition, the amplifier circuit also includes: a first switching transistor, with its drain coupled to a first node, its source used to receive a high level, and its gate used to receive a first switching signal, configured to provide a high level to the first node based on the first switching signal; and a second switching transistor, with its drain coupled to a second node, its source used to receive a low level, and its gate used to receive a second switching signal, configured to provide a low level to the second node based on the second switching signal.

[0012] In addition, the first and second switching transistors are tunneling field-effect transistors; the TFET transistor is used as a switch to receive the high level required for the pull-up potential of the sensing amplifier circuit and the low level required for the pull-down potential, so as to reduce the power consumption of the sensing amplifier circuit by taking advantage of the low operating voltage and high switching current ratio of the TFET transistor.

[0013] In addition, the amplifier circuit also includes: a first adjustment circuit, one end coupled to the bit line and the other end coupled to the complementary bit line, the first adjustment circuit being configured to adjust the potential of the bit line in reverse phase based on the potential of the complementary bit line; and a second adjustment circuit, one end coupled to the bit line and the other end coupled to the complementary bit line, the second adjustment circuit being configured to adjust the potential of the complementary bit line in reverse phase based on the potential of the bit line, thereby accelerating the amplification speed of the sensing amplifier circuit by increasing the cross-coupled circuit.

[0014] Additionally, the first adjustment circuit includes: a first adjustment P-type transistor, the source of which is used to receive a high level, a drain coupled to a bit line, and a gate coupled to a complementary bit line; the second adjustment circuit includes: a second adjustment P-type transistor, the source of which is used to receive a high level, a drain coupled to a complementary bit line, and a gate coupled to a bit line.

[0015] Additionally, the first adjustment circuit includes: a first adjustment N-type transistor, the source of which is used to receive a low level, the drain of which is coupled to a bit line, and the gate of which is coupled to a complementary bit line; the second adjustment circuit includes: a second adjustment N-type transistor, the source of which is used to receive a low level, the drain of which is coupled to a complementary bit line, and the gate of which is coupled to a bit line.

[0016] In addition, the first adjustment circuit, coupled to the bit line, is configured to adjust the potential of the bit line in phase based on the potential of the bit line; the second adjustment circuit, coupled to the complementary bit line, is configured to adjust the potential of the complementary bit line in phase based on the potential of the complementary bit line. By increasing the in-phase coupling circuit, the amplification speed of the sensing amplifier circuit is accelerated.

[0017] Additionally, the first adjustment circuit includes: a first adjustment P-type transistor and a first inverter; the source of the first adjustment P-type transistor is used to receive a high level, and its drain is coupled to a bit line; the first inverter has its input coupled to the bit line and its output coupled to the gate of the first adjustment P-type transistor; the second adjustment circuit includes: a second adjustment P-type transistor and a second inverter; the source of the first adjustment P-type transistor is used to receive a high level, and its drain is coupled to a complementary bit line; the second inverter has its input coupled to the complementary bit line and its output coupled to the gate of the second adjustment P-type transistor.

[0018] Additionally, the first adjustment circuit includes: a first adjustment N-type transistor and a first inverter; the source of the first adjustment N-type transistor is used to receive a low level, and its drain is coupled to a bit line; the first inverter has its input coupled to the bit line and its output coupled to the gate of the first adjustment N-type transistor; the second adjustment circuit includes: a second adjustment N-type transistor and a second inverter; the source of the first adjustment N-type transistor is used to receive a low level, and its drain is coupled to a complementary bit line; the second inverter has its input coupled to the complementary bit line and its output coupled to the gate of the second adjustment N-type transistor.

[0019] In addition, the first regulating P-type transistor and the second regulating P-type transistor are tunneling field-effect transistors; in addition, the first regulating N-type transistor and the second regulating N-type transistor are tunneling field-effect transistors; the advantages of TFET transistors, such as low operating voltage and high switching current ratio, are used to reduce the power consumption of the first regulating circuit and the second regulating circuit.

[0020] This disclosure also provides a memory including the amplification circuit provided in the above embodiments to improve the efficiency of the sensing amplification circuit in amplifying the voltage difference between the bit line and the complementary bit line. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an amplifier circuit provided in an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the structure of a pull-up control module and a pull-down control module provided in an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of another pull-up control module and a pull-down control module provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of an amplifier circuit having a first adjustment circuit and a second adjustment circuit is provided in an embodiment of this disclosure;

[0026] Figure 5 An embodiment of this disclosure provides a method based on Figure 4A schematic diagram of the first and second adjustment circuits for the adjustment method shown.

[0027] Figure 6 Another embodiment of this disclosure based on Figure 4 A schematic diagram of the first and second adjustment circuits for the adjustment method shown.

[0028] Figure 7 A schematic diagram of another amplifier circuit having a first adjustment circuit and a second adjustment circuit is provided for one embodiment of this disclosure;

[0029] Figure 8 An embodiment of this disclosure provides a method based on Figure 7 A schematic diagram of the first and second adjustment circuits for the adjustment method shown.

[0030] Figure 9 Another embodiment of this disclosure based on Figure 7 A schematic diagram of the first and second adjustment circuits for the adjustment method shown.

[0031] Figure 10 This is a schematic diagram of the structure of a memory according to another embodiment of the present disclosure. Detailed Implementation

[0032] In traditional DRAM circuit structures, sensing amplification (SA) circuits are used to amplify the voltage difference between bit lines and complementary bit lines. As DRAM process dimensions continue to shrink, the power consumption of traditional sensing amplification circuit structures increases, making it increasingly difficult for them to meet market demands for high-performance DRAM. Therefore, it is necessary to improve the performance of sensing amplification circuits by changing their structure.

[0033] One embodiment of this disclosure provides an amplifier circuit that improves the efficiency of amplifying the voltage difference between a bit line and a complementary bit line through a novel sensing amplifier circuit structure.

[0034] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0035] Figure 1 This is a schematic diagram of the amplifier circuit provided in this embodiment. Figure 2This is a schematic diagram of the structure of a pull-up control module and a pull-down control module provided in this embodiment. Figure 3 This is a schematic diagram of another pull-up control module and a pull-down control module provided in this embodiment. Figure 4 This is a schematic diagram of the amplifier circuit with a first adjustment circuit and a second adjustment circuit provided in this embodiment. Figure 5 This embodiment provides a method based on Figure 4 The diagram shows the structure of the first and second adjustment circuits for the adjustment method shown. Figure 6 Another method based on this embodiment Figure 4 The diagram shows the structure of the first and second adjustment circuits for the adjustment method shown. Figure 7 This embodiment provides a schematic diagram of another amplifier circuit with a first adjustment circuit and a second adjustment circuit. Figure 8 This embodiment provides a method based on Figure 7 The diagram shows the structure of the first and second adjustment circuits for the adjustment method shown. Figure 9 Another method based on this embodiment Figure 7 The diagram shows the structure of the first and second adjustment circuits for the adjustment method shown. The following is a detailed description of the amplifier circuit provided in this embodiment, with reference to the accompanying drawings:

[0036] refer to Figure 1 An amplifier circuit, coupled to bit line BL and complementary bit line BLB, includes:

[0037] The pull-up module 101 has an input terminal coupled to the first node J1, an output terminal coupled to the bit line BL, and another output terminal coupled to the complementary bit line BLB. The first node J1 is used to receive the high level required for the potential pull-up.

[0038] The pull-up control module 111 has an input terminal for receiving a first control signal and an output terminal coupled to the pull-up module 101. The pull-up control module 111 is configured to drive the pull-up module 101 to pull up the potential of the bit line BL or the complementary bit line BLB based on the first control signal.

[0039] The pull-down module 102 has an input coupled to the second node J2, one output coupled to the bit line BL, and another output coupled to the complementary bit line BLB. The second node is used to receive the low level required for the potential pull-down.

[0040] The pull-down control module 112 has an input terminal for receiving a second control signal and an output terminal coupled to the pull-down module 102. The pull-down control module 112 is configured to drive the pull-down module 102 to pull down the potential of the bit line BL or the complementary bit line BLB based on the second control signal.

[0041] In this configuration, one of the first control signal and the second control signal is provided by bit line BL, and the other is provided by complementary bit line BLB.

[0042] It should be noted that if pull-up module 101 pulls up the potential of bit line BL, then pull-down module 102 pulls down the potential of complementary bit line BLB; conversely, if pull-up module 101 pulls up the potential of complementary bit line BLB, then pull-down module 102 pulls down the potential of bit line BL. Additionally, Figure 1 In the accompanying drawings, the first control signal is provided by the complementary bit line BLB and the second control signal is provided by the bit line BL. This does not constitute a limitation on this embodiment. In other embodiments, the second control signal may be provided by the complementary bit line BLB and the first control signal may be provided by the bit line BL.

[0043] Specifically, refer to Figure 2 and Figure 3 The pull-up module 101 includes a first P-type transistor and a second P-type transistor, and the pull-down module 102 includes a first N-type transistor and a second N-type transistor. The drain-coupled bit line BL of the first P-type transistor is coupled to the first node J1 at its source, and its gate is connected to the pull-up control module 111. The drain-coupled complementary bit line BLB of the second P-type transistor is coupled to the first node J1 at its source, and its gate is connected to the pull-up control module 111. The drain-coupled bit line BL of the first N-type transistor is coupled to the second node J2 at its source, and its gate is connected to the pull-down control module 112. The drain-coupled complementary bit line BLB of the second N-type transistor is coupled to the second node J2 at its source, and its gate is connected to the pull-down control module 112.

[0044] In some embodiments, the first P-type transistor and the second P-type transistor are tunneling field-effect transistors (TFETs); in some embodiments, the first N-type transistor and the second N-type transistor are tunneling field-effect transistors; in some embodiments, the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are tunneling field-effect transistors.

[0045] For an NTFET (N-type TFET transistor), the substrate is lightly doped with N-type, the source region is heavily doped with P-type, and the drain region is heavily doped with N-type; when Vgs (gate-source voltage) > Vth (threshold voltage), the NTFET transistor conducts; for a PTFET (P-type TFET transistor), the substrate is lightly doped with P-type, the source region is heavily doped with N-type, and the drain region is heavily doped with P-type; when Vgs (gate-source voltage) < Vth (threshold voltage), the PTFET transistor conducts; in the off state, the P-I-N diode of the tunneling field-effect transistor is always reverse-biased, resulting in a thick tunneling barrier between different energy bands in the working region, and the thick tunneling barrier leads to a reduced tunneling probability, thereby generating a very small off-state current, thus reducing the leakage current generated by the transistor.

[0046] Taking the NTFET transistor as an example, for the NTFET, the substrate is lightly doped with N-type. As the gate voltage increases, it causes the accumulation of the N region. The surface tunneling junction is located at the junction of the gate oxide (Gox) / channel / P-doped region. In the NTFET, when an appropriate bias voltage is applied, electrons tunnel from the P-type doped region into the channel and then flow into the N-type doped region. When the TFET transistor is in the on state, the tunneling barrier width decreases, and charge carriers tunnel from the valence band of the source region to the conduction band of the channel region and then reach the conduction band of the drain region. This band-to-band tunneling process is the main reason for the injection of carriers from the source region. Due to the existence of the BTBT (Band ToBand Tunneling) barrier, the on-state and off-state currents of the TFET transistor are always lower than those of the traditional MOSFET transistor. The advantages of the TFET such as low operating voltage, low subthreshold swing, and high switching current ratio are used to reduce the power consumption of the sense amplifier circuit.

[0047] For the first node J1 and the second node J2, continue to refer to Figure 2 and Figure 3 , in some embodiments, the amplifier circuit further includes: a first switching transistor K1 and a second switching transistor K2, wherein the drain of the first switching transistor K1 is coupled to the first node J1, the source is used to receive the high level Vcc, and the gate is used to receive the first switching signal. The first switching transistor K1 is configured to provide the high level Vcc to the first node J1 based on the first switching signal; the drain of the second switching transistor K2 is coupled to the second node J2, the source is used to receive the low level Vss, and the gate is used to receive the second switching signal. The second switching transistor K2 is configured to provide the low level Vss to the second node J2 based on the second switching signal.

[0048] Furthermore, the first switching transistor K1 and the second switching transistor K2 are tunneling field-effect transistors; by using TFET transistors as switches to receive the high level Vcc required for the potential pull-up of the sensing amplifier circuit and the low level Vss required for the potential pull-down, the power consumption of the sensing amplifier circuit is reduced by taking advantage of the low operating voltage and high switching current ratio of TFET transistors.

[0049] For the pull-up control module 111 and the pull-down control module 112, in some embodiments, if the first control signal is provided based on bit line BL and the second control signal is provided based on complementary bit line BLB, refer to Figure 2 The pull-up control module 111 includes a first pull-up inverter and a second pull-up inverter; the pull-down control module 112 includes a first pull-down inverter and a second pull-down inverter; wherein, the input terminal of the first pull-up inverter is connected to the gate of a first P-type transistor, and the output terminal is connected to the gate of a second P-type transistor; the input terminal of the second pull-up inverter is connected to bit line BL, and the output terminal is connected to the input terminal of the first pull-up inverter; the input terminal of the first pull-down inverter is connected to the gate of a second N-type transistor, and the output terminal is connected to the gate of the first N-type transistor; the input terminal of the second pull-down inverter is connected to the complementary bit line BLB, and the output terminal is connected to the input terminal of the first pull-up inverter. In other embodiments, if the first control signal is provided based on the complementary bit line BLB, and the second control signal is provided based on bit line BL, refer to... Figure 3 The pull-up control module 111 includes a pull-up inverter; the pull-down control module 112 includes a pull-down inverter; wherein, the input terminal of the pull-up inverter and the gate of the second P-type transistor are connected to the complementary bit line BLB, the output terminal of the pull-up inverter is connected to the gate of the first P-type transistor, the input terminal of the pull-down inverter and the gate of the first N-type transistor are connected to the bit line BL, and the output terminal of the pull-down inverter is connected to the gate of the second N-type transistor.

[0050] Specifically, if bit line BL is greater than a preset level, then complementary bit line BLB is less than the preset level. The first P-type transistor is turned on, the second P-type transistor is turned off, and bit line BL is coupled to a high level Vcc to pull it up to the high level Vcc. The first N-type transistor is turned off, the second N-type transistor is turned on, and complementary bit line BLB is coupled to a low level Vss to pull it down to the low level Vss. If bit line BL is at a low level Vss, then complementary bit line BLB is greater than the preset level. The first P-type transistor is turned off, the second P-type transistor is turned off, and complementary bit line BLB is coupled to a high level Vcc to pull it up to the high level Vcc. The first N-type transistor is turned on, the second N-type transistor is turned off, and bit line BL is coupled to a low level Vss to pull it down to the low level Vss.

[0051] refer to Figure 4In some embodiments, the amplification circuit further includes: a first adjustment circuit 201, one end coupled to bit line BL and the other end coupled to complementary bit line BLB, the first adjustment circuit 201 being configured to adjust the potential of the bit line in reverse phase based on the potential of complementary bit line BLB; and a second adjustment circuit 202, one end coupled to complementary bit line BLB, the second adjustment circuit 202 being configured to adjust the potential of complementary bit line BLB in reverse phase based on the potential of bit line BL, thereby accelerating the amplification speed of the sensing amplification circuit by increasing the cross-coupled circuit.

[0052] In one example, refer to Figure 5 The first adjustment circuit 201 includes a first adjustment P-type transistor T1, the source of which is used to receive a high level Vcc, the drain is coupled to a bit line BL, and the gate is coupled to a complementary bit line BLB; the second adjustment circuit 202 includes a second adjustment P-type transistor T2, the source of which is used to receive a high level Vcc, the drain is coupled to a complementary bit line BLB, and the gate is coupled to a bit line BL.

[0053] If bit line BL is at a high level (Vcc), then the complementary bit line BLB is at a low level (Vss). At this time, the first regulating P-type transistor T1 is turned on, coupling bit line BL to the high level (Vcc) through the turned-on transistor T1, thereby accelerating the amplification speed of the sensing amplifier circuit. If bit line BL is at a low level (Vss), then the complementary bit line BLB is at a high level (Vcc). At this time, the second regulating P-type transistor T2 is turned on, coupling the complementary bit line BLB to the high level (Vcc) through the turned-on transistor T2, thereby accelerating the amplification speed of the sensing amplifier circuit.

[0054] In one example, refer to Figure 6 The first adjustment circuit 201 includes a first adjustment N-type transistor T1, the source of which is used to receive a low level Vss, a drain-coupled bit line BL, and a gate-coupled complementary bit line BLB; the second adjustment circuit 202 includes a second adjustment N-type transistor T2, the source of which is used to receive a low level Vss, a drain-coupled complementary bit line BLB, and a gate-coupled bit line BL.

[0055] If bit line BL is at a high level (Vcc), then the complementary bit line BLB is at a low level (Vss). At this time, the second regulating N-type transistor T2 is turned on, coupling the complementary bit line BLB to the low level Vss through the turned-on second regulating N-type transistor T2, thereby accelerating the amplification speed of the sensing amplifier circuit. If bit line BL is at a low level (Vss), then the complementary bit line BLB is at a high level (Vcc). At this time, the first regulating N-type transistor T1 is turned on, coupling the bit line BL to the low level Vss through the turned-on first regulating N-type transistor T1, thereby accelerating the amplification speed of the sensing amplifier circuit.

[0056] refer to Figure 7 In other embodiments, the amplification circuit further includes: a first adjustment circuit 201 coupled to a bit line BL, the first adjustment circuit 201 being configured to adjust the potential of the bit line BL in phase based on the potential of the bit line BL; and a second adjustment circuit 202 coupled to a complementary bit line BLB, the second adjustment circuit BLB being configured to adjust the potential of the complementary bit line BLB in phase based on the potential of the complementary bit line BLB, thereby accelerating the amplification speed of the sensing amplifier circuit by increasing the in-phase coupling circuit.

[0057] In one example, refer to Figure 8 The first adjustment circuit 201 includes a first adjustment P-type transistor T1 and a first inverter F1. The source of the first adjustment P-type transistor T1 is used to receive a high level Vcc, and the drain is coupled to the bit line BL. The input terminal of the first inverter F1 is coupled to the bit line BL, and the output terminal is coupled to the gate of the first adjustment P-type transistor T1. The second adjustment circuit 202 includes a second adjustment P-type transistor T2 and a second inverter F2. The source of the second adjustment P-type transistor T2 is used to receive a high level Vcc, and the drain is coupled to the complementary bit line BLB. The input terminal of the second inverter F2 is coupled to the complementary bit line BLB, and the output terminal is coupled to the gate of the second adjustment P-type transistor T2.

[0058] If bit line BL is at a high level (Vcc), then the complementary bit line BLB is at a low level (Vss). At this time, the first regulating P-type transistor T1 is turned on, coupling bit line BL to the high level (Vcc) through the turned-on transistor T1, thereby accelerating the amplification speed of the sensing amplifier circuit. If bit line BL is at a low level (Vss), then the complementary bit line BLB is at a high level (Vcc). At this time, the second regulating P-type transistor T2 is turned on, coupling the complementary bit line BLB to the high level (Vcc) through the turned-on transistor T2, thereby accelerating the amplification speed of the sensing amplifier circuit.

[0059] In one example, refer to Figure 9 The first adjustment circuit 201 includes a first adjustment N-type transistor T1 and a first inverter F1. The source of the first adjustment N-type transistor T1 is used to receive a low level Vss, and the drain is coupled to the bit line BL. The input terminal of the first inverter F1 is coupled to the bit line BL, and the output terminal is coupled to the gate of the first adjustment N-type transistor T1. The second adjustment circuit 202 includes a second adjustment N-type transistor T2 and a second inverter F2. The source of the second adjustment N-type transistor T2 is used to receive a low level Vss, and the drain is coupled to the complementary bit line BLB. The input terminal of the second inverter F2 is coupled to the complementary bit line BLB, and the output terminal is coupled to the gate of the second adjustment N-type transistor T2.

[0060] If bit line BL is at a high level (Vcc), then the complementary bit line BLB is at a low level (Vss). At this time, the second regulating N-type transistor T2 is turned on, coupling the complementary bit line BLB to the low level Vss through the turned-on second regulating N-type transistor T2, thereby accelerating the amplification speed of the sensing amplifier circuit. If bit line BL is at a low level (Vss), then the complementary bit line BLB is at a high level (Vcc). At this time, the first regulating N-type transistor T1 is turned on, coupling the bit line BL to the low level Vss through the turned-on first regulating N-type transistor T1, thereby accelerating the amplification speed of the sensing amplifier circuit.

[0061] for Figure 5 and Figure 8 In some embodiments of the first adjustment circuit 201 and the second adjustment circuit 202 shown, the first adjustment P-type transistor T1 and the second adjustment P-type transistor T2 are tunneling field-effect transistors; for Figure 6 and Figure 9 In some embodiments of the first regulating circuit 201 and the second regulating circuit 202 shown, the first regulating N-type transistor T1 and the second regulating N-type transistor T2 are tunneling field-effect transistors; the advantages of the low operating voltage and high switching current ratio of the TFET transistor are used to reduce the power consumption of the first regulating circuit 201 and the second regulating circuit 202.

[0062] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0063] It should be noted that the features disclosed in the amplifier circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new amplifier circuit embodiments.

[0064] Another embodiment of this disclosure provides a memory including the amplification circuit provided in the above embodiments to improve the efficiency of the sensing amplification circuit in amplifying the voltage difference between the bit line and the complementary bit line.

[0065] Figure 10 This is a schematic diagram of the memory structure in this embodiment. The memory provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0066] refer to Figure 10Memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0067] The memory device can input / output data via the data line DQ in response to control commands CMD and address signals received from an external device, such as a memory controller. The memory device includes a memory cell array 10, a command decoder 30, control logic 40, an address buffer 20, a row decoder 21, a column decoder 22, an amplifier circuit 50, and a data input / output circuit 60.

[0068] The memory cell array 10 includes a plurality of memory cells provided in a matrix format arranged in multiple rows and columns. The memory cell array 10 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL can be connected to rows of the memory cells, and the plurality of bit lines BL can be connected to columns of the memory cells.

[0069] Command decoder 30 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc. received from external devices such as memory controllers, and can allow control logic 40 to generate control signals corresponding to control command CMD.

[0070] The control command (CMD) can include activation commands, read commands, write commands, precharge commands, etc.

[0071] Address buffer 20 receives address signals from the memory controller, which is an external device. Address signals include a row address RA for addressing rows of the memory cell array 10 and a column address CA for addressing columns of the memory cell array 10. Address buffer 120 can send the row address RA to row decoder 21 and the column address CA to column decoder 22.

[0072] The row decoder 21 can select any one of the multiple word lines WL connected to the memory cell array 10. The row decoder 21 can decode the row address RA received from the address buffer 120, select any word line corresponding to the row address RA, and activate the selected word line WL.

[0073] The column decoder 22 can select a predetermined number of bit lines from a plurality of bit lines BL of the memory cell array 10. The column decoder 22 can decode the column address CA received from the address buffer 120 and select the predetermined number of bit lines BL corresponding to the received column address CA.

[0074] Amplifier circuit 50 is connected to the bit line BL of memory cell array 10. Amplifier circuit 50 can read the voltage change of selected bit line among multiple bit lines BL, amplify the voltage change, and output the amplified voltage change.

[0075] The data input / output circuit 60 can output data via the data line DQ based on the voltage read and amplified by the amplifier circuit 50.

[0076] Amplifier circuit 50 can receive isolation signal ISO and offset cancellation signal OC from control logic 40. Amplifier circuit 50 can perform offset cancellation operation in response to isolation signal ISO and offset cancellation signal OC. For example, offset represents the characteristic difference between the semiconductor devices constituting amplifier circuit 50, such as the difference between the threshold voltages of different semiconductor devices.

[0077] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. An amplifier circuit coupled to bit lines and complementary bit lines, characterized in that, include: The pull-up module has an input terminal coupled to a first node, an output terminal coupled to the bit line, and another output terminal coupled to the complementary bit line. The first node is used to receive the high level required for the potential pull-up. The pull-up control module has an input terminal for receiving a first control signal and an output terminal coupled to the pull-up module. The pull-up control module is configured to drive the pull-up module to pull up the potential of the bit line or the complementary bit line based on the first control signal. The pull-down module has an input coupled to a second node, an output coupled to the bit line, and another output coupled to the complementary bit line. The second node is used to receive the low level required for the potential pull-down. The pull-down control module has an input terminal for receiving a second control signal and an output terminal coupled to the pull-down module. The pull-down control module is configured to drive the pull-down module to pull down the potential of the bit line or the complementary bit line based on the second control signal. Wherein, one of the first control signal and the second control signal is provided by the bit line only, and the other is provided by the complementary bit line only; The pull-up module includes: a first P-type transistor and a second P-type transistor; The pull-down module includes: a first N-type transistor and a second N-type transistor; The drain of the first P-type transistor is coupled to the bit line, the source is coupled to the first node, and the gate is connected to the pull-up control module. The drain of the second P-type transistor is coupled to the complementary bit line, the source is coupled to the first node, and the gate is connected to the pull-up control module. The drain of the first N-type transistor is coupled to the bit line, the source is coupled to the second node, and the gate is connected to the pull-down control module; The drain of the second N-type transistor is coupled to the complementary bit line, the source is coupled to the second node, and the gate is connected to the pull-down control module.

2. The amplifier circuit according to claim 1, characterized in that, The first P-type transistor and the second P-type transistor are tunneling field-effect transistors.

3. The amplifier circuit according to claim 1 or 2, characterized in that, The first N-type transistor and the second N-type transistor are tunneling field-effect transistors.

4. The amplifier circuit according to claim 1, characterized in that, include: The pull-up control module includes: a first pull-up inverter and a second pull-up inverter; The pull-down control module includes: a first pull-down inverter and a second pull-down inverter; The input terminal of the first pull-up inverter is connected to the gate of the first P-type transistor, and the output terminal is connected to the gate of the second P-type transistor. The input terminal of the second pull-up inverter is connected to the bit line, and the output terminal is connected to the input terminal of the first pull-up inverter. The input terminal of the first pull-down inverter is connected to the gate of the second N-type transistor, and the output terminal is connected to the gate of the first N-type transistor. The input terminal of the second pull-down inverter is connected to the complementary bit line, and the output terminal is connected to the input terminal of the first pull-up inverter.

5. The amplifier circuit according to claim 1, characterized in that, include: The pull-up control module includes: a pull-up inverter; The pull-down control module includes: a pull-down inverter; The input terminal of the pull-up inverter and the gate of the second P-type transistor are connected to the complementary bit line, and the output terminal of the pull-up inverter is connected to the gate of the first P-type transistor. The input terminal of the pull-down inverter and the gate of the first N-type transistor are connected to the bit line, and the output terminal of the pull-down inverter is connected to the gate of the second N-type transistor.

6. The amplifier circuit according to claim 1, characterized in that, Also includes: A first switching transistor, with its drain coupled to the first node, its source used to receive the high level, and its gate used to receive a first switching signal, is configured to provide the high level to the first node based on the first switching signal. The second switching transistor, with its drain coupled to the second node, its source for receiving the low level, and its gate for receiving a second switching signal, is configured to provide the low level to the second node based on the second switching signal.

7. The amplifier circuit according to claim 6, characterized in that, The first switching transistor and the second switching transistor are tunneling field-effect transistors.

8. The amplifier circuit according to claim 1, characterized in that, Also includes: A first adjustment circuit is coupled at one end to the bit line and at the other end to the complementary bit line. The first adjustment circuit is configured to adjust the potential of the bit line in reverse phase based on the potential of the complementary bit line. A second adjustment circuit is coupled at one end to the bit line and at the other end to the complementary bit line. The second adjustment circuit is configured to adjust the potential of the complementary bit line in reverse phase based on the potential of the bit line.

9. The amplifier circuit according to claim 8, characterized in that, include: The first adjustment circuit includes: a first adjustment P-type transistor, wherein the source of the first adjustment P-type transistor is used to receive the high level, the drain is coupled to the bit line, and the gate is coupled to the complementary bit line; The second adjustment circuit includes: a second adjustment P-type transistor, wherein the source of the second adjustment P-type transistor is used to receive the high level, the drain is coupled to the complementary bit line, and the gate is coupled to the bit line.

10. The amplifier circuit according to claim 8, characterized in that, include: The first adjustment circuit includes: a first adjustment N-type transistor, wherein the source of the first adjustment N-type transistor is used to receive the low level, the drain is coupled to the bit line, and the gate is coupled to the complementary bit line; The second adjustment circuit includes: a second adjustment N-type transistor, wherein the source of the second adjustment N-type transistor is used to receive the low level, the drain is coupled to the complementary bit line, and the gate is coupled to the bit line.

11. The amplifier circuit according to claim 1, characterized in that, Also includes: A first adjustment circuit is coupled to the bit line, and the first adjustment circuit is configured to adjust the potential of the bit line based on the potential of the bit line. A second adjustment circuit is coupled to the complementary bit line, and the second adjustment circuit is configured to adjust the potential of the complementary bit line in phase based on the potential of the complementary bit line.

12. The amplifier circuit according to claim 11, characterized in that, include: The first adjustment circuit includes: a first adjustment P-type transistor and a first inverter; The source of the first regulating P-type transistor is used to receive the high level, and the drain is coupled to the bit line; The first inverter has its input terminal coupled to the bit line and its output terminal coupled to the gate of the first adjustable P-type transistor; The second adjustment circuit includes: a second adjustment P-type transistor and a second inverter; The source of the first regulating P-type transistor is used to receive the high level, and the drain is coupled to the complementary bit line; The second inverter has its input coupled to the complementary bit line and its output coupled to the gate of the second adjustable P-type transistor.

13. The amplifier circuit according to claim 11, characterized in that, include: The first adjustment circuit includes: a first adjustment N-type transistor and a first inverter; The source of the first regulating N-type transistor is used to receive the low level, and the drain is coupled to the bit line; The first inverter has its input terminal coupled to the bit line and its output terminal coupled to the gate of the first adjustable N-type transistor; The second adjustment circuit includes: a second adjustment N-type transistor and a second inverter; The source of the first regulating N-type transistor is used to receive the low level, and the drain is coupled to the complementary bit line; The second inverter has its input coupled to the complementary bit line and its output coupled to the gate of the second adjustable N-type transistor.

14. The amplifier circuit according to claim 9 or 12, characterized in that, The first regulated P-type transistor and the second regulated P-type transistor are tunneling field-effect transistors.

15. The amplifier circuit according to claim 10 or 13, characterized in that, The first regulated N-type transistor and the second regulated N-type transistor are tunneling field-effect transistors.

16. A memory, characterized in that, Includes the amplifier circuit described in any one of claims 1 to 15.

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