Semiconductor device and method of manufacturing the same

Abstract

A method of fabricating a semiconductor device includes forming a dielectric layer stack including a first oxide layer and a second oxide layer on the first oxide layer. An opening is formed in the dielectric layer stack, the opening including a first portion and a second portion, the first portion exposing a sidewall of the first oxide layer, and the second portion exposing a sidewall of the second oxide layer. A sacrificial layer is formed on a top surface of the dielectric layer stack and along the sidewall of the first oxide layer and the sidewall of the second oxide layer in the opening. A first etch process is performed to remove a first portion of the sacrificial layer along the sidewall of the first oxide layer. A second etch process is performed to widen the first portion of the opening. A second portion of the sacrificial layer along the sidewall of the second oxide layer and on the top surface of the dielectric layer stack is removed. A capacitor is formed in the opening of the dielectric layer stack. The bottom of the capacitor of some embodiments of the present disclosure is widened, thus becoming more stable.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The memory structure comprises multiple capacitors and transistors arranged in an array. Transistors connected to word lines can be turned on or off. When a transistor is on, it can be connected to a capacitor to charge or discharge it. Data can be written to or read from the bit lines connected to the transistors. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method of manufacturing a semiconductor device, comprising forming a dielectric layer stack including a first oxide layer and a second oxide layer on the first oxide layer. An opening is formed in the dielectric layer stack, wherein the opening includes a first portion and a second portion, the first portion exposing a plurality of sidewalls of the first oxide layer, and the second portion exposing a plurality of sidewalls of the second oxide layer. A sacrificial layer is formed on the top surface of the dielectric layer stack and along the sidewalls of the first oxide layer and the second oxide layer in the opening. A first etching process is performed to remove the first portion of the sacrificial layer along the sidewalls of the first oxide layer. A second etching process is performed to widen the first portion of the opening. The second portion of the sacrificial layer along the sidewalls of the second oxide layer and on the top surface of the dielectric layer stack is removed. After removing the second portion of the sacrificial layer, a capacitor is formed in the opening of the dielectric layer stack.

[0004] In some embodiments, forming a dielectric layer stack includes forming a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer and a third nitride layer in sequence from bottom to top.

[0005] In some embodiments, the first oxide layer is doped with a dopant, and the dopant comprises boron, phosphorus, or a combination thereof.

[0006] In some embodiments, the method further includes adjusting the concentration of dopant during the formation of the dielectric layer stack such that the concentration of dopant in the first oxide layer decreases as it moves further away from the bottom surface of the dielectric layer stack.

[0007] In some embodiments, during the formation of the sacrificial layer, the sacrificial layer along the sidewall of the second oxide layer is thicker than the sacrificial layer along the sidewall of the first oxide layer.

[0008] In some implementations, the first etching process also laterally and partially removes the sacrificial layer along the sidewalls of the second oxide layer.

[0009] In some implementations, the method further includes controlling the timing of the first etching process to remove a sacrificial layer along the sidewalls of the first oxide layer.

[0010] In some implementations, the first etchant used in the first etching process etches the sacrificial layer faster than the first oxide layer.

[0011] In some embodiments, the second etchant used in the second etching process etches the first oxide layer faster than the sacrificial layer.

[0012] Some embodiments disclosed herein provide a method of manufacturing a semiconductor device, comprising forming a dielectric layer stack including, from bottom to top, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer. An opening is formed in the dielectric layer stack, the opening including a first portion and a second portion, the first portion exposing a plurality of sidewalls of the first oxide layer, and the second portion exposing a plurality of sidewalls of the second oxide layer, wherein the width of the second portion of the opening is greater than the width of the first portion of the opening. The first portion of the opening is widened such that the sidewalls of the first oxide layer are substantially perpendicular to the bottom surface of the dielectric layer stack. After widening the first portion of the opening, a capacitor is formed in the opening of the dielectric layer stack.

[0013] In some embodiments, forming a capacitor in an opening of the dielectric layer stack includes forming a bottom electrode layer along the sidewalls of the opening. A portion of the third nitride layer and the bottom electrode layer is removed to form a first opening at a corner exposing a second oxide layer. The second oxide layer is removed from the first opening. A second opening is formed in the second nitride layer to expose a portion of the first oxide layer. The first oxide layer is removed from the second opening. A high-dielectric-constant dielectric layer is formed along the sidewalls of the bottom electrode layer. A top electrode layer is formed along the sidewalls of the high-dielectric-constant dielectric layer.

[0014] In some embodiments, the method further includes forming a plurality of semiconductor layers between the first nitride layer and the second nitride layer and between the second nitride layer and the third nitride layer.

[0015] In some implementations, the method further includes forming a semiconductor layer that contacts the top electrode layer.

[0016] In some embodiments, the slope of the sidewall of the bottom electrode layer between the first nitrided layer and the second nitrided layer is different from the slope of the sidewall of the bottom electrode layer between the second nitrided layer and the third nitrided layer.

[0017] In some implementations, a high dielectric constant dielectric layer is placed between the first nitride layer and the second nitride layer.

[0018] Some embodiments of this disclosure provide a semiconductor device comprising a plurality of dielectric layers and a capacitor. The dielectric layers are arranged from bottom to top and spaced apart from each other. The capacitor contacts a plurality of sidewalls of the dielectric layers, and an intermediate layer of the dielectric layers defines an upper and a lower portion of the capacitor, wherein the upper sidewall of the capacitor is inclined relative to one of the dielectric layers than the lower sidewall of the capacitor.

[0019] In some implementations, the lower sidewall of the capacitor is substantially perpendicular to one of the dielectric layers.

[0020] In some implementations, the semiconductor device includes multiple semiconductor layers vertically positioned between dielectric layers.

[0021] In some implementations, the capacitor contacts multiple bottom surfaces of the dielectric layer.

[0022] In some implementations, the capacitor contacts multiple top surfaces of the dielectric layer.

[0023] Some embodiments disclosed herein relate to the process of semiconductor devices in memory devices. Additional processes can be used to widen the bottom of the opening used to house the capacitor. Therefore, the bottom of the capacitor becomes wider, and the capacitor structure of some embodiments disclosed herein becomes more stable. Attached Figure Description

[0024] Figures 1 to 14 A cross-sectional view is shown of an intermediate stage in the manufacturing process of a semiconductor device according to some embodiments disclosed herein. Detailed Implementation

[0025] The following describes several embodiments of this disclosure with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0026] Some embodiments disclosed herein relate to the process of semiconductor devices in memory devices. Additional processes can be used to widen the bottom of the opening used to house the capacitor. Therefore, the bottom of the capacitor becomes wider, and the capacitor structure of some embodiments disclosed herein becomes more stable.

[0027] Figures 1 to 14 This illustration shows a cross-sectional view of an intermediate stage in the manufacturing process of a semiconductor device according to some embodiments disclosed herein. Reference Figure 1A dielectric layer stack 100 is formed, wherein the dielectric layer stack 100 includes a first oxide layer 104 and a second oxide layer 108 on the first oxide layer 104. More specifically, forming the dielectric layer stack 100 includes forming a first nitride layer 102, a first oxide layer 104, a second nitride layer 106, a second oxide layer 108, and a third nitride layer 110 sequentially from bottom to top. Thus, the first nitride layer 102 is below the first oxide layer 104, the second nitride layer 106 is between the first oxide layer 104 and the second oxide layer 108, and the third nitride layer 110 is on the second oxide layer 108. The dielectric layer stack 100 may be formed on a layer containing contacts, transistors, or other similar components. Therefore, capacitors subsequently formed in the dielectric layer stack 100 are connected to underlying components, such as transistors. In some embodiments, the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110 comprise silicon nitride, and the first oxide layer 104 and the second oxide layer 108 comprise silicon oxide. In some embodiments, the thickness of the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110 is less than the thickness of the first oxide layer 104 and the second oxide layer 108.

[0028] When the first oxide layer 104 is formed, it is doped with a dopant comprising boron, phosphorus, or a combination thereof. The dopant weakens the silicon oxide bonds in the first oxide layer 104, making it easier to etch in subsequent etching processes. For example, the dopant concentration of the first oxide layer 104 decreases with increasing distance from the bottom surface 102B of the dielectric layer stack 100. At high dopant concentrations, the silicon oxide bonds are weakened, therefore the first oxide layer 104 with a high dopant concentration is easier to etch than the first oxide layer 104 with a low dopant concentration. The dopant concentration can be adjusted during the formation of the first oxide layer 104 of the dielectric layer stack 100. In some embodiments, the first oxide layer 104 is formed by chemical vapor deposition (CVD), and silicon-containing chemicals (e.g., tetraethyl orthosilicate (TEOS)), boron-containing chemicals (e.g., triethylborane (TEB), diborane), and phosphorus-containing chemicals (e.g., trimethyl phosphate (TMPO)) can be used. The first oxide layer 104 is made of boro-phospho-silicate glass (BPSG), which is silicon oxide doped with boron and phosphorus. The dopant concentration can be adjusted by changing the flow rates of the silicon-containing chemicals, boron-containing chemicals, and phosphorus-containing chemicals. On the other hand, the second oxide layer 108 does not contain dopant, or the dopant concentration of the second oxide layer 108 is lower than that of the first oxide layer 104.

[0029] refer to Figure 2 After forming the dielectric layer stack 100, openings 120 are formed in the dielectric layer stack 100. Each opening 120 includes a first portion 122 and a second portion 124, the first portion 122 exposing the sidewalls 104S of the first oxide layer 104, and the second portion 124 exposing the sidewalls 108S of the second oxide layer 108. The openings 120 can be formed by any suitable process, such as dry etching, wet etching, or the like. In a cross-sectional view, the openings 120 are tapered. That is, in a cross-sectional view, the width of the second portion 124 of the opening 120 is greater than the width of the first portion 122 of the opening 120.

[0030] refer to Figure 3 On the top surface 110T of the dielectric layer stack 100 (e.g.) Figure 4 A sacrificial layer 130 is formed on the first oxide layer 104 and along the sidewalls of the second oxide layer 108 in the opening 120. The sacrificial layer 130 includes a first portion 132 along the sidewall 104S of the first oxide layer 104 and a second portion 134 along the sidewall 108S of the second oxide layer 108. During the formation of the sacrificial layer 130, the second portion 134 of the sacrificial layer 130 along the sidewall 108S of the second oxide layer 108 is thicker than the first portion 132 of the sacrificial layer 130 along the sidewall 104S of the first oxide layer 104. In other words, the thickness of the sacrificial layer 130 increases with distance from the bottom surface 102B of the dielectric layer stack 100. The smaller thickness of the first portion 132 of the sacrificial layer 130 may be due to the narrow gap of the first portion 122, making it difficult for the material of the sacrificial layer 130 to be deposited in the first portion 122 of the opening 120. In some embodiments, the second portion 134 of the sacrificial layer 130 is about 1 nanometer to about 2 nanometers thicker than the first portion 132 of the sacrificial layer 130. The sacrificial layer 130 may be made of a material different from that of the dielectric layer stack 100, such as titanium nitride. In some embodiments, the sacrificial layer 130 is also formed on a layer (e.g., a contact layer) beneath the dielectric layer stack 100.

[0031] refer to Figure 4A first etching process is performed to remove a first portion 132 of the sacrificial layer 130 along the sidewalls 104S of the first oxide layer 104. The first etchant used in the first etching process etches the sacrificial layer 130 at a rate faster than the first oxide layer 104, or substantially does not etch the first oxide layer 104. In some embodiments, the first etchant may be a mixture of sulfuric acid and hydrogen peroxide. During the first etching, the timing of the first etching process is controlled to remove the first portion 132 of the sacrificial layer 130 along the sidewalls 104S of the first oxide layer 104. The first etching process also laterally and partially removes a second portion 134 of the sacrificial layer 130 along the sidewalls 108S of the second oxide layer 108. Because the second portion 134 of the sacrificial layer 130 is thicker than the first portion 132 of the sacrificial layer 130, it is not completely removed when the sidewalls 104S are exposed. Therefore, after the first etching process, only the sidewalls 104S of the first oxide layer 104 are exposed. After the first etching process, the sidewalls of the first nitride layer 102 and a portion of the layer (e.g., the contact layer) beneath the dielectric layer stack 100 are also exposed.

[0032] refer to Figure 5 A second etching process is performed to widen the first portion 122 of the opening 120. The second etchant used in the second etching process etches the first oxide layer 104 faster than the sacrificial layer 130, or substantially does not etch the sacrificial layer 130. In some embodiments, the second etchant may be diluted hydrofluoric acid. Because the sacrificial layer 130 is not etched or is barely etched in the second etching process, the second portion 134 of the sacrificial layer 130 may act as an etching mask during the second etching process. After the second etching process, the sidewalls 104S of the first oxide layer 104 exposed in the first portion 122 of the opening 120 are substantially perpendicular to the bottom surface 102B of the dielectric layer stack 100 (e.g., ...). Figure 4 As shown), the second portion 124 of the opening 120 remains conical. In other words, relative to the bottom surface 102B of the dielectric layer stack 100 (as shown), the second portion 124 of the opening 120 remains conical. Figure 4 As shown), the sidewalls of the second oxide layer 108 are more inclined than the sidewalls 104S of the first oxide layer 104 exposed to the first portion 122 of the opening 120. After widening the first portion 122 of the opening 120, in subsequent processes, because the first portion 122 of the opening 120 is wider, it is easier to fill the capacitor material in the first portion 122 of the opening 120. Because the widened first portion 122 of the opening 120 can provide sufficient support, the capacitor (such as...) formed in the opening 120... Figure 14 The 140 capacitor in the structure can be relatively stable.

[0033] refer to Figure 6The sacrificial layer 130 is removed along the sidewall 108S of the second oxide layer 108 and the second portion 134 on the top surface 110T of the dielectric layer stack 100. The etchant used to remove the second portion 134 of the sacrificial layer 130 is similar to or the same as that used to remove the first portion 132 of the sacrificial layer 130. After removing the second portion 134 of the sacrificial layer 130, the sidewalls of the second oxide layer 108 are more inclined than the sidewalls 104S of the first oxide layer 104 relative to the bottom surface 102B of the dielectric layer stack 100.

[0034] refer to Figures 7 to 14 After removing the second portion 134 of the sacrificial layer 130, capacitor 140 is formed. For more details, see [reference needed]. Figure 7 A bottom electrode layer 142 is formed along the sidewall of the opening 120. The slope of the sidewall of the bottom electrode layer 142 between the first nitride layer 102 and the second nitride layer 106 is different from the slope of the sidewall of the bottom electrode layer 142 between the second nitride layer 106 and the third nitride layer 110. The bottom electrode layer 142 along the sidewall 108S of the second oxide layer 108 is more inclined than the bottom electrode layer 142 along the sidewall 104S of the first oxide layer 104 relative to the bottom surface 102B of the dielectric layer stack 100. In some embodiments, the bottom electrode layer 142 does not cover the top surface of the dielectric layer stack 100 or the layers (e.g., contact layers) beneath the dielectric layer stack 100. In some embodiments, the bottom electrode layer 142 is made of any suitable material, such as titanium nitride.

[0035] refer to Figure 8 The third nitride layer 110 and a portion of the bottom electrode layer 142 are removed. More specifically, the third nitride layer 110 and a portion of the bottom electrode layer 142 are removed to form a first opening at the corner exposing the second oxide layer 108. (See reference...) Figure 9 The second oxide layer 108 is removed. For example, an etching process can be performed to remove the oxide layer formed on... Figure 8 The second oxide layer 108 is removed through the first opening. After the removal of the second oxide layer 108, a space S1 is formed between the second nitride layer 106 and the third nitride layer 110.

[0036] refer to Figure 10 This forms a second opening in the second nitrided layer 106, exposing a portion of the first oxide layer 104. (See reference) Figure 11 The first oxide layer 104 is removed. For example, an etching process can be performed to remove the oxide layer formed on the oxide layer. Figure 10The first oxide layer 104 is removed through the second opening. After the first oxide layer 104 is removed, a space S2 is formed between the first nitride layer 102 and the second nitride layer 106, and an opening in the second nitride layer 106 connects spaces S1 and S2. The bottom electrode layer 142 connects the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110.

[0037] refer to Figure 12 A high-dielectric-constant dielectric layer 144 is formed along the sidewall of the bottom electrode layer 142. The high-dielectric-constant dielectric layer 144 can be formed in spaces S1 and S2 along the sidewall of the bottom electrode layer 142. It can also be formed in the opening 120 along the sidewall of the bottom electrode layer 142. Furthermore, the high-dielectric-constant dielectric layer 144 can also be formed along the sidewalls, top and bottom surfaces of the second nitride layer 106 and the third nitride layer 110, and the top surface of the first nitride layer 102.

[0038] refer to Figure 13 A top electrode layer 146 is formed along the high-dielectric-constant dielectric layer 144. The top electrode layer 146 can be formed along the sidewalls of the high-dielectric-constant dielectric layer 144 in spaces S1 and S2. It can also be formed along the sidewalls of the high-dielectric-constant dielectric layer 144 in the opening 120. In some embodiments, the top electrode layer 146 is on the horizontal surface of the high-dielectric-constant dielectric layer 144. The top electrode layer 146 can be formed of any suitable material, such as titanium nitride.

[0039] refer to Figure 14 A semiconductor layer 150 is formed in the space S1 between the first nitride layer 102 and the second nitride layer 106, the space S2 between the second nitride layer 106 and the third nitride layer 110, and the opening of the second nitride layer 106. The semiconductor layer 150 can completely fill the spaces S1, S2 and the opening 120. The semiconductor layer 150 can also contact and cover the top electrode layer 146 on the third nitride layer 110. In this way, a capacitor 140 is formed in the opening 120 and the spaces S1 and S2. Because the first portion 122 of the opening 120 is widened, the bottom electrode layer 142, the high dielectric constant dielectric layer 144, the top electrode layer 146, and the semiconductor layer 150 are more easily formed in the opening 120. Because the material in the first portion 122 of the opening 120 provides strong support, the structure of the capacitor 140 is also more stable.

[0040] A semiconductor device 10 comprising multiple dielectric layers and capacitors 140 is illustrated in Figure 14The dielectric layer comprises a first nitride layer 102, a second nitride layer 106, and a third nitride layer 110 arranged from bottom to top, and the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110 are spaced apart from each other. In other words, the third nitride layer 110 is above the second nitride layer 106, and the second nitride layer 106 is above the first nitride layer 102. The thickness of the third nitride layer 110 is less than the thickness of the first nitride layer 102.

[0041] Capacitor 140 includes a bottom electrode layer 142, a high-dielectric-constant dielectric layer 144, and a top electrode layer 146. The bottom electrode layer 142 of capacitor 140 contacts the sidewalls 102S of the first nitride layer 102, the sidewalls 106S of the second nitride layer 106, and the sidewalls 110S of the third nitride layer 110. The high-dielectric-constant dielectric layer 144 contacts the bottom electrode layer 142, and the top electrode layer 146 contacts the high-dielectric-constant dielectric layer 144, such that the high-dielectric-constant dielectric layer 144 is located between the bottom electrode layer 142 and the top electrode layer 146. Intermediate layers of the dielectric layer (e.g., Figure 14 The second nitride layer 106 defines the upper portion 140U and the lower portion 140B of the capacitor 140, wherein the sidewalls of the upper portion 140U of the capacitor are inclined relative to the dielectric layer (e.g., the first nitride layer 102) than the sidewalls of the lower portion 140B of the capacitor 140. In some embodiments, the sidewalls of the lower portion 140B of the capacitor are substantially perpendicular to the bottom surface of the dielectric layer (e.g., the first nitride layer 102). Therefore, the lower portion 140B of the capacitor 140 is wide enough to provide strong support for the capacitor 140 and to stabilize the structure of the capacitor 140. In some embodiments, a high dielectric constant dielectric layer 144 and a top electrode layer 146 may be formed between the first nitride layer 102 and the second nitride layer 106, and between the second nitride layer 106 and the third nitride layer 110. A high-dielectric-constant dielectric layer 144 covers the dielectric layers (e.g., the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110) and the bottom electrode layer 142. A top electrode layer 146 covers the high-dielectric-constant dielectric layer 144. Therefore, the high-dielectric-constant dielectric layer 144 and the top electrode layer 146 can be planar and inclined layers, respectively. In some embodiments, the high-dielectric-constant dielectric layer 144 can be a continuous layer on the third nitride layer 110 and extends from one bottom electrode layer 142 to another. The high-dielectric-constant dielectric layer 144 can contact the bottom and top surfaces of the dielectric layers.

[0042] The semiconductor device further includes a semiconductor layer 150, which is vertically positioned between dielectric layers (i.e., the first nitride layer 102, the second nitride layer 106, and the third nitride layer 110). The semiconductor layer 150 is also formed on the top electrode layer 146 and in the opening 120. It should be noted that... Figure 14 The capacitor 140 is illustrative, and the capacitor 140 is not limited to... Figure 14The configuration shown. For example, capacitor 140 may contain additional layers.

[0043] In summary, some embodiments of the capacitor disclosed herein have a lower portion and an upper portion. The sidewall of the upper portion of the capacitor is more inclined than the sidewall of the lower portion. In this way, the lower portion of the capacitor is wide enough to provide strong support for the capacitor and to stabilize the capacitor structure.

[0044] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0045] [Symbol Explanation]

[0046] 10: Semiconductor devices

[0047] 100: Dielectric layer stacking

[0048] 102: First nitriding layer

[0049] 102B: Bottom surface

[0050] 102S: Sidewall

[0051] 104: First oxide layer

[0052] 104S: Sidewall

[0053] 106: Second nitride layer

[0054] 106S: Sidewall

[0055] 108: Second oxide layer

[0056] 108S: Sidewall

[0057] 110: Third nitride layer

[0058] 110S: Sidewall

[0059] 110T: Top surface

[0060] 120: Opening

[0061] 122: Part One

[0062] 124: Part Two

[0063] 130: Sacrifice Layer

[0064] 132: Part One

[0065] 134: Part Two

[0066] 140: Capacitor

[0067] 140B: Lower part

[0068] 140U: upper part

[0069] 142: Bottom Electrode Layer

[0070] 144: High dielectric constant dielectric layer

[0071] 146: Top electrode layer

[0072] 150: Semiconductor layer

[0073] S1: Space

[0074] S2: Space.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A dielectric layer stack is formed, wherein the dielectric layer stack includes a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer and a third nitride layer formed sequentially from bottom to top, and the second nitride layer has an opening; An opening is formed in the dielectric layer stack, wherein the opening includes a first portion and a second portion, the first portion exposing a plurality of sidewalls of the first oxide layer, and the second portion exposing a plurality of sidewalls of the second oxide layer; A sacrificial layer is formed on the top surface of the dielectric layer stack and along the plurality of sidewalls of the first oxide layer and the plurality of sidewalls of the second oxide layer in the opening; Perform a first etching process to remove a first portion of the sacrificial layer along the plurality of sidewalls of the first oxide layer; A second etching process is performed to widen the first portion of the opening; Remove the sacrificial layer along the plurality of sidewalls of the second oxide layer and the second portion on the top surface of the dielectric layer stack; After the second portion of the sacrificial layer is removed, a capacitor is formed in the opening of the dielectric layer stack; A semiconductor layer is formed in the first space between the first nitride layer and the second nitride layer, the second space between the second nitride layer and the third nitride layer, and the opening; as well as The semiconductor layer located in the first space is connected to the semiconductor layer located in the second space through the opening in the second nitride layer.

2. The method according to claim 1, characterized in that, The first oxide layer is doped with a dopant, and the dopant contains boron, phosphorus, or a combination thereof.

3. The method according to claim 2, characterized in that, It also includes adjusting the concentration of the dopant during the formation of the dielectric layer stack, such that the concentration of the dopant in the first oxide layer decreases as it moves further away from the bottom surface of the dielectric layer stack.

4. The method according to claim 1, characterized in that, During the formation of the sacrificial layer, the sacrificial layer along the plurality of sidewalls of the second oxide layer is thicker than the sacrificial layer along the plurality of sidewalls of the first oxide layer.

5. The method according to claim 1, characterized in that, The first etching process also laterally and partially removes the sacrificial layer along the plurality of sidewalls of the second oxide layer.

6. The method according to claim 1, characterized in that, It also includes controlling the timing of the first etching process to remove the sacrificial layer along the plurality of sidewalls of the first oxide layer.

7. The method according to claim 1, characterized in that, The first etchant used in the first etching process etches the sacrificial layer faster than the first oxide layer.

8. The method according to claim 1, characterized in that, The second etchant used in the second etching process etches the first oxide layer faster than the sacrificial layer.

9. A method for manufacturing a semiconductor device, characterized in that, Include: A dielectric layer stack is formed, wherein the dielectric layer stack includes, from bottom to top, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer and a third nitride layer, and the second nitride layer has a first opening; An opening is formed in the dielectric layer stack, wherein the opening includes a first portion and a second portion, the first portion exposes a plurality of sidewalls of the first oxide layer, and the second portion exposes a plurality of sidewalls of the second oxide layer, and the width of the second portion of the opening is greater than the width of the first portion of the opening; The first portion of the opening is widened such that the plurality of sidewalls of the first oxide layer are substantially perpendicular to the bottom surface of the dielectric layer stack; After widening the first portion of the opening, a capacitor is formed in the opening of the dielectric layer stack; A semiconductor layer is formed in the first space between the first nitride layer and the second nitride layer, the second space between the second nitride layer and the third nitride layer, and the opening; as well as The semiconductor layer located in the first space is connected to the semiconductor layer located in the second space through the first opening of the second nitride layer.

10. The method according to claim 9, characterized in that, The capacitor is formed within the opening in the dielectric layer stack: A bottom electrode layer is formed along the plurality of sidewalls of the opening; Remove a portion of the third nitride layer and the bottom electrode layer to form a second opening at the corner that exposes the second oxide layer; Remove the second oxide layer from the second opening; A portion of the first oxide layer is exposed through the first opening located in the second nitrided layer; Remove the first oxide layer from the first opening; A high dielectric constant dielectric layer is formed along the sidewall of the bottom electrode layer; and A top electrode layer is formed along the sidewall of the high dielectric constant dielectric layer.

11. The method according to claim 10, characterized in that, The semiconductor layer contacts the top electrode layer.

12. The method according to claim 10, characterized in that, The slope of the sidewall of the bottom electrode layer between the first nitrided layer and the second nitrided layer is different from the slope of the sidewall of the bottom electrode layer between the second nitrided layer and the third nitrided layer.

13. The method according to claim 10, characterized in that, The high dielectric constant dielectric layer is located between the first nitride layer and the second nitride layer.

14. A semiconductor device, characterized in that, Include: Multiple dielectric layers are arranged from bottom to top, and the multiple dielectric layers are spaced apart from each other; A capacitor, contacting multiple sidewalls of the plurality of dielectric layers, wherein an intermediate layer of the plurality of dielectric layers defines an upper and a lower portion of the capacitor, wherein the upper sidewall of the capacitor is inclined relative to one of the dielectric layers than the lower sidewall of the capacitor; and A semiconductor layer is vertically located between the plurality of dielectric layers, wherein the upper semiconductor layer of the capacitor is connected to the lower semiconductor layer of the capacitor through a hole in the intermediate layer.

15. The semiconductor device according to claim 14, characterized in that, The lower sidewall of the capacitor is substantially perpendicular to one of the dielectric layers.

16. The semiconductor device according to claim 14, characterized in that, The capacitor contacts multiple bottom surfaces of the plurality of dielectric layers.

17. The semiconductor device according to claim 14, characterized in that, The capacitor contacts multiple top surfaces of the plurality of dielectric layers.

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