Radio frequency front-end circuit, control method thereof and radio frequency module
By setting up multiplexed signal lines between the CMOS controller and the RF switch and using an enable control module, the communication delay problem between the CMOS controller and the RF switch is solved, thereby improving the performance of the RF module.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG STARSHINE SEMICON CO LTD
- Filing Date
- 2023-08-25
- Publication Date
- 2026-08-04
AI Technical Summary
In existing technologies, the time delay in serial communication between the CMOS controller and the RF switch leads to a decrease in the transmission performance of the RF module.
Multiplexed clock and data signal lines are set between the CMOS controller and the RF switch, and synchronous control is achieved by enabling the control module to control the conduction or disconnection of the signal lines according to the register data in the MIPI module.
It eliminates the serial communication delay between the CMOS controller and the RF switch, improves the performance of the RF module, and avoids the impact of harmonic characteristics and RF performance.
Smart Images
Figure CN117118474B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency communication technology, and in particular to a radio frequency front-end circuit and its control method, and a radio frequency module. Background Technology
[0002] The RF front-end refers to the RF components located between the antenna and the transceiver. An integrated RF front-end solution, as opposed to a discrete solution, refers to a solution that integrates two or more discrete components such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers into a single module. This improves integration and performance while miniaturizing the device. Depending on the integration method, integrated solutions can be categorized as FEMiD (integrated RF switch, filter, and duplexer), PAMiD (integrated multi-mode multi-band power amplifier and FEMiD), LPAMiD (low-noise amplifier, integrated multi-mode multi-band power amplifier, and FEMiD), DiFEM (integrated RF switch and filter), and LFEM (integrated RF switch, low-noise amplifier, and filter), among others.
[0003] In module product design, a CMOS controller is typically used for functional control, including communication with RF switches. For example... Figure 1 As shown, in the prior art, a common practice is to integrate a MIPI module (Mobile Industry Processor Interface, a communication protocol for standardizing communication between devices in a mobile terminal system) inside the CMOS Controller chip, and then establish serial communication with the RF switch through the CMOS Controller.
[0004] Serial communication, as a typical asynchronous communication method, generally requires three lines: ground, transmit, and receive. It allows data to be sent on one line while data is received on another. Therefore, although serial communication is slower than parallel communication, it remains a widely used and stable communication method. Figure 2 The diagram shown is a typical serial communication diagram and a serial port diagram.
[0005] Using serial communication, after the MIPI register data is rewritten, there is still a timing delay before it reaches the internal switching chip. Therefore, the switching time obviously has a certain delay. Figure 3As shown in the simulation results, the data transmission time required for communication between the CMOS controller and the switch serial port is approximately 0.45μs. For RF chip designs requiring sensitive switching, it is essential to minimize the problems caused by switch switching time delay; otherwise, it will further affect the transmission performance of the RF module. Summary of the Invention
[0006] To address the aforementioned technical problems, this invention provides an RF front-end circuit and its control method, as well as an RF module, aiming to solve the technical problem of delay caused by serial communication time between the CMOS controller and the RF switch.
[0007] A first aspect of the present invention provides a radio frequency front-end circuit, comprising:
[0008] CMOS controller;
[0009] Radio frequency switch;
[0010] The CMOS controller is equipped with a MIPI module, and the MIPI module is connected to the RF switch and is provided with multiplexed clock signal lines and data signal lines.
[0011] The CMOS controller is equipped with an enable control module, which is used to control the clock signal line and the data signal line to be connected to the radio frequency switch respectively according to the register data in the MIPI module.
[0012] Optionally, the enable control module specifically includes:
[0013] Detection unit;
[0014] Output unit;
[0015] The detection unit is used to detect whether the first data in the register of the MIPI module is the same as at least one set of first preset data stored in the detection unit; the first data in the register is address data.
[0016] The output unit is used to output an enable signal according to the detection result of the detection unit. The enable signal controls the clock signal line and the data signal line to be connected to the radio frequency switch respectively.
[0017] Optionally, the first preset data is the address data of a register related to radio frequency switch control.
[0018] Optionally, the detection unit specifically includes:
[0019] Byte data reading subunit;
[0020] Bit data reading subunit;
[0021] The byte data reading subunit is used to read the byte address in the register, and the byte address points to the bit data that stores the first data of the register;
[0022] The bit data reading subunit is used to read the first register data stored in the bit data of the byte address.
[0023] Optionally, the byte address includes a high-order byte address and a low-order byte address.
[0024] Optionally, the radio frequency switch is configured with a logic processing module; the logic processing module specifically includes:
[0025] Data extraction unit;
[0026] Channel control unit;
[0027] The data extraction unit is used to extract the second register data from the MIPI module; the second register data is channel control data.
[0028] The channel control unit is used to control the conduction state of the channel within the radio frequency switch according to the second data in the register.
[0029] A second aspect of the present invention provides a control method for a radio frequency (RF) front-end circuit, the RF front-end circuit including a CMOS controller and an RF switch, the control method for the RF front-end circuit including:
[0030] Multiplexed clock and data signal lines are connected between the MIPI module of the CMOS controller and the RF switch;
[0031] Configure an enable control module in the CMOS controller;
[0032] The enable control module generates an enable signal based on the register data in the MIPI module;
[0033] The enable signal is sent to the radio frequency switch to control the clock signal line and the data signal line to be connected to the radio frequency switch for conduction.
[0034] Optionally, the step of generating an enable signal based on the register data in the MIPI module specifically includes:
[0035] The system detects whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit; the first data in the register is address data.
[0036] If yes, control the clock signal line and the data signal line to be connected to the RF switch respectively; if no, control the clock signal line and the data signal line to be disconnected from the RF switch respectively.
[0037] Optionally, the first preset data is the address data of a register related to radio frequency switch control.
[0038] Optionally, the step of detecting whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit specifically includes:
[0039] Read the byte address in the register data, where the byte address points to the bit data storing the first data of the register;
[0040] Read the first data of the register stored in the bit data of the byte address.
[0041] Optionally, the step of reading the byte address in the register data specifically includes: reading the high-order byte data and the low-order byte data in the register data.
[0042] Optionally, the control method for the RF front-end circuit also includes:
[0043] Extract the second data from the register in the MIPI module; the second data in the register is channel control data.
[0044] The conduction state of the channel within the RF switch is controlled based on the second data in the register.
[0045] In a third aspect, the present invention provides a radio frequency module comprising the radio frequency front-end circuit as described above.
[0046] The beneficial effects of this invention are as follows: It proposes a radio frequency front-end circuit and its control method, as well as a radio frequency module. By connecting and setting multiplexed clock signal lines and data signal lines between the MIPI module of the CMOS controller and the radio frequency switch, the delay caused by the serial communication time between the CMOS controller and the radio frequency switch is eliminated. Furthermore, by enabling the control module to disconnect the communication when the radio frequency front-end circuit does not need to control the radio frequency switch, the harmonic characteristics and radio frequency performance are avoided, thereby improving the performance of the radio frequency module. Attached Figure Description
[0047] Figure 1 This is a schematic diagram of the structure for establishing serial communication between the CMOS controller and the RF switch;
[0048] Figure 2 This is a typical diagram of serial communication;
[0049] Figure 3This is a schematic diagram illustrating the transmission delay during serial communication simulation between the CMOS controller and the RF switch.
[0050] Figure 4 This is a schematic diagram of the radio frequency front-end circuit in this invention;
[0051] Figure 5 This is a schematic diagram of the 13-bit frame of the MIPI command of this invention;
[0052] Figure 6 This is a schematic diagram of the 9-bit data frame of the MIPI command of this invention;
[0053] Figure 7 This is a schematic diagram of the sequence of the Register Read / Write command of this invention;
[0054] Figure 8 This is a schematic diagram of the sequence of the Extended Register Read / Write command of this invention;
[0055] Figure 9 This is a schematic diagram of the sequence of the Extended Register Read / Write command of this invention;
[0056] Figure 10 This is a flowchart illustrating the control method for the radio frequency front-end circuit of the present invention. Detailed Implementation
[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0058] Example 1:
[0059] Reference Figure 4 , Figure 4 This is a schematic diagram of a radio frequency (RF) front-end circuit according to Embodiment 1 of the present invention. The RF front-end circuit includes: a CMOS controller; and an RF switch. The CMOS controller is configured with a MIPI module, and the MIPI module is connected to the RF switch and provided with multiplexed clock signal lines and data signal lines. The CMOS controller is also configured with an enable control module, which is used to control the clock signal lines and the data signal lines to be connected to the RF switch respectively according to the register data in the MIPI module.
[0060] It should be noted that the CMOS controller is the controller used to perform functional control in the RF module, while the RF switch is the circuit used to control and process high-power RF signals in the RF module. When serial communication is usually used between the CMOS controller and the RF switch, the MIPI module configured in the CMOS controller needs to wait for a certain time after the register data is rewritten before it reaches the RF switch. This causes a certain delay in the switching time of the RF switch, reduces the sensitivity of the RF chip, and thus affects the transmission performance of the RF module.
[0061] In this embodiment, during the design of the module product, the MIPI module of the CMOS controller in the RF front-end circuit is configured to be multiplexed with the clock signal line (CLK) and data signal line (DATA) of the RF switch. When the data in the MIPI module register is rewritten, a signal can be sent to the RF switch synchronously to control the switching of the switch and achieve synchronous control.
[0062] In practical applications, to avoid the impact of RF switches on harmonic characteristics and RF performance when RF switch control is not required, an enable control module can be configured in the CMOS controller. This enable control module is used to control the conduction connection of the RF switch on the clock signal line and data signal line according to the register data in the MIPI module. In this way, the RF switch can be selectively turned on or off according to the data in the register.
[0063] This embodiment provides an RF front-end circuit that eliminates the delay caused by serial communication between the CMOS controller and the RF switch by connecting and setting multiplexed clock signal lines and data signal lines between the MIPI module of the CMOS controller and the RF switch. Furthermore, by enabling the control module to disconnect communication when the RF front-end circuit does not need to control the RF switch, the harmonic characteristics and RF performance are avoided, thus improving the performance of the RF module.
[0064] In one optional implementation of the RF front-end circuit, the enable control module specifically includes: a detection unit and an output unit; wherein the detection unit is used to detect whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit; the first data in the register is address data; wherein the output unit is used to output an enable signal according to the detection result of the detection unit, the enable signal controlling the clock signal line and the data signal line to be connected to the RF switch respectively. In practical applications, the first preset data is the address data of the register related to the RF switch control.
[0065] It should be noted that the enable control module outputs an enable signal (high level in this embodiment) to control the clock signal line and the data signal line to be connected to the RF switch when the address in the register data of the MIPI module matches the preset address. Conversely, it outputs an enable signal (low level in this embodiment) to control the clock signal line and the data signal line to be disconnected from the RF switch when the address in the register data of the MIPI module does not match the preset address. Specifically, the detection unit of the enable control module first extracts the register data from the MIPI module, and then determines whether there is a register first data with the same address data as the register related to RF switch control. If so, the output unit of the enable control module outputs a high-level enable signal; otherwise, it outputs a low-level enable signal, thereby controlling the connection between the clock signal line and the data signal line and the RF switch.
[0066] In a preferred embodiment, the RF switch is configured with a logic processing module; the logic processing module specifically includes: a data extraction unit; and a channel control unit; wherein the data extraction unit is used to extract second register data from the MIPI module; the second register data is channel control data; and the channel control unit is used to control the conduction state of the channel within the RF switch according to the second register data.
[0067] In this embodiment, when the RF switch is connected to the clock signal line and the data signal line, the RF switch will synchronously receive the second data of the register in the MIPI module as channel control data. After being processed by the logic processing module, the second data of the register is used to control the conduction or deactivation of the relevant channels in the RF switch, thereby completely eliminating the serial communication time.
[0068] For example, based on the 13-bit frame of the MIPI command (such as... Figure 5 (as shown) and data 9-bit frames (as shown) Figure 6 (As shown) This further explains the specific implementation process of the enable control module. Specifically, taking a typical RegisterRead / Write instruction sequence as an example, if a 52MHz clock is used, the instruction time for each register write is approximately 0.5μs, and its instruction sequence is as follows: Figure 7As shown, in this instruction sequence, bits A4-A0 are the address bits of the register. When determining whether there is the first data of the register with the same address data as the register related to the RF switch control from the register data, specifically, whether the matching address bit is the same as the preset address bit corresponding to the RF switch. Bits D7-D0 are the data bits of the register. When the RF switch is turned on with the clock signal line and the data signal line, the data received by the RF switch from the MIPI module is the data bit of this register.
[0069] In one optional implementation of the radio frequency front-end circuit, the detection unit specifically includes: a byte data reading subunit; and a bit data reading subunit; wherein the byte data reading subunit is used to read the byte address in the register, the byte address pointing to the bit data storing the first data of the register; and wherein the bit data reading subunit is used to read the first data of the register stored in the bit data of the byte address.
[0070] The aforementioned embodiments only provide five address bits, A4-A0. In some scenarios, when the switch control logic is complex, the address bits may be exhausted. This embodiment first reads the byte address in the register, and then reads the stored first register data from the bit data in the byte address to support multi-byte operations, thereby enabling more register addresses. For example, as shown... Figure 8 As shown, when using the Extended Register Read / Write command, in addition to the eight bits A7-A0 representing the address, there are also bytes B3-B0 used to represent the number of bytes being operated on.
[0071] In a preferred embodiment, the byte address includes a high-order byte address and a low-order byte address.
[0072] The foregoing embodiments provide eight address bits A7-A0. In some scenarios, to provide more register addresses, both the high-order byte address and the low-order byte address are provided to support multi-byte operations, thereby enabling more register addresses. For example, as shown... Figure 9 As shown, the Extended Register Read / Write Long command uses sixteen address bits A15-A0, and bytes B2-B0 to represent the number of bytes used in the operation.
[0073] Example 2:
[0074] Reference Figure 10 , Figure 10 This is a flowchart illustrating a control method for a radio frequency (RF) front-end circuit according to Embodiment 2 of the present invention. The RF front-end circuit includes a CMOS controller and an RF switch. The method includes:
[0075] Step S1: Connect and configure multiplexed clock and data signal lines between the MIPI module of the CMOS controller and the RF switch;
[0076] Step S2: Configure the enable control module in the CMOS controller;
[0077] Step S3: The enable control module generates an enable signal based on the register data in the MIPI module;
[0078] Step S4: Send the enable signal to the RF switch to control the clock signal line and the data signal line to be connected to the RF switch for conduction.
[0079] It should be noted that the CMOS controller is the controller used to perform functional control in the RF module, while the RF switch is the circuit used to control and process high-power RF signals in the RF module. When serial communication is usually used between the CMOS controller and the RF switch, the MIPI module configured in the CMOS controller needs to wait for a certain time after the register data is rewritten before it reaches the RF switch. This causes a certain delay in the switching time of the RF switch, reduces the sensitivity of the RF chip, and thus affects the transmission performance of the RF module.
[0080] In this embodiment, during the design of the module product, the MIPI module of the CMOS controller in the RF front-end circuit is configured to be multiplexed with the clock signal line (CLK) and data signal line (DATA) of the RF switch. When the data in the MIPI module register is rewritten, a signal can be sent to the RF switch synchronously to control the switching of the switch and achieve synchronous control.
[0081] In practical applications, to avoid the impact of RF switches on harmonic characteristics and RF performance when RF switch control is not required, an enable control module can be configured in the CMOS controller. This enable control module is used to control the conduction connection of the RF switch on the clock signal line and data signal line according to the register data in the MIPI module. In this way, the RF switch can be selectively turned on or off according to the data in the register.
[0082] This embodiment provides a control method for an RF front-end circuit. By connecting and setting multiplexed clock signal lines and data signal lines between the MIPI module of the CMOS controller and the RF switch, the delay caused by serial communication time between the CMOS controller and the RF switch is eliminated. Furthermore, by enabling the control module to disconnect communication when the RF front-end circuit does not need to control the RF switch, the harmonic characteristics and RF performance are avoided, thereby improving the performance of the RF module.
[0083] The control method for the aforementioned RF front-end circuit can be implemented in one of the following steps: generating an enable signal based on register data in the MIPI module, specifically including:
[0084] Step S11: Detect whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit; the first data in the register is address data;
[0085] Step S12: If yes, control the clock signal line and the data signal line to be connected to the RF switch respectively; if no, control the clock signal line and the data signal line to be disconnected from the RF switch respectively.
[0086] In practical applications, the first preset data is the address data of the registers related to radio frequency switch control.
[0087] It should be noted that the enable control module outputs an enable signal (high level in this embodiment) to control the clock signal line and the data signal line to be connected to the RF switch when the address in the register data of the MIPI module matches the preset address. Conversely, it outputs an enable signal (low level in this embodiment) to control the clock signal line and the data signal line to be disconnected from the RF switch when the address in the register data of the MIPI module does not match the preset address. Specifically, the detection unit of the enable control module first extracts the register data from the MIPI module, and then determines whether there is a register first data with the same address data as the register related to RF switch control. If so, the output unit of the enable control module outputs a high-level enable signal; otherwise, it outputs a low-level enable signal, thereby controlling the connection between the clock signal line and the data signal line and the RF switch.
[0088] In a preferred embodiment, the method further includes:
[0089] Step S5: Extract the second register data from the MIPI module; the second register data is channel control data;
[0090] Step S6: Control the conduction state of the channel within the RF switch according to the second data in the register.
[0091] In this embodiment, when the RF switch is connected to the clock signal line and the data signal line, the RF switch will synchronously receive the second data of the register in the MIPI module as channel control data. After being processed by the logic processing module, the second data of the register is used to control the conduction or deactivation of the relevant channels in the RF switch, thereby completely eliminating the serial communication time.
[0092] For example, based on the 13-bit frame of the MIPI command (such as... Figure 5 (as shown) and data 9-bit frames (as shown) Figure 6 (As shown) This further explains the specific implementation process of the enable control module. Specifically, taking a typical RegisterRead / Write instruction sequence as an example, if a 52MHz clock is used, the instruction time for each register write is approximately 0.5μs, and its instruction sequence is as follows: Figure 7 As shown, in this instruction sequence, bits A4-A0 are the address bits of the register. The register first data is determined from the register data to see if it has the same address data as the register related to the RF switch control. Specifically, it is determined whether the matching address bit is the same as the preset address bit corresponding to the RF switch. Bits D7-D0 are the data bits of the register. When the RF switch is connected to the clock signal line and the data signal line, the data received by the RF switch from the MIPI module is the data bit of this register.
[0093] The control method for the radio frequency front-end circuit can be implemented in one of the following steps: detecting whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit, specifically including:
[0094] Step S111: Read the byte address in the register data, where the byte address points to the bit data storing the first data of the register;
[0095] Step S112: Read the first data of the register stored in the bit data of the byte address.
[0096] The aforementioned embodiments only provide five address bits, A4-A0. In some scenarios, when the switch control logic is complex, the address bits may be exhausted. This embodiment first reads the byte address in the register, and then reads the stored first register data from the bit data in the byte address to support multi-byte operations, thereby enabling more register addresses. For example, as shown... Figure 8 As shown, when using the Extended Register Read / Write command, in addition to the eight bits A7-A0 representing the address, there are also bytes B3-B0 used to represent the number of bytes being operated on.
[0097] In a preferred embodiment, the step of reading the byte address in the register data specifically includes: reading the high-order byte data and the low-order byte data in the register data.
[0098] The foregoing embodiments provide eight address bits A7-A0. In some scenarios, to provide more register addresses, both the high-order byte address and the low-order byte address are provided to support multi-byte operations, thereby enabling more register addresses. For example, as shown... Figure 9 As shown, the Extended Register Read / Write Long command uses sixteen address bits A15-A0, and bytes B2-B0 to represent the number of bytes used in the operation.
[0099] Example 3:
[0100] Embodiment 3 of the present invention provides a radio frequency (RF) module, which includes one of the aforementioned optional embodiments of the RF front-end circuit. The specific implementation is basically the same as the aforementioned embodiments of the RF front-end circuit, and will not be repeated here.
[0101] In the description of the embodiments of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "center," "top," "bottom," "top," "bottom," "inner," "outer," "inner side," and "outer side," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. "Inner side" refers to the interior or enclosed area or space. "Outer perimeter" refers to the area surrounding a specific component or specific area.
[0102] In the description of embodiments of the present invention, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature. In the description of the present invention, unless otherwise stated, "a plurality of" means two or more.
[0103] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.
[0104] In the description of embodiments of the present invention, specific features, structures, materials or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0105] In the description of the embodiments of the present invention, it should be understood that "-" and "~" represent a range of two values, and this range includes the endpoints. For example, "AB" represents a range greater than or equal to A and less than or equal to B. "A~B" represents a range greater than or equal to A and less than or equal to B.
[0106] In the description of embodiments of the present invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0107] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A radio frequency front-end circuit, characterized in that, include: CMOS controller; Radio frequency switch; The CMOS controller is equipped with a MIPI module. The MIPI module is connected to the RF switch and is provided with multiplexed clock signal lines and data signal lines. The clock signal lines and data signal lines are used to synchronously send control signals to the RF switch when the register data of the MIPI module is rewritten, so as to control the switching of the RF switch. The CMOS controller is equipped with an enable control module, which is used to control the clock signal line and the data signal line to be connected to the radio frequency switch respectively according to the register data in the MIPI module.
2. The radio frequency front-end circuit according to claim 1, characterized in that, The enabling control module specifically includes: Detection unit; Output unit; The detection unit is used to detect whether the first data in the register of the MIPI module is the same as at least one set of first preset data stored in the detection unit; the first data in the register is address data. The output unit is used to output an enable signal according to the detection result of the detection unit. The enable signal controls the clock signal line and the data signal line to be connected to the radio frequency switch respectively.
3. The radio frequency front-end circuit according to claim 2, characterized in that, The first preset data is the address data of the registers related to radio frequency switch control.
4. The radio frequency front-end circuit according to claim 2 or 3, characterized in that, The detection unit specifically includes: Byte data reading subunit; Bit data reading subunit; The byte data reading subunit is used to read the byte address in the register, and the byte address points to the bit data that stores the first data of the register; The bit data reading subunit is used to read the first register data stored in the bit data of the byte address.
5. The radio frequency front-end circuit according to claim 4, characterized in that, The byte address includes the high-order byte address and the low-order byte address.
6. The radio frequency front-end circuit according to claim 1, characterized in that, The radio frequency switch is equipped with a logic processing module; the logic processing module specifically includes: Data extraction unit; Channel control unit; The data extraction unit is used to extract the second register data from the MIPI module; the second register data is channel control data. The channel control unit is used to control the conduction state of the channel within the radio frequency switch according to the second data in the register.
7. A control method for a radio frequency (RF) front-end circuit, wherein the RF front-end circuit includes a CMOS controller and an RF switch, characterized in that, include: A multiplexed clock signal line and a data signal line are connected between the MIPI module of the CMOS controller and the RF switch. The clock signal line and the data signal line are used to synchronously send control signals to the RF switch when the register data of the MIPI module is rewritten, so as to control the switching of the RF switch. Configure an enable control module in the CMOS controller; The enable control module generates an enable signal based on the register data in the MIPI module; The enable signal is sent to the radio frequency switch to control the clock signal line and the data signal line to be connected to the radio frequency switch for conduction.
8. The control method for the radio frequency front-end circuit according to claim 7, characterized in that, The step of generating an enable signal based on the register data in the MIPI module specifically includes: The system detects whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit; the first data in the register is address data. If yes, control the clock signal line and the data signal line to be connected to the RF switch respectively; if no, control the clock signal line and the data signal line to be disconnected from the RF switch respectively.
9. The control method for the radio frequency front-end circuit according to claim 8, characterized in that, The first preset data is the address data of the registers related to radio frequency switch control.
10. The control method for the radio frequency front-end circuit according to claim 8 or 9, characterized in that, The step of detecting whether the first data in the register of the MIPI module is the same as at least one set of first preset data pre-stored in the detection unit specifically includes: Read the byte address in the register, where the byte address points to the bit data storing the first data of the register; Read the first data of the register stored in the bit data of the byte address.
11. The control method for the radio frequency front-end circuit according to claim 10, characterized in that, The step of reading the byte address in the register data specifically includes: reading the high-order byte data and the low-order byte data in the register data.
12. The control method for the radio frequency front-end circuit according to claim 7, characterized in that, Also includes: Extract the second data from the register in the MIPI module; the second data in the register is channel control data. The conduction state of the channel within the RF switch is controlled based on the second data in the register.
13. A radio frequency module, characterized in that, Includes the radio frequency front-end circuit as described in any one of claims 1-6.