Method, electronic device, and medium for automatically generating a chip shell

Abstract

The application relates to a method for automatically generating a chip empty shell, an electronic device and a medium, and the method comprises the following steps: B1, obtaining a plurality of basic unit information as first basic unit information, generating a first design empty shell only comprising first basic unit port information and first design interconnection port information, and adding the first design empty shell into a self-defined design empty shell library; B2, obtaining a plurality of pth design empty shells, generating a qth design empty shell only comprising the pth design empty shell and qth design interconnection port information; or, obtaining at least one pth design empty shell and at least one basic unit information as qth basic unit information, generating a qth design empty shell only comprising the pth design empty shell, qth basic unit port information and qth design interconnection port information; and adding the qth design empty shell into the self-defined design empty shell library. The application can establish interconnection based on a high-level abstract layer, generate a chip design empty shell, accelerate chip design recombination and improve the efficiency of design recombination.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a method for automatically generating a chip shell, an electronic device and a medium. BACKGROUND

[0002] In the process of chip design, it is usually necessary to establish interconnections between multiple modules and multiple levels, and in particular for a large-scale chip design such as a GPU, manual establishment of interconnections is extremely low in efficiency, and therefore automatic interconnection is required. In the prior art, a script (such as Excel) is usually used to interconnect using PINs. For example, all the pins are listed in Excel, and then the script is used to capture signals in Excel to make adaptive interconnections, but the prior art at least has the following disadvantages: it is difficult to maintain all the signals in Excel, the speed of processing Excel is very slow, and some contents described in Excel are relatively simple and it is difficult to customize some interconnection rules, and the extensibility is poor. In addition, the prior art is based on the establishment of interconnection relationships at the bottom signal layer, and using the existing way to design a chip requires writing a large amount of bottom signal code (such as Verilog code), which is low in design efficiency, prone to errors, and poor in extensibility, and cannot realize flexible configuration and reconstruction. Therefore, how to provide a chip design technology which is not prone to errors, efficient, extensible, reconfigurable and configurable becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a method for automatically generating a chip shell, an electronic device and a medium, which can establish interconnections based on a high-level abstraction layer, generate a chip design shell, accelerate chip design reconstruction, and improve the efficiency of design reconstruction.

[0004] According to a first aspect of the present application, a method for automatically generating a chip shell is provided, comprising:

[0005] Step B1, obtaining a plurality of basic unit information from a preset basic unit information library as first basic unit information, generating a first design shell including only first basic unit port information and first design interconnection port information based on bus interconnection definition of the first basic unit information, adding the first design shell to a preset custom design shell library, the basic unit information library stores a plurality of basic unit information, and the basic unit information is RTL code;

[0006] Step B2, obtaining a plurality of pth design shells from the custom design shell library, generating a qth design shell including only the pth design shell and qth design interconnection port information based on bus interconnection definition of the plurality of pth design shells;

[0007] Or,

[0008] acquire at least one pth design shell from the self-defined design shell library and at least one basic cell information as qth basic cell information from a preset basic cell information library, and generate a qth design shell including only the pth design shell, qth basic cell port information and qth design interconnection port information based on the pth design shell and the at least one qth basic cell information through bus interconnection definition;

[0009] add the qth design shell to the preset self-defined design shell library, and the value range of q is 2 to N, N is the total number of target design levels, and the value range of p is 1 to q-1.

[0010] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory connected in communication with the processor; wherein the memory stores instructions executable by the processor, and the instructions are configured to execute the method according to the first aspect of the present application.

[0011] According to the third aspect of the present application, a computer readable storage medium is provided, and the computer instructions are used to execute the method according to the first aspect of the present application.

[0012] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical scheme, the method for automatically generating a chip shell, the electronic device and the medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value, and at least have the following advantages:

[0013] The present application can establish interconnection based on a high-level abstraction layer, generate a chip design shell, accelerate chip design reorganization, and improve the efficiency of design reorganization.

[0014] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, and the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following preferred embodiments are provided, and the detailed description is as follows in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The method flowchart for automatically generating a chip design RTL code provided for embodiment one is shown in the figure;

[0016] Figure 2 The method flowchart for automatically generating a chip shell provided for embodiment two is shown in the figure;

[0017] Figure 3 The method flowchart for generating a chip weak shell provided for embodiment three is shown in the figure;

[0018] Figure 4A flow chart of a chip design reorganization method provided for Example Four. DETAILED DESCRIPTION

[0019] To further clarify the technical means and effects taken by the present application to achieve the predetermined inventive purpose, the specific embodiments of a method for automatically generating a chip shell, an electronic device and a medium according to the present application and their effects are described in detail below in conjunction with the drawings and preferred embodiments.

[0020] Example One,

[0021] Example One of the present application provides a method for automatically generating a chip design RTL code, as shown in the following formula (I), which comprises the following steps: Figure 1

[0022] Step A1, obtaining a plurality of basic unit information from a preset basic unit information library as first basic unit information, generating first design interconnection information through bus interconnection definition of the first basic unit information, adding the first design interconnection information to a preset self-defined design interconnection information library, the basic unit information library stores a plurality of basic unit information, and the basic unit information is an RTL code;

[0023] It should be noted that the basic unit information is a pre-written RTL code, for example, an RTL code written in Verilog, VHDL or SystemVerilog. The basic unit information library can be pre-set with a plurality of general basic unit information, or the basic unit information can be added according to the new design requirement, that is, the basic unit information library can be self-defined and has good expansibility. The first basic unit information is used to compose the first design interconnection information, and the first basic unit information can be any basic unit information in the basic unit information library. The plurality of first basic unit information can be the same basic unit information or different basic unit information. Each design interconnection information can be defined as a DIY (Design Interconnect assemblY, design interconnection assembly).

[0024] Step A2, obtaining a plurality of i-th design interconnection information from the self-defined design interconnection information library, generating j-th design interconnection information through bus interconnection definition of the plurality of i-th design interconnection information, or obtaining at least one i-th design interconnection information from the self-defined design interconnection information library and obtaining at least one basic unit information from a preset basic unit information library as j-th basic unit information, generating j-th design interconnection information through bus interconnection definition of the i-th design interconnection information and the j-th basic unit information, adding the j-th design interconnection information to a preset self-defined design interconnection information library, and the value range of j is 2 to N, N is the total number of target design levels, and the value range of i is 1 to j-1; ​

[0025] It can be understood that the first design interconnection information is composed of a plurality of basic unit information interconnections, and each level of design interconnection information is composed of the design interconnection information that has been generated and the basic unit information as a component, and all the components are interconnected by bus interconnection definition to establish an interconnection relationship, and only a simple bus interconnection definition is required, without writing a large amount of underlying signal code. The jth basic unit information is used to compose the jth design interconnection information, which can be any basic unit information in the basic unit information library, and a plurality of jth basic units can be the same basic unit information or different basic unit information. Each generated design interconnection information, that is, each DIY, can be used as a component of other level design interconnection information.

[0026] Step A3, generating a chip design RTL code based on the Nth design interconnection information.

[0027] The chip design RTL code can be Verilog code, System Verilog code, VHDL code, or the like. As an example, in steps A1 and A2, the corresponding design interconnection information is generated by bus interconnection definition, including: configuring the corresponding bus reconstruction structure for each basic unit information and design interconnection information, configuring the attribute information of the interconnection bus reconstruction structure for each initiator, and establishing the interconnection relationship between the corresponding bus reconstruction structures according to the interconnection relationship of each design interconnection information. The corresponding design interconnection information is generated. It should be noted that the attribute information of the interconnection bus reconstruction structure refers to the detailed parameter information of the interconnection bus reconstruction structure. Among them, configuring the corresponding bus reconstruction structure includes defining the name of the bus reconstruction structure and selecting the corresponding bus reconstruction structure type from the preset bus description reconstruction library. It should be noted that each component can have one or more bus reconstruction structures, and the component refers to the basic unit or the generated level interconnection information at a certain level. Two components can be interconnected by one or more bus reconstruction structures, and the design interconnection information and the components of the design interconnection information can also be interconnected by one or more bus reconstruction structures, and based on this, the bus interconnection with other design interconnection information is established.

[0028] As an example, in the step A1 and the step A2, the interconnection relationship between the corresponding bus reconstruction structures is established according to the interconnection relationship corresponding to each design interconnection information, and the corresponding design interconnection information is generated, which includes: defining the interconnection relationship between the bus reconstruction structures and the interconnection relationship between the signal lines in the connected bus reconstruction structures, establishing the interconnection relationship between the corresponding bus reconstruction structures based on the interconnection relationship between all the bus reconstruction structures, and establishing the connection between each initiator bus reconstruction structure and the corresponding receiver bus reconstruction structure; and based on the attribute information of the interconnection bus reconstruction structure stored in the initiator and the interconnection relationship between the signal lines in the connected bus reconstruction structures, the connection between the signal lines is adaptively established, and the corresponding design interconnection information is generated. It should be noted that between two components with an interconnection relationship, one is an initiator and the other is a receiver. The distinction between the initiator and the receiver is a common knowledge in the art, which will not be described here. In the embodiment of the application, only the attribute information of the interconnection bus reconstruction structure stored in each initiator is needed. The initiator and the receiver establish the interconnection relationship, and share the attribute information of the corresponding interconnection bus reconstruction structure.

[0029] As an example, in the step A1, the first basic unit information is used to generate the first design interconnection information through bus interconnection definition, which specifically can include:

[0030] Step A11, based on the preset bus description reconstruction library, one or more bus reconstruction structures corresponding to each first basic unit information and first design interconnection information are configured, and attribute information of the interconnection bus reconstruction structure corresponding to each initiator is configured;

[0031] Step A12, based on the interconnection relationship between the first basic unit information and the interconnection relationship between the first basic unit information and the first design interconnection information bus reconstruction structure, the interconnection between the corresponding bus reconstruction structures is established, and the first design interconnection information is generated.

[0032] As an example, in the step A2, the plurality of i-th design interconnection information is used to generate the j-th design interconnection information through bus interconnection definition, which includes:

[0033] Step A21, based on the preset bus description reconstruction library, one or more bus reconstruction structures corresponding to the j-th design interconnection information are configured, and attribute information of the interconnection bus reconstruction structure corresponding to each initiator is configured;

[0034] Step A22, based on the interconnection relationship between the plurality of i-th design interconnection information and the interconnection relationship between the plurality of i-th design interconnection information and the j-th design interconnection information bus reconstruction structure, the interconnection between the corresponding bus reconstruction structures is established, and the j-th design interconnection information is generated.

[0035] As an example, in the step A2, the i-th design interconnection information and the j-th basic unit information are connected through a bus to generate the j-th design interconnection information, including:

[0036] In the step A23, one or more bus refactor structures corresponding to each j-th basic unit information and j-th design interconnection information are configured based on a preset bus description refactor library, and attribute information of the corresponding interconnection bus refactor structure is configured for each initiator;

[0037] In the step A24, interconnections between the corresponding bus refactor structures are established based on the interconnection relationship between the i-th design interconnection information and the j-th basic unit information, and the interconnection relationship between the i-th design interconnection information, the j-th basic unit information and the j-th design interconnection information bus refactor structure, to generate the j-th design interconnection information.

[0038] As an embodiment, the preset bus description refactor library includes one or more predefined bus refactor structure IDF (Interface Description Refactor), and the IDF is adopted as m IDFm represents the m-th bus refactor structure, and m is in the range of 1 to M, and M is the number of bus refactor structures. It can be understood that the IDF in the bus description refactor library can be increased or reduced according to the specific application requirement, that is, it can be customized, and has good expansibility, and after the IDF is determined, it can be directly called and used, without repeated definition in the design.

[0039] The IDF follows any one of the preset bus protocols, and the bus protocol can be an existing industrial standard bus protocol, such as AMBA (Arm Microcontroller Bus Architecure), PCI-Express (peripheral component interconnect express) and the like. It can also be a bus protocol customized according to the design requirement. The bus refactor structure is generated according to the preset bus description refactor structure, and IDF m The attribute information of the corresponding bus description refactor structure includes mX information segments {S1 m ,S2 m ,…S mX m}, wherein S mx m S mx mThis includes signal description information, timing diagram information, direction information, signal width information, reset value, and default value. The value of `mx` ranges from 1 to `mX`. It can be understood that different IDFs can correspond to different numbers of signals, with each signal corresponding to an information segment; that is, the value of `mX` may differ for different IDFs. The signal description information describes the signal and can be used to generate documentation. The direction information includes input, output, and inout, configured according to the specific direction of the signal. The signal width information can be a fixed value or a configurable value. The reset value and default value are pre-configured according to the specific signal. The reset value is used to generate a reasonable drive value, serving as a weak drive value. In complex signal application scenarios, S... mx m It also includes a structure describing the signal, according to S mx m The corresponding application scenario is configured with a structure describing the signal, for example, a structure describing 256 bits of data, where different data segments represent different meanings. IDF, basic unit information, and generated hierarchical design information are all universal and reusable. Furthermore, detailed parameters in the IDF can be configured to adapt to design requirements without affecting high-level descriptions. Since the IDF framework, most parameters, and basic unit information are predetermined, they can be directly called during the design process, resulting in high design efficiency and reduced error rates. It should be noted that for the same type of bus reconfiguration structure, details such as signal width and address width may differ in different applications. In such cases, feature variables can be used to adapt the attribute information within the IDF.

[0040] During the interconnection process between corresponding bus structures, if there are end interconnection ports in the interconnection chain, the end interconnection port of type output will be set to a floating state, and the end interconnection port of type input will be set to a corresponding default value, or the signal port corresponding to the end interconnection port of type input will be set to a corresponding custom value. It should be noted that one interconnection port corresponds to a group of signal ports.

[0041] Most existing bus interconnects are handled manually or by scripts using Verilog itself. This involves processing signal lines, which are the lowest-level signals. Even buses are expanded; for example, a bus may contain 100 signal lines. Existing technologies require processing each of these 100 signal lines individually. In the embodiments of this invention, by defining an IDF (Integrated Data Framework), interconnect relationships are defined. Interconnect relationships can be established using only a high-level abstract description, a concise description, declaring the bus type, defining the bus name, and defining the interconnect relationships. All bus details are defined in the IDF, greatly improving the efficiency and accuracy of interconnect design, thereby improving chip design efficiency.

[0042] It should be noted that any existing implementation of chip design RTL code based on Nth design interconnect information falls within the protection scope of this invention. Those skilled in the art will also understand that any technology implemented after this application that generates chip design RTL code based on Nth design interconnect information also falls within the protection scope of this invention. As a preferred example, in step A3,

[0043] Step A31: Based on the RTL code corresponding to the basic unit information of each component in the Nth design interconnection information, the interconnection relationship between each generated part, and the reconfiguration structure information of each bus, generate the target design RTL code according to the preset RTL code format template.

[0044] In the Nth design interconnection information, each basic unit information corresponds to a pre-written RTL code. The interconnection relationship between each component is obtained from the bus reconfiguration structure information, and the corresponding bus attribute information is obtained. The target design RTL code is generated by expanding layer by layer according to the preset RTL code format template.

[0045] The preset RTL code format template can be a Verilog code format template, a SystemVerilog code format template, or a VHDL RTL code format template.

[0046] It should be noted that if it is necessary to generate corresponding design RTL code from the design interconnection information of a certain level in the Nth design interconnection information, then the design interconnection information of that level can be obtained, and the corresponding design RTL code can be generated according to the process in step A31.

[0047] In the embodiment one, only the bottom RTL code of the basic cell information is written, and then the first design interconnection information, i.e. the design interconnection information of the first level, is generated based on the basic cell information through the bus interconnection. The design interconnection information of all subsequent levels is stacked by the generated design interconnection information and the basic cell information, and all components are defined through the bus interconnection. The design interconnection information of each level is generated, i.e. only through the high-level abstract description, the design interconnection information of each level is defined through the simple bus interconnection, without writing a large amount of bottom signal code, and without error, improving the efficiency of chip design. It should be noted that the related technical details in the subsequent other embodiments can also be applied to the related steps in this embodiment, which will not be repeated here.

[0048] Embodiment two,

[0049] The embodiment one can generate a complete target design RTL code, but in some application scenarios, for example, in the scene of acceleration regrouping, if the entire complete target design is imported, it is very time-consuming, and for part of the design, only the port information corresponding to the design is needed, without paying attention to the specific information of the internal components. At this time, a shell (Stub or Interface Module) including only the port information of the design can be generated. It should be noted that the design interconnection information of each level can correspond to a design, and can correspond to a chip. Based on this, the embodiment two provides a method for automatically generating a chip shell, as shown in Figure 2 , which comprises:

[0050] Step B1, obtaining a plurality of basic cell information as first basic cell information from a preset basic cell information library, generating a first design shell including only the first basic cell port information and the first design interconnection port information based on the bus interconnection definition of the first basic cell information, and adding the first design shell to a preset custom design shell library;

[0051] It can be understood that the chip shell referred to in this embodiment, i.e. the chip shell including only the port information, does not include the detailed RTL information of the specific components in the chip. The custom design shell library stores all generated design shells for subsequent level design shells to directly call, i.e. the generated design shell can be used as a component in the subsequent level design shell, avoiding repeated design and improving the efficiency of chip design.

[0052] Step B2, obtaining a plurality of pth design shells from the custom design shell library, and generating a qth design shell including only the pth design shell and qth design interconnection port information based on the bus interconnection definition of the plurality of pth design shells;

[0053] Or,

[0054] obtaining at least one pth design shell from the self-defined design shell library and obtaining at least one basic cell information as qth basic cell information from the preset basic cell information library, and generating a qth design shell including only the pth design shell, qth basic cell port information and qth design interconnection port information based on the pth design shell and the at least one qth basic cell information through bus interconnection definition;

[0055] adding the qth design shell into the preset self-defined design shell library, where q ranges from 2 to N, N is the total number of target design levels, and p ranges from 1 to q-1.

[0056] The qth design shell can be generated into RTL code of the qth design shell in a preset RTL code format template, which can be Verilog code, System Verilog code or VHDL code and the like.

[0057] It should be noted that steps B1 to B2 describe a manner of generating a design shell corresponding to each level of design, but it can be understood that if only part of the design levels need to be generated into a design shell and part of the design levels still need specific information of internal composition, then the part of the internal composition level needs to be generated according to steps A1 and A2 in Embodiment 1, and details are not repeated here. For the design level that needs to generate a design shell, it is generated in the manner of steps B1 to B2. That is, Embodiment 1 and Embodiment 2 can be combined and applied according to specific application requirements in chip design.

[0058] As an example, in steps B1 and B2, the following steps are included:

[0059] Step B10, configuring a bus reconstruction structure corresponding to each basic cell information and design interconnection information based on a preset bus description reconstruction library;

[0060] Bus description reconstruction library, and IDF m Details such as attribute information of the corresponding bus description reconstruction structure have been described in detail in Embodiment 1, and are not repeated here.

[0061] Step B20, establishing an interconnection relationship between the corresponding bus reconstruction structures according to the interconnection relationship of each design interconnection information, and generating a corresponding design shell based on the interconnection relationship between the corresponding bus reconstruction structures.

[0062] It should be noted that there can be one or more bus reconstruction structures for each component, and the component refers to a basic unit or a hierarchical interconnection information generated at a certain level. Two components can be interconnected through one or more bus reconstruction structures. The design interconnection information and the component of the design interconnection information can also be interconnected through one or more bus reconstruction structures, and based on this, other design interconnection information is interconnected through the bus. Correspondingly, the port information corresponding to each component and each level interconnection information is one or more.

[0063] As an example, in step B10, configuring the corresponding bus reconstruction structure includes:

[0064] Step B101, define the name of the bus reconstruction structure and select the corresponding bus reconstruction structure type from the preset bus description reconstruction library, and configure the attribute information of the interconnection bus reconstruction structure for each initiator.

[0065] It should be noted that between two components with an interconnection relationship, one is an initiator and the other is a receiver. The distinction between the initiator and the receiver is well known in the art and will not be described here. In the embodiment of the present application, only the attribute information of the interconnection bus reconstruction structure stored at each initiator is required. The initiator and the receiver establish an interconnection relationship and share the attribute information of the corresponding interconnection bus reconstruction structure.

[0066] As an example, step B20 includes:

[0067] B201, according to the interconnection relationship corresponding to each design interconnection information and the attribute information of the interconnection bus reconstruction structure configured for each initiator, expand and generate the input, output, and inout port information of each level design module included in the corresponding design module according to the preset RTL code structure, to obtain the corresponding design shell.

[0068] It should be noted that the related technical details in the previous embodiment and subsequent other embodiments can also be applicable to the related steps in this embodiment, which will not be repeated here.

[0069] Embodiment two can generate a chip design shell, which can accelerate chip design reorganization and improve the efficiency of design reorganization.

[0070] Embodiment three,

[0071] Embodiment two can be applied in chip reorganization scene, and can accelerate reorganization. However, in the application scene of function simulation and verification, although generating the chip shell can accelerate the chip design efficiency, the simulation and verification function cannot be realized because only the port information is reserved and the port driving is not reserved, which causes the composition of the received signal to be suspended (for example, the "Z state" of the Verilog port causes the "X state" to propagate, the "Z state" represents the high resistance state, and the "X state" represents the uncertain or unknown logic state). Therefore, in order to set a corresponding reasonable driving, that is, a weak driving, for each port information on the basis of the chip shell, the chip simulation and verification function can be realized normally, and the speed of the chip simulation and verification can be accelerated, and the chip design efficiency can be improved. Based on this, embodiment three provides a method for generating a chip weak driving shell (Shell), comprising:

[0072] Step C1, obtaining a plurality of basic unit information from a preset basic unit information library as first basic unit information, generating a first design weak driving shell including first basic unit port information, first design interconnection port information, and weak driving information corresponding to each port information based on bus interconnection definition of the first basic unit information, and adding the first design weak driving shell to a preset custom design weak driving shell library, wherein the basic unit information library stores a plurality of basic unit information, and the basic unit information is an RTL code;

[0073] It can be understood that the design weak driving shell referred to in the embodiment refers to a chip shell including port information and reasonable driving information corresponding to the port information, and does not include detailed RTL information of specific components in the chip. The custom design weak driving shell library stores all generated design weak driving shells, which are directly called by subsequent level design weak driving shells, that is, the generated design weak driving shells can be used as components in the subsequent level design weak driving shells, thereby avoiding repeated design and improving the chip design efficiency.

[0074] Step C2, obtaining a plurality of pth design weak driving shells from the custom design weak driving shell library, and generating a qth design weak driving shell including the pth design weak driving shell, qth design interconnection port information, and weak driving information corresponding to each port information based on bus interconnection definition of the plurality of pth design weak driving shells,

[0075] Or,

[0076] obtaining at least one pth design weak driving shell from the custom design weak driving shell library, and obtaining at least one basic unit information from a preset basic unit information library as qth basic unit information, and generating a qth design weak driving shell including the pth design weak driving shell, qth basic unit port information, qth design interconnection port information, and weak driving information corresponding to each port information based on bus interconnection definition of the pth design weak driving shell and the at least one qth basic unit information;

[0077] The qth design weak drive shell is added to a preset custom design weak drive shell library, q ranges from 2 to N, N is the total number of target design levels, and p ranges from 1 to q-1.

[0078] The RTL code of the qth design weak drive shell can be generated according to a preset RTL code format template, which can be Verilog code, System Verilog code, or VHDL code.

[0079] It should be noted that steps C1-C2 describe a way of generating a design weak drive shell for each level of design, but it can be understood that if only part of the design level needs to be generated as a design weak drive shell, and part of the design level still needs specific information of internal composition, then the part that needs internal composition level can be generated according to steps A1 and A2 in Embodiment 1, which will not be repeated here; for the design level that needs to generate a design empty shell, it is generated in the manner of steps B1-B2 in Embodiment 2, which will not be repeated here; for the design level that needs to generate a design weak drive shell, it is generated in the manner of steps C1-C2. That is, Embodiment 1, Embodiment 2, and Embodiment 3 can be combined and applied according to specific application requirements in chip design.

[0080] As an example, in steps C1 and C2, the following steps are included:

[0081] Step C10, configuring a bus reconstruction structure corresponding to each basic unit information and design interconnection information based on a preset bus description reconstruction library;

[0082] Bus description reconstruction library, and IDF m The attribute information and other details of the corresponding bus description reconstruction structure have been described in detail in Embodiment 1, which will not be repeated here.

[0083] Step C20, establishing an interconnection relationship between the corresponding bus reconstruction structures according to the interconnection relationship of each design interconnection information, generating port information corresponding to each design generation unit and design interconnection information based on the interconnection relationship between the corresponding bus reconstruction structures, and obtaining weak drive information corresponding to each port information, adding the weak drive information to the corresponding port information, and generating the corresponding design weak drive shell.

[0084] It should be noted that the bus reconstruction structure of each component part can be one or more, and the component part refers to a basic unit or a hierarchical interconnection information generated at a certain level. Two component parts can be interconnected through one or more bus reconstruction structures. The design interconnection information and the component part of the design interconnection information can also be interconnected through one or more bus reconstruction structures, and based on this, other design interconnection information is interconnected through a bus. Correspondingly, the port information corresponding to each component part and each level interconnection information is one or more. By adding corresponding weak drive information to the port information, without generating specific component information of each component part of each design interconnection information, the simulation and verification speed can be accelerated, and the accuracy of simulation and verification can be ensured, thereby improving the efficiency of chip design.

[0085] As an example, in step C10, the corresponding bus reconstruction structure includes:

[0086] Step C101, define the name of the bus reconstruction structure and select the corresponding bus reconstruction structure type from the preset bus description reconstruction library, and configure the attribute information of the corresponding interconnection bus reconstruction structure for each initiator.

[0087] It should be noted that between two component parts with an interconnection relationship, one is an initiator and the other is a receiver. The distinction between the initiator and the receiver is well known in the art and will not be described here. In the embodiment of the present application, only the attribute information of the interconnection bus reconstruction structure stored at each initiator is needed. The initiator and the receiver establish an interconnection relationship and share the attribute information of the corresponding interconnection bus reconstruction structure.

[0088] As an example, the weak drive value of the port can be directly set based on the reset value corresponding to the signal in the IDF. In step C20, the weak drive information corresponding to each port information is obtained, including:

[0089] Step C201, obtain the reset value corresponding to the output direction from the attribute information of the interconnection bus reconstruction structure configured by the initiator as the weak drive information of the output port of the initiator, and obtain the reset value corresponding to the input direction as the weak drive information of the output port of the receiver.

[0090] As an example, each DIY can also be provided with an extension field (tied off), and the weak drive value can be set linearly through the extension field to cover the corresponding reset value, so that in general, the scene that needs the reset value as the weak drive value can directly set the weak drive value in step C201, and for part of the special weak drive value setting scene, the weak drive value is set through the extension field, without changing the reset value, that is, without changing the corresponding IDF. In this way, the weak drive value acquisition demand in all scenes can be met, and the universality of the IDF can be ensured. Specifically, in step C20, the interconnection relationship between the corresponding bus reconstruction structure is generated, and each port custom weak drive value in the preset extension field is also set. In step C20, the weak drive information corresponding to each port information is obtained, including:

[0091] Step C202, determine whether the corresponding custom weak drive value is set in the preset extension field, if it exists, execute step C203;

[0092] Step C203, obtain the corresponding custom weak drive value as the weak drive information corresponding to the port information, if it does not exist, obtain the reset value corresponding to the output direction from the attribute information of the interconnection bus reconstruction structure initiated by the initiator as the weak drive information corresponding to the output port of the initiator, and obtain the reset value corresponding to the input direction as the weak drive information corresponding to the output port of the receiver.

[0093] It should be noted that the related technical details in the foregoing embodiments and subsequent other embodiments can also be applicable to the related steps in this embodiment, which will not be repeated here.

[0094] Embodiment three can generate a chip design weak drive shell, which can accelerate the speed of simulation and verification and improve the efficiency of design.

[0095] Embodiment four,

[0096] In the chip design process, the original target design information is usually generated based on logical interconnection, but in the process of establishing physical interconnection, according to factors such as layout physical position and synthesis demand, the recombination of part of the components is often needed. The existing EDA company usually needs to parse the bottommost code (such as Verilog) of the design, and the recombination design rule is deduced from the bottommost code to design the recombination chip. This process needs to consume a lot of time and is prone to errors. Embodiment four provides a chip design recombination method applied to the recombination process from chip logical interconnection to physical interconnection, including:

[0097] Step D1, obtaining original target design information {DIY1, DIY2, … DIY N ; IDF 01 , IDF 02 , … IDF0R DIY n DIY 0r DIY

[0098] DIY n DIY n DIY s DIY s DIY n DIY n DIY n DIY

[0099] DIY y DIY y+1 DIY N DIY

[0100] DIY y DIY y+1 DIY N DIY y-1 DIY y-1 DIYy DIY y+1 DIY N DIY

[0101] Step D3, reorganizing the u-th design interconnection information based on the chip design reorganization information, the unit information library and the IDF 01 IDF 02 IDF 0R DIY y DIY y+1 DIY T DIY u DIY y DIY y+1 DIY T DIY y DIY y+1 DIY N DIY

[0102] Step D4, generating the reorganized target design information {DIY1, DIY2, … DIY y-1 DIY y DIY y+1 DIY T IDF 01 IDF 02 IDF 0R}.

[0103] As an example, the step D3 includes:

[0104] Step D31, initializing u=y;

[0105] Step D32, obtaining the unit information required for reorganizing the u-th design interconnection information from the unit information library based on the chip design reorganization information, and defining the bus interconnection according to the interconnection relationship of the unit information required for the u-th design interconnection information in the original target design information, and obtaining the attribute information of the bus description reconstruction structure corresponding to all initiators in the reorganized u-th design interconnection information from {IDF 01 IDF 02 IDF 0R}, and configuring it to the corresponding initiator information to generate the reorganized u-th design interconnection information DIY u DIY u{F1, F2, … F

[0106] It is to be noted that the details of bus interconnection definition, configuring attribute information of bus description reconfiguration structure in initiator information, and attribute information of bus description reconfiguration structure of bus description are described in detail in Embodiment One, which will not be described herein.

[0107] Step D33, judging whether u is less than T, if yes, setting u = u + 1, and returning to execute Step D32.

[0108] In the reconfiguration process, new constituent units can be introduced, if the design reconfiguration information includes new reconfiguration unit information {F1, F2, … F Z} in the design reconfiguration information, F z represents the zthnew reconfiguration unit information as an example, the Step D3 includes:

[0109] Step D301, adding {F1, F2, … F Z} to the reconfiguration unit information library, and initializing u = y;

[0110] Step D32, obtaining the reconfiguration unit information required by the uthdesign interconnection information from the reconfiguration unit information library based on the chip design reconfiguration information, defining bus interconnection according to the interconnection relationship of the reconfiguration unit information required by the uthdesign interconnection information in the original target design information, and obtaining the attribute information of bus description reconfiguration structure corresponding to all initiators in the uthdesign interconnection information from {IDF 01 , IDF 02 , … IDF 0R}, and configuring to the corresponding initiator information, if new reconfiguration unit information is involved, establishing corresponding bus interconnection according to the corresponding interconnection relationship and the corresponding reconfiguration unit according to the new generated unit information F z in the design reconfiguration information, setting the attribute information IDF z of the corresponding bus description reconfiguration structure, generating the uthreconfiguration design interconnection information DIY u ', adding DIY u ' to the reconfiguration unit information library;

[0111] Step D33, judging whether u is less than T, if yes, setting u = u + 1, and returning to execute Step D32.

[0112] If the design reconfiguration information includes new reconfiguration unit information, in the Step D4, the generated reconfiguration target design information is {DIY1, DIY2, … DIY y-1 , DIY y ', DIY y+1 ', … DIY T '; IDF01 IDF 02 IDF 0R IDF1', IDF2',... IDF Z}.

[0113] It should be noted that the related technical details in the foregoing and subsequent other embodiments can also be applicable to the related steps in this embodiment, which will not be repeated here.

[0114] In the recombination process of the fourth embodiment, the underlying code does not need to be processed, and only the high-level recombination rules need to be modified according to the recombination information, which is not prone to errors and has high recombination efficiency, thereby improving the chip design efficiency.

[0115] It should be noted that all the above embodiments are applicable to the design process of all types of chips, and are particularly suitable for the design method of agile chips.

[0116] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps in a sequential order, many of the steps can be performed in parallel, concurrently or at the same time. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but can also have additional steps not included in the figure. The process can correspond to a method, function, routine, subroutine, or the like.

[0117] Those skilled in the art can understand that all the places mentioned in the full text where the information is set at the initiation end can also be replaced by setting the corresponding information at the receiving end, that is, all can be set at the initiation end or all can be set at the receiving end, which will not be repeated here.

[0118] The embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory connected with the processor in communication; wherein the memory stores instructions executable by the processor, and the instructions are arranged to execute the method of the embodiment of the present application.

[0119] The embodiment of the present application also provides a computer readable storage medium, and the computer instructions are used to execute the method of the embodiment of the present application.

[0120] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A method for automatically generating a chip cavity, characterized by, Comprising: Step B1, obtaining a plurality of basic cell information from a preset basic cell information library as first basic cell information, generating a first design shell including only first basic cell port information and first design interconnection port information based on bus interconnection definition of the first basic cell information, adding the first design shell into a preset custom design shell library, the basic cell information library stores a plurality of basic cell information, and the basic cell information is an RTL code; Step B2, obtaining a plurality of pth design shells from the custom design shell library, and generating a qth design shell including only the pth design shell and qth design interconnection port information based on bus interconnection definition of the plurality of pth design shells; Or, Obtaining at least one pth design shell from the custom design shell library, and obtaining at least one basic cell information from a preset basic cell information library as qth basic cell information, generating a qth design shell including only the pth design shell, qth basic cell port information and qth design interconnection port information based on bus interconnection definition of the pth design shell and at least one qth basic cell information; Adding the qth design shell into a preset custom design shell library, and the value range of q is 2 to N, and N is the total number of target design levels, and the value range of p is 1 to q-1; In the step B1 and the step B2, comprising: Step B10, configuring a bus reconstruction structure corresponding to each basic cell information and design interconnection information based on a preset bus description reconstruction library; Step B20, establishing an interconnection relationship between corresponding bus reconstruction structures according to an interconnection relationship corresponding to each design interconnection information, and generating a corresponding design shell based on the interconnection relationship between the corresponding bus reconstruction structures; The preset bus description reconfiguration library includes multiple predefined bus reconfiguration structures (IDFs), and adopts IDFs. m This represents the m-th bus reconfiguration structure, where m ranges from 1 to M, and M is the number of bus reconfiguration structures. (IDF) m The corresponding bus description reconfiguration structure attribute information includes mX information segments {S1} m S2 m ,…S mX m }, where S mx m S represents the information segment corresponding to the mx-th signal line in the m-th bus reconfiguration structure. mx m It includes signal description information, timing diagram information, direction information, signal width information, and default values. The value of mx ranges from 1 to mX.

2. The method of claim 1, wherein, In the step B10, configuring the corresponding bus reconstruction structure comprises: Step B101, defining a name of the bus reconstruction structure, selecting a corresponding bus reconstruction structure type from a preset bus description reconstruction library, and configuring attribute information of the interconnection bus reconstruction structure for each initiator.

3. The method of claim 1, wherein, The IDF complies with any one of a plurality of bus protocols, and the bus protocols include an industry standard bus protocol and a custom bus protocol.

4. The method of claim 1, wherein, The direction information includes input, output, and inout.

5. The method of claim 4, wherein, The step B20 comprises: B201, according to the interconnection relationship corresponding to each design interconnection information and the attribute information of the interconnection bus reconstruction structure configured for each initiator, expanding a corresponding design module and input, output and inout port information of each level design module contained in the corresponding design module according to a preset RTL code structure to obtain the corresponding design shell.

6. An electronic device, comprising: Comprising: At least one processor; And a memory in communication connection with the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any one of the preceding claims 1-5.

7. A computer readable storage medium characterized by computer executable instructions for performing the method of any one of the preceding claims 1-5.

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