Display panel, driving method thereof, and display device

Abstract

The present disclosure relates to the technical field of display, and proposes a display panel, a driving method thereof and a display device. The display panel comprises a plurality of pixel driving circuits (Pix), the plurality of pixel driving circuits (Pix) are arranged along a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) intersect, and the plurality of pixel driving circuits (Pix) form a plurality of pixel driving circuit groups (Pz), each pixel driving circuit group (Pz) comprises a plurality of pixel driving circuit rows, each pixel driving circuit row comprises a plurality of pixel driving circuits (Pix) arranged along the first direction (X), and each pixel driving circuit (Pix) comprises a driving circuit (74) and a first switch unit (71). The driving circuit (74) is connected with a first node (N1), a second node (N2) and a third node (N3), and is configured to input a driving current to the third node (N3) through the second node (N2) in response to a signal of the first node (N1). The first end of the first switch unit (71) is connected with a first power supply end (VDD), the second end is connected with the second node (N2), and the first switch unit (71) is configured to connect the first power supply end (VDD) and the second node (N2) in response to a pulse width modulation signal. In the same pixel driving circuit group (Pz), the second end of any first switch unit (71) is connected with the second end of at least one first switch unit (71) in each pixel driving circuit row. The display panel can improve the threshold offset problem of the first switch unit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] In the related art, a pixel driving circuit usually includes a switch transistor connected between a power supply terminal and a driving transistor. The display panel can adjust the brightness of a sub-pixel where the pixel driving circuit is located by controlling the duty cycle of a pulse width modulation signal of the gate of the switch transistor. However, since the switch transistor is in an on state for a long time, the threshold voltage of the switch transistor drifts seriously, which affects normal display.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel includes: a plurality of pixel driving circuits, the plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersect, the plurality of pixel driving circuits form a plurality of pixel driving circuit groups, each of the pixel driving circuit groups includes a plurality of pixel driving circuit rows, the pixel driving circuit row includes a plurality of pixel driving circuits arranged along the first direction, the pixel driving circuit includes: a driving circuit, a first switch unit, the driving circuit is connected to a first node, a second node, and a third node, and is configured to input a driving current to the third node through the second node in response to a signal of the first node; the first end of the first switch unit is connected to a first power supply terminal, the second end is connected to the second node, and is configured to connect the first power supply terminal and the second node in response to a pulse width modulation signal; wherein in the same pixel driving circuit group, the second end of any first switch unit is connected to the second end of at least one first switch unit in each of the other pixel driving circuit rows.

[0005] In an example embodiment of the present disclosure, the driving circuit comprises: a driving transistor, a first electrode of the driving transistor being connected to the second node, a second electrode of the driving transistor being connected to the third node, and a gate electrode of the driving transistor being connected to the first node; and the first switch unit comprises: a first transistor, a first electrode of the first transistor being connected to the first power supply end, a second electrode of the first transistor being connected to the second node, and a gate electrode of the first transistor being connected to the pulse width modulation signal end. The pixel driving circuit further comprises: a second transistor, a third transistor, and a capacitor, a first electrode of the second transistor being connected to a data signal end, a second electrode of the second transistor being connected to the first node, and a gate electrode of the second transistor being connected to a first gate driving signal end; a first electrode of the third transistor being connected to the third node, a second electrode of the third transistor being connected to a sensing signal end, and a gate electrode of the third transistor being connected to a second gate driving signal end; and the capacitor being connected between the first node and the third node.

[0006] In an example embodiment of the present disclosure, the display panel further comprises: a gate driving circuit, the gate driving circuit comprising a plurality of output ends, the output ends being arranged corresponding to the rows of pixel driving circuits, and the output ends being configured to provide the pulse width modulation signals to the control ends of the first switch units in the rows of pixel driving circuits corresponding to the output ends; and the gate driving circuit being configured to provide the pulse width modulation signals to a sub-group of pixel driving circuits in a same group of pixel driving circuits in a same frame, a part of the rows of pixel driving circuits in the group of pixel driving circuits forming the sub-group of pixel driving circuits, and the gate driving circuit being configured to provide the pulse width modulation signals to different sub-groups of pixel driving circuits in the same group of pixel driving circuits in at least partially different frames.

[0007] In an example embodiment of the present disclosure, the group of pixel driving circuits comprises a plurality of rows of pixel driving circuits adjacent in the second direction, and in the same group of pixel driving circuits, the second ends of the first switch units in the plurality of pixel driving circuits distributed in the second direction are connected to each other.

[0008] In an example embodiment of the present disclosure, the sub-group of pixel driving circuits comprises one row of pixel driving circuits, the group of pixel driving circuits comprises an odd row of pixel driving circuits located in an odd row and an even row of pixel driving circuits located in an even row, and two rows of pixel driving circuits in the group of pixel driving circuits are arranged adjacent in the second direction; the gate driving circuit is configured to provide the pulse width modulation signals to the odd row of pixel driving circuits or the even row of pixel driving circuits in a same frame, and the gate driving circuit is configured to provide the pulse width modulation signals to the odd row of pixel driving circuits in at least partially different frames and to provide the pulse width modulation signals to the even row of pixel driving circuits in at least partially different frames.

[0009] In an example embodiment of the present disclosure, the gate drive circuit comprises: a first gate drive circuit, a second gate drive circuit, the first gate drive circuit being connected to a first signal input line, a first clock signal line, a second clock signal line, and being configured to provide the pulse width modulation signal to an odd pixel drive circuit row in response to signals of the first signal input line, the first clock signal line, and the second clock signal line; and the second gate drive circuit being connected to a second signal input line, the first clock signal line, and the second clock signal line, and being configured to provide the pulse width modulation signal to an even pixel drive circuit row in response to signals of the second signal input line, the first clock signal line, and the second clock signal line.

[0010] In an example embodiment of the present disclosure, the first gate drive circuit comprises a plurality of cascaded shift register units, and the second gate drive circuit comprises a plurality of cascaded shift register units; each of the shift register units comprises: a first input circuit, a second input circuit, a pull-up circuit, a pull-down circuit, a first output circuit, and a second output circuit, the first input circuit being connected to a signal input terminal, a first clock signal terminal, and a fourth node, and being configured to transmit a signal of the signal input terminal to the fourth node in response to a signal of the first clock signal terminal; the second input circuit being connected to a second power supply terminal, a second clock signal terminal, a fifth node, and the signal input terminal, and being configured to transmit a signal of the second power supply terminal to the fifth node in response to a signal of the second clock signal terminal, and to transmit a signal of the second clock signal terminal to the fifth node in response to a signal of the signal input terminal; the pull-up circuit being connected to the first clock signal terminal, the fifth node, and a sixth node, and being configured to transmit a signal of the first clock signal terminal to the sixth node in response to signals of the fifth node and the first clock signal terminal; the pull-down circuit being connected to the fourth node, a third power supply terminal, and the sixth node, and being configured to transmit a signal of the third power supply terminal to the sixth node in response to a signal of the fourth node; the first output circuit being connected to the fourth node, a first output terminal, and the second power supply terminal, and being configured to transmit a signal of the second power supply terminal to the first output terminal in response to a signal of the fourth node; and the second output circuit being connected to the sixth node, the third power supply terminal, and the first output terminal, and being configured to transmit a signal of the third power supply terminal to the first output terminal in response to a signal of the sixth node.

[0011] In an example embodiment of the present disclosure, the first input circuit comprises a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is connected to the signal input end, the second electrode is connected to a seventh node, and the gate electrode is connected to the first clock signal end; the first electrode of the fifth transistor is connected to the seventh node, the second electrode is connected to the fourth node, and the gate electrode is connected to the first clock signal end. The second input circuit comprises a seventh transistor, an eighth transistor and a ninth transistor, the first electrode of the seventh transistor is connected to the second power supply end, the second electrode is connected to a fifth node, and the gate electrode is connected to the second clock signal end; the first electrode of the eighth transistor is connected to the fifth node, the second electrode is connected to an eighth node, and the gate electrode is connected to the signal input end; the first electrode of the ninth transistor is connected to the eighth node, the second electrode is connected to the second clock signal end, and the gate electrode is connected to the signal input end.

[0012] In an example embodiment of the present disclosure, the shift register unit further comprises a first isolation circuit and a second isolation circuit, the first isolation circuit is connected to the second power supply end, the fourth node and the seventh node, and is used for transmitting the signal of the second power supply end to the seventh node in response to the signal of the fourth node; the second isolation circuit is connected to the eighth node, the second power supply end and the fifth node, and is used for transmitting the signal of the second power supply end to the eighth node in response to the signal of the fifth node.

[0013] In an example embodiment of the present disclosure, the first isolation circuit comprises a sixth transistor, the first electrode of the sixth transistor is connected to the seventh node, the second electrode is connected to the second power supply end, and the gate electrode is connected to the fourth node; the second isolation circuit comprises a tenth transistor, the first electrode of the tenth transistor is connected to the second power supply end, the second electrode is connected to the eighth node, and the gate electrode is connected to the fifth node.

[0014] In an example embodiment of the present disclosure, the pull-up circuit comprises an eleventh transistor, a twelfth transistor and a first capacitor, the first electrode of the eleventh transistor is connected to the first clock signal end, the second electrode is connected to a ninth node, and the gate electrode is connected to the fifth node; the first electrode of the twelfth transistor is connected to the ninth node, the second electrode is connected to the sixth node, and the gate electrode is connected to the first clock signal end; the first capacitor is connected to the fifth node. The pull-down circuit comprises a thirteenth transistor, the first electrode of the thirteenth transistor is connected to the third power supply end, the second electrode is connected to the sixth node, and the gate electrode is connected to the fourth node.

[0015] In an example embodiment of the present disclosure, the first output circuit is further connected to a second output terminal, and is configured to transmit a signal of the second power terminal to the second output terminal in response to a signal of the fourth node; and the second output circuit is further connected to the second output terminal and a fourth power terminal, and is configured to transmit a signal of the fourth power terminal to the second output terminal in response to a signal of the sixth node, wherein the first output terminal or the second output terminal forms an output terminal of the gate drive circuit.

[0016] In an example embodiment of the present disclosure, the effective driving levels of the first input circuit, the second input circuit, the pull-up circuit, the first output circuit and the second output circuit are high levels; the second power terminal is a high-level signal terminal; the fourth power terminal and the third power terminal are low-level signal terminals, and the voltage of the third power terminal is lower than the voltage of the fourth power terminal.

[0017] In an example embodiment of the present disclosure, the first output circuit comprises a fourteenth transistor, a fifteenth transistor and a second capacitor, wherein a first electrode of the fourteenth transistor is connected to the second power terminal, a second electrode of the fourteenth transistor is connected to the first output terminal, and a gate electrode of the fourteenth transistor is connected to the fourth node; a first electrode of the fifteenth transistor is connected to the second power terminal, a second electrode of the fifteenth transistor is connected to the second output terminal, and a gate electrode of the fifteenth transistor is connected to the fourth node; and the second capacitor is connected to the fourth node; and the second output circuit comprises a sixteenth transistor, a seventeenth transistor and a third capacitor, wherein a first electrode of the sixteenth transistor is connected to the third power terminal, a second electrode of the sixteenth transistor is connected to the first output terminal, and a gate electrode of the sixteenth transistor is connected to the sixth node; a first electrode of the seventeenth transistor is connected to the fourth power terminal, a second electrode of the seventeenth transistor is connected to the second output terminal, and a gate electrode of the seventeenth transistor is connected to the sixth node; and the third capacitor is connected to the sixth node.

[0018] In an example embodiment of the present disclosure, the second output circuit comprises a sixteenth transistor, a twenty-fifth transistor, wherein a first electrode of the sixteenth transistor is connected to the seventh node, a second electrode of the sixteenth transistor is connected to the first output terminal, and a gate electrode of the sixteenth transistor is connected to the sixth node; a first electrode of the twenty-fifth transistor is connected to the seventh node, a second electrode of the twenty-fifth transistor is connected to the third power terminal, and a gate electrode of the twenty-fifth transistor is connected to the sixth node; and a third capacitor is connected to the sixth node.

[0019] In an example embodiment of the present disclosure, the shift register unit further comprises a reset circuit connected to the fourth node, a first clock signal terminal, a reset signal terminal, the second power terminal and the sixth node, and configured to transmit a signal of the first clock signal terminal to the fourth node in response to a signal of the reset signal terminal, and configured to transmit a signal of the second power terminal to the sixth node in response to a signal of the reset signal terminal.

[0020] In an example embodiment of the present disclosure, the first input circuit comprises: a fourth transistor, a fifth transistor, a first electrode of the fourth transistor being connected to the signal input end, a second electrode being connected to a seventh node, and a gate electrode being connected to the first clock signal end; a first electrode of the fifth transistor being connected to the seventh node, a second electrode being connected to the fourth node, and a gate electrode being connected to the first clock signal end; the shift register unit further comprises: a first isolation circuit connected to the second power supply end, the fourth node and the seventh node, for transmitting the signal of the second power supply end to the seventh node in response to the signal of the fourth node; the reset circuit comprises: an eighteenth transistor, a nineteenth transistor and a twentieth transistor, a first electrode of the eighteenth transistor being connected to the fourth node, a second electrode being connected to a tenth node, and a gate electrode being connected to the reset signal end; a first electrode of the nineteenth transistor being connected to the tenth node, a second electrode being connected to the first clock signal end, and a gate electrode being connected to the reset signal end; a first electrode of the twentieth transistor being connected to the second power supply end, a second electrode being connected to a sixth node, and a gate electrode being connected to the reset signal end; and the seventh node is connected to the tenth node.

[0021] In an example embodiment of the present disclosure, in the first gate drive circuit: the first output end of the shift register unit of the current stage is connected to the signal input end of the shift register unit of the adjacent next stage; the first signal input line is connected to the signal input end of the shift register unit of the first stage in the first gate drive circuit; the first clock signal line is connected to the first clock signal end of the shift register unit of the odd stage and the second clock signal end of the shift register unit of the even stage in the first gate drive circuit, and the second clock signal line is connected to the first clock signal end of the shift register unit of the even stage and the second clock signal end of the shift register unit of the odd stage in the first gate drive circuit. In the second gate drive circuit: the first output end of the shift register unit of the current stage is connected to the signal input end of the shift register unit of the adjacent next stage; the second signal input line is connected to the signal input end of the shift register unit of the first stage in the second gate drive circuit; the first clock signal line is connected to the first clock signal end of the shift register unit of the odd stage and the second clock signal end of the shift register unit of the even stage in the second gate drive circuit, and the second clock signal line is connected to the first clock signal end of the shift register unit of the even stage and the second clock signal end of the shift register unit of the odd stage in the second gate drive circuit.

[0022] In an example embodiment of the present disclosure, the gate drive circuit comprises: a plurality of cascaded shift register units, a plurality of output control circuits, the shift register units are arranged correspondingly with the pixel drive circuits, and the shift register units are configured to output the pulse width modulation signals through output ends; the output control circuits are arranged correspondingly with the shift register units, and the output control circuits are connected with the output ends of the corresponding shift register units, a fifth power supply end, a first control signal end, a second control signal end, a third output end, and a fourth output end; the output control circuits are configured to transmit the pulse width modulation signals of the output ends of the shift register units to the third output end in response to signals of the first control signal end, and transmit signals of the fifth power supply end to the fourth output end in response to signals of the first control signal end; the output control circuits are also configured to transmit the pulse width modulation signals of the output ends of the shift register units to the fourth output end in response to signals of the second control signal end, and transmit signals of the fifth power supply end to the third output end in response to signals of the second control signal end; and the third output end and the fourth output end form output ends of the gate drive circuit, the third output end is configured to provide the pulse width modulation signals to odd pixel drive circuit rows corresponding to the output control circuits, and the fourth output end is configured to provide the pulse width modulation signals to even pixel drive circuit rows corresponding to the output control circuits.

[0023] In an example embodiment of the present disclosure, the output control circuit comprises: a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor; a first electrode of the twenty-first transistor is connected with an output end of the corresponding shift register unit, a second electrode is connected with the third output end, and a gate electrode is connected with the first control signal end; a first electrode of the twenty-second transistor is connected with an output end of the corresponding shift register unit, a second electrode is connected with the fourth output end, and a gate electrode is connected with the second control signal end; a first electrode of the twenty-third transistor is connected with the fifth power supply end, a second electrode is connected with the third output end, and a gate electrode is connected with the second control signal end; and a first electrode of the twenty-fourth transistor is connected with the fifth power supply end, a second electrode is connected with the fourth output end, and a gate electrode is connected with the first control signal end.

[0024] According to an aspect of the present disclosure, a display panel driving method is provided for driving the display panel described above, the display panel driving method comprising:

[0025] The pulse width modulation signal is provided to a subgroup of pixel driving circuits in the same pixel driving circuit group within the same frame, wherein a portion of the pixel driving circuits in the pixel driving circuit group forms the subgroup of pixel driving circuits, and the pulse width modulation signal is provided to different subgroups of pixel driving circuits in the same pixel driving circuit group in at least some different frames.

[0026] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 This is a schematic diagram of a pixel driving circuit in related technologies;

[0030] Figure 2 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0031] Figure 3 for Figure 2 A complete structural diagram of region A in the middle;

[0032] Figure 4 This is a schematic diagram of the structure in another exemplary embodiment of the display panel of this disclosure;

[0033] Figure 5 for Figure 2 A schematic diagram of the gate-to-agent (GOA) drive circuit.

[0034] Figure 6a for Figure 5 A schematic diagram of an exemplary embodiment of a shift register unit;

[0035] Figure 6b For Figure 5 A schematic diagram of another exemplary embodiment of the shift register unit;

[0036] Figure 7 for Figure 6a The timing diagram of each node in a driving method for the shift register unit shown is as follows;

[0037] Figure 8 A timing diagram of each signal line in a driving method of the shift register unit shown in FIG. 9A is shown in FIG. 9B. Figure 5 A timing diagram of each signal line in a driving method of the display panel shown in FIG. 1 is shown in FIG. 2.

[0038] Figure 9 A structure diagram of another exemplary embodiment of the gate driving circuit in the display panel of the present disclosure is shown in FIG. 3.

[0039] Figure 10 A timing diagram of each signal line in a driving method of the shift register unit shown in FIG. 9A is shown in FIG. 9B. Figure 9 A timing diagram of each signal line in a driving method of the shift register unit shown in FIG. 9A is shown in FIG. 9B. DETAILED DESCRIPTION

[0040] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same can be omitted.

[0041] The terms "one", "a", "said" are used to indicate that there is one or more of the elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusion of elements / components / etc. in the resulting system, apparatus, etc. and do not preclude additional elements / components / etc.

[0042] As Figure 1The diagram shown is a schematic representation of a pixel driving circuit in the related art. This pixel driving circuit may include a driving circuit 74, a first switching unit 71, a second switching unit 72, a third switching unit 73, and a capacitor C. The driving circuit connects the first node N1, the second node N2, and the third node N3, and is used to input driving current to the third node N3 through the second node N2 in response to the signal of the first node N1. The first terminal of the first switching unit 71 is connected to the first power supply terminal VDD, the second terminal is connected to the second node N2, and the control terminal is connected to the pulse width modulation signal terminal PWM, and is used to connect the first power supply terminal VDD and the second node N2 in response to the pulse width modulation signal of the pulse width modulation signal terminal PWM. The second switching unit 72 is connected to the data signal terminal Da, the first node N1, and the first gate drive signal terminal G1, and is used to connect the first node N1 and the data signal terminal Da in response to the signal of the first gate drive signal terminal G1. The third switching unit 73 is connected to the third node N3, the sensing signal terminal Sense, and the second gate drive signal terminal G2, and is used to connect the third node N3 and the sensing signal terminal Sense in response to the signal of the second gate drive signal terminal G2. The capacitor C is connected between the first node N1 and the third node N3. The third node N3 is used to connect the first electrode of a light-emitting unit OLED, and the other electrode of the light-emitting unit OLED can be connected to the sixth power supply terminal VSS.

[0043] like Figure 1 As shown, the driving circuit 74 may include: a driving transistor DT, the first terminal of which is connected to the second node N2, the second terminal of which is connected to the third node N3, and the gate of which is connected to the first node N1; the first switching unit 71 may include: a first transistor T1, the first terminal of which is connected to the first power supply terminal VDD, the second terminal of which is connected to the second node N2, and the gate of which is connected to the pulse width modulation signal terminal PWM. The second switching unit 72 may include: a second transistor T2, the first terminal of which is connected to the data signal terminal Da, the second terminal of which is connected to the first node N1, and the gate of which is connected to the first gate drive signal terminal G1. The third switching unit 73 may include a third transistor T3, the first terminal of which is connected to the third node N3, the second terminal of which is connected to the sensing signal terminal Sense, and the gate of which is connected to the second gate drive signal terminal G2. The first transistor T1, the second transistor T2, and the third transistor T3 may all be N-type transistors. The first power supply terminal VDD may be a high-level power supply terminal, and the sixth power supply terminal VSS may be a low-level power supply terminal.

[0044] like Figure 1As shown, the pixel driving circuit can turn on the second transistor T2 in the data writing stage, and write the data signal to the first node N1 through the data signal end Da; in the light emitting stage, the first transistor T1 is turned on by the pulse width modulation signal of the pulse width modulation signal end PWM, so as to connect the first power supply end VDD and the second node, and drive the transistor DT to provide driving current to the third node N3 according to the voltage of the first node N1, so as to drive the light emitting unit OLED to emit light. Wherein, the display panel can adjust the duty cycle of the pulse width modulation signal to adjust the brightness of the light emitting unit OLED. However, since the first transistor T1 is in the on state for a long time, the threshold voltage of the first transistor T1 will drift seriously, which will affect the display effect.

[0045] Based on this, the present exemplary embodiment provides a display panel, as shown in Figure 2 、 3 , Figure 2 is a structural schematic diagram of an exemplary embodiment of the display panel of the present disclosure, Figure 3 is Figure 2 a complete structural schematic diagram of the region A in FIG. 8. The display panel can include a plurality of pixel driving circuits Pix, which can be as shown in Figure 1 , wherein, Figure 2 shows the first switch unit 71 in the pixel driving circuit and other circuit structures P in the pixel driving circuit. A plurality of said pixel driving circuits Pix are arrayed along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X can be the row direction, and the second direction Y can be the column direction. A plurality of said pixel driving circuit groups Pz can be formed by a plurality of said pixel driving circuits Pix, and the pixel driving circuit group Pz can include an odd pixel driving circuit row located in an odd row and an even pixel driving circuit row located in an even row, and two pixel driving circuit rows in the pixel driving circuit group Pz can be arranged adjacent in the second direction Y. Wherein, the pixel driving circuit row includes a plurality of said pixel driving circuits Pix distributed along the first direction. As shown in Figure 2 、 3 , in the same pixel driving circuit group Pz, the second ends of the first switch units 71 in two said pixel driving circuits distributed in the second direction Y are connected to each other.

[0046] In the example embodiment, the display panel can provide the pulse width modulation signal to two pixel driving circuit rows in the same pixel driving circuit group in the same frame, and provide the pulse width modulation signal to different pixel driving circuit rows in the same pixel driving circuit group in at least partially different frames. For example, the display panel can provide the pulse width modulation signal to the odd pixel driving circuit row in the first driving period, at this time, the first switch unit 71 in the odd pixel driving circuit row is turned on, and the first power supply end VDD provides the power supply voltage to the second node N2 in the odd pixel driving circuit row and the second node N2 in the even pixel driving circuit row through the first switch unit 71 in the odd pixel driving circuit row, so as to realize that the odd pixel driving circuit row and the even pixel driving circuit row enter the light emitting stage at the same time. The display panel can provide the pulse width modulation signal to the even pixel driving circuit row in the second driving period, at this time, the first switch unit 71 in the even pixel driving circuit row is turned on, and the first power supply end VDD provides the power supply voltage to the second node N2 in the odd pixel driving circuit row and the second node N2 in the even pixel driving circuit row through the first switch unit 71 in the even pixel driving circuit row, so as to realize that the odd pixel driving circuit row and the even pixel driving circuit row enter the light emitting stage at the same time. In the example embodiment, in the first driving period, the first switch unit in the even pixel driving circuit row is not turned on, and the first switch unit in the even pixel driving circuit row can perform threshold recovery in the period. In the second driving period, the first switch unit in the odd pixel driving circuit row is not turned on, and the first switch unit in the odd pixel driving circuit row can perform threshold recovery in the period. Thus, the display panel can improve the problem of threshold drift of the first switch unit described above. The first driving period and the second driving period can include one frame or multiple frames.

[0047] As shown in Figure 2 The display panel can further include a gate driving circuit GOA1 and a gate driving circuit GOA2. The gate driving circuit GOA1 can be configured to provide a gate driving signal to the first gate driving signal end G1 in the pixel driving circuit row by row. The gate driving circuit GOA2 can be configured to provide a gate driving signal to the second gate driving signal end G2 in the pixel driving circuit row by row.

[0048] As shown in Figure 2As shown, the display panel can further include a gate drive circuit GOA, which can include a plurality of output terminals corresponding to the pixel drive circuit rows, and the output terminals are configured to provide the pulse width modulation signal to the control terminals of the first switch units 71 in the pixel drive circuit rows corresponding thereto. The gate drive circuit GOA can be configured to provide the pulse width modulation signal to the odd pixel drive circuit rows or the even pixel drive circuit rows in the same frame, and the gate drive circuit is configured to provide the pulse width modulation signal to the odd pixel drive circuit rows in at least part of the frames, and to provide the pulse width modulation signal to the even pixel drive circuit rows in at least part of the frames.

[0049] In the present example embodiment, as shown in FIG. 1, the second terminals of the first switch units 71 in the same pixel drive circuit row can be connected by a first connection line L1. In the same pixel drive circuit group, the second terminals of the first switch units in two pixel drive circuits distributed adjacently in the second direction Y can be connected by a second connection line L2. The first connection line L1 and the second connection line L2 intersect to form a grid structure, so as to reduce the potential difference of the second nodes in different pixel drive circuits. It should be understood that in other example embodiments, the display panel can also be provided with only the second connection line L2. In addition, in other example embodiments, in the same pixel drive circuit group, the second terminal of any first switch unit can be connected to the second terminal of the first switch unit in any position of the pixel drive circuit in another pixel drive circuit row. For example, in the same pixel drive circuit group, the second terminal of the first switch unit in the first column of pixel drive circuits in the odd pixel drive circuit row can be connected to the second terminal of the first switch unit in the second column of pixel drive circuits in the even pixel drive circuit row. Figure 2 In other example embodiments, the pixel drive circuit group Pz can further include pixel drive circuit rows of other numbers, and the plurality of pixel drive circuit rows in the same pixel drive circuit group Pz can be adjacently arranged. As shown in FIG. 2, the pixel drive circuit group Pz can include an odd pixel drive circuit row and an even pixel drive circuit row, and the pixel drive circuit group Pz can further include a third pixel drive circuit row and a fourth pixel drive circuit row. The third pixel drive circuit row and the fourth pixel drive circuit row can be adjacently arranged between the odd pixel drive circuit row and the even pixel drive circuit row.

[0050] Figure 4 ​As shown in FIG. 6, the display panel in this embodiment of the present disclosure can include a plurality of pixel driving circuit groups Pz, and each pixel driving circuit group Pz can include a plurality of pixel driving circuit rows. In the same pixel driving circuit group Pz, the second end of any first switch unit 71 can be connected to the second end of at least one first switch unit 71 in each pixel driving circuit row. The gate driving circuit GOA can be configured to provide the pulse width modulation signal to a pixel driving circuit subgroup in the same pixel driving circuit group Pz in the same frame, the pixel driving circuit subgroup can include a part of the pixel driving circuit rows in the same pixel driving circuit group Pz, and the gate driving circuit GOA can be configured to provide the pulse width modulation signal to different pixel driving circuit subgroups in the same pixel driving circuit group Pz in at least partially different frames. For example, when the pixel driving circuit subgroup includes one pixel driving circuit row, the display panel can provide the pulse width modulation signal to each pixel driving circuit row in the same pixel driving circuit group Pz in different driving periods, so as to open the first switch unit in each pixel driving circuit row in different time periods, thereby providing sufficient recovery time for the first switch unit. The driving periods can include one frame or multiple frames. When the pixel driving circuit subgroup includes multiple pixel driving circuit rows, the different pixel driving circuit subgroups can have different combinations of pixel driving circuit rows. For example, the pixel driving circuit row in the first row and the pixel driving circuit row in the second row in the same pixel driving circuit group Pz can be provided with the pulse width modulation signal in the first driving period, the pixel driving circuit row in the second row and the pixel driving circuit row in the third row in the same pixel driving circuit group Pz can be provided with the pulse width modulation signal in the second driving period, and the pixel driving circuit row in the third row and the pixel driving circuit row in the fourth row in the same pixel driving circuit group Pz can be provided with the pulse width modulation signal in the third driving period. The above-mentioned arrangement can also provide sufficient recovery time for the first switch unit. In addition, in other exemplary embodiments, the pixel driving circuit in the display panel of the present disclosure can also have other structures, as long as the pixel driving circuit includes a first switch unit connected between the driving transistor and the high-level power supply end, and the pixel driving circuit can improve the threshold drift of the first switch unit through the above-mentioned arrangement.

[0051] In this embodiment of the present disclosure, as shown in FIG. 6, Figure 5 Figure 2 ​Structure diagram of middle gate drive circuit GOA. The gate drive circuit can include: a first gate drive circuit 81, a second gate drive circuit 82, the first gate drive circuit 81 being connected with a first signal input line STUA, a first clock signal line LC1, a second clock signal line LC2, for providing the pulse width modulation signal to the odd pixel drive circuit row in response to the signals of the first signal input line STUA, the first clock signal line LC1, the second clock signal line LC2; the second gate drive circuit 82 being connected with a second signal input line STUB, the first clock signal line LC1, the second clock signal line LC2, for providing the pulse width modulation signal to the even pixel drive circuit row in response to the signals of the second signal input line STUB, the first clock signal line LC1, the second clock signal line LC2.

[0052] In the present exemplary embodiment, as shown in Figure 5 The first gate drive circuit 81 can include a plurality of cascaded shift register units PWM, and the second gate drive circuit 82 can include a plurality of cascaded shift register units PWM. As shown in Figure 6a The first gate drive circuit 81 can include a plurality of cascaded shift register units PWM, and the second gate drive circuit 82 can include a plurality of cascaded shift register units PWM. As shown in Figure 5Fig. 1 is a structural schematic diagram of an exemplary embodiment of a middle shift register unit. The shift register unit can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a pull-down circuit 4, a first output circuit 21, and a second output circuit 22. The first input circuit 11 is connected to a signal input end In, a first clock signal end CK1, and a fourth node N4, and is configured to transmit a signal of the signal input end In to the fourth node N4 in response to a signal of the first clock signal end CK1. The second input circuit 12 is connected to a second power supply end VGH, a second clock signal end CK2, a fifth node N5, and the signal input end In, and is configured to transmit a signal of the second power supply end VGH to the fifth node N5 in response to a signal of the second clock signal end CK2, and to transmit a signal of the second clock signal end CK2 to the fifth node N5 in response to a signal of the signal input end In. The pull-up circuit 3 is connected to the first clock signal end CK1, the fifth node N5, and a sixth node N6, and is configured to transmit a signal of the first clock signal end CK1 to the sixth node N6 in response to signals of the fifth node N5 and the first clock signal end CK1. The pull-down circuit 4 is connected to the fourth node N4, a third power supply end LVGL, and the sixth node N6, and is configured to transmit a signal of the third power supply end LVGL to the sixth node N6 in response to a signal of the fourth node N4. The first output circuit 21 is connected to the fourth node N4, a first output end Out1, and the second power supply end VGH, and is configured to transmit a signal of the second power supply end VGH to the first output end Out1 in response to a signal of the fourth node N4. The second output circuit 22 is connected to the sixth node N6, the third power supply end LVGL, and the first output end Out1, and is configured to transmit a signal of the third power supply end LVGL to the first output end Out1 in response to a signal of the sixth node N6.

[0053] In the example embodiment, the second power supply end VGH can be an effective level end, and the third power supply end LVGL can be an ineffective level end. The shift register unit driving method can include seven stages. In the first stage, the effective level is input to the first clock signal end Ck1, and the ineffective level is input to the second clock signal end CK2 and the signal input end In. The effective level is the potential that can drive the target circuit to work normally. In the first stage, the first input circuit 11 transmits the ineffective level of the signal input end In to the fourth node N4 under the action of the first clock signal end CK1. The fifth node N5 maintains the effective level of the previous stage, and the pull-up circuit 3 transmits the effective level of the first clock signal end CK1 to the sixth node N6 under the action of the effective level of the fifth node N5 and the first clock signal end CK1. The second output circuit 22 transmits the ineffective level of the third power supply end LVGL to the first output end Out1 under the action of the effective level of the sixth node N6. In the second stage, the effective level can be input to the second clock signal end CK2, and the ineffective level can be input to the first clock signal end CK1 and the signal input end In. The second input circuit 12 can transmit the effective level of the second power supply end VGH to the fifth node N5 under the action of the second clock signal end CK2, the fourth node N4 maintains the ineffective level of the previous stage, the sixth node N6 maintains the effective level of the previous stage, and the second output circuit 22 transmits the ineffective level of the third power supply end LVGL to the first output end Out1 under the action of the effective level of the sixth node N6. In the third stage, the effective level is input to the first clock signal end CK1, and the ineffective level is input to the second clock signal end CK2 and the signal input end In. The first input circuit 11 transmits the ineffective level of the signal input end In to the fourth node N4 under the action of the first clock signal end CK1. The fifth node N5 maintains the effective level of the previous stage, and the pull-up circuit 3 transmits the effective level of the first clock signal end CK1 to the sixth node N6 under the action of the effective level of the fifth node N5 and the first clock signal end CK1. The second output circuit 22 transmits the ineffective level of the third power supply end LVGL to the first output end Out1 under the action of the effective level of the sixth node N6. In the fourth stage, the ineffective level is input to the first clock signal end CK1, and the effective level is input to the second clock signal end CK2 and the signal input end In. The second input circuit 12 can transmit the effective level of the second clock signal end CK2 and the second power supply end VGH to the fifth node N5 under the action of the signal input end In and the second clock signal end CK2, the fourth node N4 maintains the ineffective level of the previous stage, the sixth node N6 maintains the effective level of the previous stage, and the second output circuit 22 transmits the ineffective level of the third power supply end LVGL to the first output end Out1 under the action of the effective level of the sixth node N6. In the fifth stage, the ineffective level is input to the second clock signal end CK2, and the effective level is input to the first clock signal end Ck1 and the signal input end In.The first input circuit 11 transmits the active level of the signal input terminal In to the fourth node N4 under the action of the first clock signal terminal CK1. The pull-down circuit 4 transmits the inactive level of the third power supply terminal LVGL to the sixth node N6 under the action of the fourth node N4. The first output circuit 21 transmits the active level of the second power supply terminal VGH to the first output terminal Out1 under the action of the fourth node N4. In the sixth stage, the inactive level is input to the first clock signal terminal CK1 and the signal input terminal In, and the active level is input to the second clock signal terminal CK2. The second input circuit 12 can transmit the active level of the second power supply terminal VGH to the fifth node N5 under the action of the second clock signal terminal CK2. The sixth node N6 maintains the inactive level of the last stage, and the fourth node N4 maintains the active level of the last stage. The first output circuit 21 transmits the active level of the second power supply terminal VGH to the first output terminal Out1 under the action of the fourth node N4. In the seventh stage, the inactive level is input to the second clock signal terminal CK2 and the signal input terminal In, and the active level is input to the first clock signal terminal CK1. The first input circuit 11 transmits the inactive level of the signal input terminal In to the fourth node N4 under the action of the first clock signal terminal CK1. The pull-up circuit 3 transmits the active level of the first clock signal terminal CK1 to the sixth node N6 under the action of the fifth node N5 and the first clock signal terminal CK1, and the second output circuit 22 transmits the inactive level of the third power supply terminal LVGL to the first output terminal Out1 under the action of the active level of the sixth node N6. The shift register unit can realize the shift output of the signal.

[0054] In the example embodiment, as shown in FIG. 1, the first input circuit 11 can include a fourth transistor T4 and a fifth transistor T5. The first electrode of the fourth transistor T4 is connected to the signal input terminal In, the second electrode is connected to a seventh node N7, and the gate electrode is connected to the first clock signal terminal CK1. The first electrode of the fifth transistor T5 is connected to the seventh node N7, the second electrode is connected to the fourth node N4, and the gate electrode is connected to the first clock signal terminal CK1. Figure 6a The second input circuit 12 can include a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The first electrode of the seventh transistor T7 is connected to the second power supply terminal VGH, the second electrode is connected to the fifth node N5, and the gate electrode is connected to the second clock signal terminal CK2. The first electrode of the eighth transistor T8 is connected to the fifth node N5, the second electrode is connected to an eighth node N8, and the gate electrode is connected to the signal input terminal In. The first electrode of the ninth transistor T9 is connected to the eighth node N8, the second electrode is connected to the second clock signal terminal CK2, and the gate electrode is connected to the signal input terminal In.

[0055] In the example embodiment, as shown in FIG. 1, the first input circuit 11 can include a fourth transistor T4 and a fifth transistor T5. The first electrode of the fourth transistor T4 is connected to the signal input terminal In, the second electrode is connected to a seventh node N7, and the gate electrode is connected to the first clock signal terminal CK1. The first electrode of the fifth transistor T5 is connected to the seventh node N7, the second electrode is connected to the fourth node N4, and the gate electrode is connected to the first clock signal terminal CK1. Figure 6aAs shown in the figure, the shift register unit further comprises a first isolation circuit 51, a second isolation circuit 52, the first isolation circuit 51 being connected with the second power supply end VGH, the fourth node N4 and the seventh node N7, and being used for transmitting the signal of the second power supply end VGH to the seventh node N7 in response to the signal of the fourth node N4; the second isolation circuit 52 being connected with the eighth node N8, the second power supply end VGH and the fifth node N5, and being used for transmitting the signal of the second power supply end VGH to the eighth node N8 in response to the signal of the fifth node N5.

[0056] In the example embodiment, as shown in the figure, Figure 6a The first isolation circuit 51 can comprise a sixth transistor T6, the first electrode of the sixth transistor T6 being connected with the seventh node N7, the second electrode being connected with the second power supply end VGH, and the gate electrode being connected with the fourth node N4; and the second isolation circuit 52 can comprise a tenth transistor T10, the first electrode of the tenth transistor T10 being connected with the second power supply end VGH, the second electrode being connected with the eighth node N8, and the gate electrode being connected with the fifth node N5.

[0057] In the example embodiment, as shown in the figure, Figure 6a The pull-up circuit 3 can comprise an eleventh transistor T11, a twelfth transistor T12 and a first capacitor C1, the first electrode of the eleventh transistor T11 being connected with the first clock signal end CK1, the second electrode being connected with the ninth node N9, and the gate electrode being connected with the fifth node N5; the first electrode of the twelfth transistor T12 being connected with the ninth node N9, the second electrode being connected with the sixth node N6, and the gate electrode being connected with the first clock signal end CK1; and the first capacitor C1 can be connected between the fifth node N5 and the ninth node N9. The pull-down circuit 4 can comprise a thirteenth transistor T13, the first electrode of the thirteenth transistor T13 being connected with the third power supply end LVGL, the second electrode being connected with the sixth node N6, and the gate electrode being connected with the fourth node N4. The first capacitor C1 can also be connected between the fifth node N5 and another signal end.

[0058] In the example embodiment, as shown in the figure, Figure 6a The first output circuit 21 can further be connected with a second output end Out2, and be used for transmitting the signal of the second power supply end VGH to the second output end Out2 in response to the signal of the fourth node N4; and the second output circuit 22 can further be connected with the second output end Out2 and the fourth power supply end VGL, and be used for transmitting the signal of the fourth power supply end VGL to the second output end Out2 in response to the signal of the sixth node N6.

[0059] In the example embodiment, as shown in the figure, Figure 6aAs shown in the figure, the first output circuit 21 can include a fourteenth transistor T14, a fifteenth transistor T15, a second capacitor C2, a first electrode of the fourteenth transistor T14 being connected to the second power supply end VGH, a second electrode being connected to the first output end Out1, and a gate being connected to the fourth node N4; a first electrode of the fifteenth transistor T15 being connected to the second power supply end VGH, a second electrode being connected to the second output end Out2, and a gate being connected to the fourth node N4; and the second capacitor C2 can be connected between the fourth node N4 and the first output end Out1. The second output circuit 22 can include a sixteenth transistor T16, a seventeenth transistor T17, a third capacitor C3, a first electrode of the sixteenth transistor T16 being connected to the third power supply end LVGL, a second electrode being connected to the first output end Out1, and a gate being connected to the sixth node N6; a first electrode of the seventeenth transistor T17 being connected to the fourth power supply end VGL, a second electrode being connected to the second output end Out2, and a gate being connected to the sixth node N6; and the third capacitor C3 can be connected between the sixth node N6 and the third power supply end LVGL. In other exemplary embodiments, the second capacitor C2 can also be connected between the fourth node N4 and another signal end, and the third capacitor C3 can also be connected between the sixth node N6 and another signal end.

[0060] In the present exemplary embodiment, as shown in the figure, Figure 6a The shift register unit can further include a reset circuit 6 connected to the fourth node N4, a first clock signal end CK1, a reset signal end TRS, a second power supply end VGH, and a sixth node, for transmitting a signal of the first clock signal end CK1 to the fourth node N4 in response to a signal of the reset signal end TRS, and for transmitting a signal of the second power supply end VGH to the sixth node N6 in response to a signal of the reset signal end TRS.

[0061] In the present exemplary embodiment, as shown in the figure, Figure 6a The reset circuit 6 can include an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20, a first electrode of the eighteenth transistor T18 being connected to the fourth node N4, a second electrode being connected to a tenth node N10, and a gate being connected to the reset signal end TRS; a first electrode of the nineteenth transistor T19 being connected to the tenth node N10, a second electrode being connected to the first clock signal end CK1, and a gate being connected to the reset signal end TRS; a first electrode of the twentieth transistor T20 being connected to the second power supply end VGH, a second electrode being connected to the sixth node N6, and a gate being connected to the reset signal end TRS; and the seventh node N7 is connected to the tenth node N10.

[0062] In the present exemplary embodiment, as shown in the figure, Figure 6aAs shown, the fourth transistor T4 to the twentieth transistor T20 can all be N-type transistors. Correspondingly, the effective driving level of the first input circuit 11, the second input circuit 12, the pull-up circuit 3, the first output circuit 21 and the second output circuit 22 is high level, i.e. the first input circuit 11, the second input circuit 12, the pull-up circuit 3, the first output circuit 21 and the second output circuit 22 can be turned on under high level. In the exemplary embodiment, the second power supply end VGH can be a high level signal end, and the fourth power supply end VGL and the third power supply end LVGL can be low level signal ends.

[0063] As shown in FIG. 1, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 6b As shown in FIG. 1, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 5 FIG. 2 is a structural schematic diagram of another exemplary embodiment of a shift register unit. Figure 6b As shown in FIG. 2, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 6a As shown in FIG. 2, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 6b As shown in FIG. 2, the second output circuit 22 of the shift register unit 1 can further include a twenty-fifth transistor T25. Wherein, a first electrode of the sixteenth transistor T16 is connected to the seventh node N7, a second electrode is connected to the first output end Out1, and a gate is connected to the sixth node N6; a first electrode of the twenty-fifth transistor T25 is connected to the seventh node N7, a second electrode is connected to the third power supply end LVGL, and a gate is connected to the sixth node N6. When the first output end Out1 outputs high level, correspondingly, the fourth node N4 outputs high level, the sixth transistor T6 transmits the high level signal of the second power supply end VGH to the seventh node N7 under the action of the fourth node N4, and the first output end Out1 and the seventh node N7 have a small voltage difference, so that the setting can reduce the leakage current of the first output end Out1 through the sixteenth transistor T16.

[0064] As shown in FIG. 1, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 7 As shown in FIG. 1, the shift register unit 1 can include a first input circuit 11, a second input circuit 12, a pull-up circuit 3, a first output circuit 21 and a second output circuit 22. Figure 6a FIG. 4 is a timing diagram of each node in a driving method of the shift register unit shown in FIG. 2. Wherein, In is a timing diagram of an input signal input end, CK1 is a timing diagram of a first clock signal end, CK2 is a timing diagram of a second clock signal end, N5 is a timing diagram of a fifth node, N4 is a timing diagram of a fourth node, N6 is a timing diagram of a sixth node, Out1 is a timing diagram of a first output end, and Out2 is a timing diagram of a second output end.

[0065] The driving method of the shift register unit can include seven stages. Wherein, as shown in FIG. 4, the first stage is a stage of inputting a high level signal to the input signal input end In, the second stage is a stage of inputting a low level signal to the input signal input end In, the third stage is a stage of inputting a high level signal to the first clock signal end CK1, the fourth stage is a stage of inputting a low level signal to the first clock signal end CK1, the fifth stage is a stage of inputting a high level signal to the second clock signal end CK2, the sixth stage is a stage of inputting a low level signal to the second clock signal end CK2, and the seventh stage is a stage of inputting a high level signal to the second clock signal end CK2. Figure 7As shown in the first stage t1, the first clock signal terminal CK1 is inputted with an effective level, and the second clock signal terminal CK2 and the signal input terminal In are inputted with an ineffective level. The effective level is a potential capable of driving the target circuit to work normally, and in the present exemplary embodiment, the effective level is a high level, and correspondingly, the ineffective level is a low level. In the first stage t1, the fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal terminal CK1, and the signal input terminal In inputs a low level signal to the fourth node. The fifth node N5 maintains the high level signal of the previous stage, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the first clock signal terminal CK1 inputs a high level signal to the sixth node N6, the sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply terminal LVGL inputs a low level signal to the first output terminal Out1, and the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply terminal VGL inputs a low level signal to the second output terminal Out2. In addition, the threshold drift of the eighth transistor T8 and the voltage change of the signal input terminal In due to the voltage rise of the third power supply terminal LVGL can cause the off leakage current of the eighth transistor T8 to increase. In the present exemplary embodiment, in the first stage t1, the tenth transistor T10 is turned on under the action of the fifth node N5, and the second power supply terminal VGH inputs a high level signal to the eighth node N8. This setting can reduce the voltage difference between the fifth node N5 and the eighth node N8, thereby reducing the leakage current of the fifth node N5 through the eighth transistor T8.

[0066] It should be noted that, as Figure 5 shown, the first output terminal Out1 can be cascaded with the signal input terminal In of the adjacent next stage shift register unit, and the second output terminal Out2 can provide a pulse width modulation signal to the pixel driving circuit row corresponding thereto. In the present exemplary embodiment, the voltage of the third power supply terminal LVGL can be smaller than the voltage of the fourth power supply terminal VGL, and the smaller third power supply terminal LVGL can effectively turn off the eighth transistor in the next stage shift register unit, thereby reducing the leakage current of the fifth node. It should be understood that in other exemplary embodiments, the third power supply terminal LVGL can also be shared as the fourth power supply terminal VGL.

[0067] In the second stage t2, the valid level is input to the second clock signal end CK2, and the invalid level is input to the first clock signal end CK1 and the signal input end In. The seventh transistor T7 is turned on under the action of the second clock signal end CK2, the second power supply end VGH inputs the high level signal to the fifth node N5, the fourth node N4 maintains the low level signal of the last stage, the sixth node N6 maintains the high level signal of the last stage, the sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply end LVGL inputs the low level signal to the first output end Out1, the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply end VGL inputs the low level signal to the second output end Out2.

[0068] In the third stage t3, the valid level is input to the first clock signal end CK1, and the invalid level is input to the second clock signal end CK2 and the signal input end In. The fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal end CK1, and the signal input end In inputs the low level signal to the fourth node. The fifth node N5 maintains the high level signal of the last stage, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the first clock signal end CK1 inputs the high level signal to the sixth node N6, the sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply end LVGL inputs the low level signal to the first output end Out1, the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply end VGL inputs the low level signal to the second output end Out2.

[0069] In the fourth stage t4, the invalid level is input to the first clock signal end CK1, and the valid level is input to the second clock signal end CK2 and the signal input end In. The seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, the second power supply end VGH and the second clock signal end CK2 both input the high level signal to the fifth node N5, the fourth node N4 maintains the low level signal of the last stage, the sixth node N6 maintains the high level signal of the last stage, the sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply end LVGL inputs the low level signal to the first output end Out1, the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply end VGL inputs the low level signal to the second output end Out2.

[0070] In the fifth stage t5, an invalid level is input to the second clock signal end CK2, and a valid level is input to the first clock signal end CK1 and the signal input end In. The fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal end CK1, the signal input end In inputs a high level signal to the fourth node N4, the fourteenth transistor T14 is turned on under the action of the fourth node N4, the second power supply end VGH inputs a high level signal to the first output end Out1, the fifteenth transistor T15 is turned on under the action of the fourth node N4, and the second power supply end VGH inputs a high level signal to the second output end Out2. At the same time, the thirteenth transistor T13 is turned on under the action of the fourth node N4, the third power supply end LVGL inputs a low level signal to the sixth node N6, the sixteenth transistor T16 and the seventeenth transistor T17 are turned off under the action of the sixth node N6. The eighth transistor T8 and the ninth transistor T9 are turned on under the action of the signal input end In, and the second clock signal end CK2 inputs a low level signal to the fifth node N5. In addition, the sixth transistor T6 is turned on under the action of the fourth node N4, and the second power supply end VGH inputs a high level signal to the seventh node N7 and the tenth node N10. This setting can reduce the voltage difference between the fourth node N4 and the seventh node N7, and can reduce the voltage difference between the fourth node N4 and the tenth node N10, thereby reducing the drain current of the fourth node N4 through the fifth transistor T5 and the eighteenth transistor T18.

[0071] In the sixth stage t6, an invalid level is input to the first clock signal end CK1 and the signal input end In, and a valid level is input to the second clock signal end CK2. The seventh transistor T7 is turned on under the action of the second clock signal end CK2, the second power supply end VGH inputs a high level signal to the fifth node N5, the sixth node N6 maintains a low level signal of the previous stage, and the fourth node N4 maintains a high level signal of the previous stage. The fourteenth transistor T14 is turned on under the action of the fourth node N4, the second power supply end VGH inputs a high level signal to the first output end Out1, and the fifteenth transistor T15 is turned on under the action of the fourth node N4. The second power supply end VGH inputs a high level signal to the second output end Out2.

[0072] In the seventh stage t7, an invalid level is input to the second clock signal terminal CK2 and the signal input terminal In, and a valid level is input to the first clock signal terminal CK1. The fourth transistor T4 and the fifth transistor T5 are turned on, and the signal input terminal In inputs a low level signal to the fourth node N4. The eleventh transistor T11 is turned on under the action of the fifth node N5, the twelfth transistor T12 is turned on under the action of the first clock signal terminal CK1, and the first clock signal terminal CK1 provides a high level signal to the sixth node N6. The sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply terminal LVGL inputs a low level signal to the first output terminal Out1, and the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply terminal VGL inputs a low level signal to the second output terminal Out2.

[0073] It should be noted that in the present exemplary embodiment, the duration of the high level pulse output by the signal input terminal In can be adjusted according to actual needs. In the period of a single high level pulse output by the signal input terminal In, the first clock signal terminal CK1 outputs at least one high level pulse signal, the second clock signal terminal CK2 outputs at least one high level pulse signal, and when the first clock signal terminal CK1 outputs a high level pulse signal, the second clock signal terminal CK2 outputs a low level signal, and when the second clock signal terminal CK2 outputs a high level pulse signal, the first clock signal terminal CK1 outputs a low level signal. That is, as shown in FIG. 6, in the period of a single high level pulse output by the signal input terminal In, the shift register unit driving method includes at least the fourth stage t4 and the fifth stage t5. Figure 7

[0074] In the present exemplary embodiment, as shown in FIG. 6, the shift register unit driving method includes the first stage t1, the second stage t2, the third stage t3, the fourth stage t4, the fifth stage t5, the sixth stage t6, and the seventh stage t7. Figure 5 ​As shown in the first gate drive circuit 81: the first output terminal Out1 of the current stage shift register unit is connected to the signal input terminal In of the adjacent next stage shift register unit; the first signal input line STUA is connected to the signal input terminal In of the first stage shift register unit in the first gate drive circuit; the first clock signal line LC1 is connected to the first clock signal terminal CK1 of the odd stage shift register unit and the second clock signal terminal CK2 of the even stage shift register unit in the first gate drive circuit, and the second clock signal line LC2 is connected to the first clock signal terminal CK1 of the even stage shift register unit and the second clock signal terminal CK2 of the odd stage shift register unit in the first gate drive circuit. In the second gate drive circuit 82: the first output terminal Out1 of the current stage shift register unit is connected to the signal input terminal In of the adjacent next stage shift register unit; the second signal input line STUB is connected to the signal input terminal In of the first stage shift register unit in the second gate drive circuit; the first clock signal line LC1 is connected to the first clock signal terminal CK1 of the odd stage shift register unit and the second clock signal terminal CK2 of the even stage shift register unit in the second gate drive circuit, and the second clock signal line LC2 is connected to the first clock signal terminal CK1 of the even stage shift register unit and the second clock signal terminal CK2 of the odd stage shift register unit in the second gate drive circuit. In addition, the display panel can further include a reset signal line LTRS connected to the reset signal terminals of all the shift register units.

[0075] As Figure 8 shown, the first gate drive circuit 81 and the second gate drive circuit 82 are connected to the first gate line G1 and the second gate line G2 of the display panel respectively, and the first gate drive circuit 81 and the second gate drive circuit 82 are connected to the first gate line G1 and the second gate line G2 of the display panel respectively. Figure 5A timing diagram of each signal line in a driving method of the display panel is shown. Wherein, SUTA is a timing diagram of the first signal input line, STUB is a timing diagram of the second signal input line, LC1 is a timing diagram of the first clock signal line LC1, LC2 is a timing diagram of the second clock signal line, and LTRS is a timing diagram of the reset signal line. In this frame, the first signal input line STUA outputs a high-level pulse signal, and the shift register units in the first gate drive circuit 81 output pulse width modulation signals step by step to provide the pulse width modulation signals to the odd pixel drive circuit rows row by row. The second signal input line STUB continuously outputs a low-level signal, and each shift register unit in the second gate drive circuit 82 continuously outputs a low-level. It should be understood that in other frames, the second signal input line STUB can output a high-level pulse signal, and the shift register units in the second gate drive circuit 82 output pulse width modulation signals step by step to provide the pulse width modulation signals to the even pixel drive circuit rows row by row. The first signal input line STUA can continuously output a low-level signal, and each shift register unit in the first gate drive circuit 81 continuously outputs a low-level. Thus, the display panel can realize the time-sharing conduction of the first transistor in the odd pixel drive circuit row and the first transistor in the even pixel drive circuit row, thereby improving the threshold shift problem of the first transistor. In addition, the first gate drive circuit 81 and the second gate drive circuit 82 alternately output pulse width modulation signals, and this setting can also provide sufficient threshold recovery time for the fourteenth transistor T14, the sixteenth transistor T16 and other transistors in the shift register unit. For example, when the first gate drive circuit 81 outputs the pulse width modulation signal, the gate of the fourteenth transistor T14 in the first gate drive circuit is at a high level for a long time, and the gate of the sixteenth transistor T16 is at a low level for a long time. When the second gate drive circuit 82 outputs the pulse width modulation signal, the gate of the fourteenth transistor T14 in the first gate drive circuit is at a low level for a long time, and the gate of the sixteenth transistor T16 is at a high level for a long time. This setting can improve the stability of the gate drive circuit.

[0076] As shown in Figure 8 A frame F includes a blank period F1 and a scanning period F2, and the reset signal line LTRS can output a high-level signal in the blank period F1 of the first frame to turn on the eighteenth transistor T18, the nineteenth transistor T19 and the twentieth transistor T20 in each shift register unit, so as to reset the sixth node N6 through the second power supply end VGH and reset the fourth node N4 through the first clock signal end CK1. At this stage, the signal of the first clock signal end CK1 can be a low-level signal. In addition, Figure 8 The black dot area in the middle is an omitted area of the timing diagram.

[0077] In the present exemplary embodiment, as shown in Figure 9As shown in FIG. 8, the gate driving circuit can further include a plurality of cascaded shift register units PWM corresponding to the pixel driving circuit groups Pz, and a plurality of output control circuits 9 corresponding to the shift register units PWM. The shift register units PWM are configured to output the pulse width modulation signals through output ends. The output control circuits 9 are configured to be connected to the output ends of the corresponding shift register units PWM, fifth power supply ends VGL5, first control signal ends VDDA, second control signal ends VDDB, third output ends Out3, and fourth output ends Out4. The output control circuits 9 are configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the third output ends Out3 in response to signals of the first control signal ends VDDA, and transmit signals of the fifth power supply ends VGL5 to the fourth output ends Out4 in response to signals of the first control signal ends VDDA. The output control circuits 9 are further configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the fourth output ends Out4 in response to signals of the second control signal ends VDDB, and transmit signals of the fifth power supply ends VGL5 to the third output ends Out3 in response to signals of the second control signal ends VDDB. The third output ends Out3 are configured to provide the pulse width modulation signals to the odd pixel driving circuit rows corresponding to the output control circuits, and the fourth output ends Out4 are configured to provide the pulse width modulation signals to the even pixel driving circuit rows corresponding to the output control circuits. The output control circuits 9 and the pixel driving circuit rows corresponding to the same shift register units correspond to each other.

[0078] As shown in FIG. 8, the gate driving circuit can further include a plurality of cascaded shift register units PWM corresponding to the pixel driving circuit groups Pz, and a plurality of output control circuits 9 corresponding to the shift register units PWM. The shift register units PWM are configured to output the pulse width modulation signals through output ends. The output control circuits 9 are configured to be connected to the output ends of the corresponding shift register units PWM, fifth power supply ends VGL5, first control signal ends VDDA, second control signal ends VDDB, third output ends Out3, and fourth output ends Out4. The output control circuits 9 are configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the third output ends Out3 in response to signals of the first control signal ends VDDA, and transmit signals of the fifth power supply ends VGL5 to the fourth output ends Out4 in response to signals of the first control signal ends VDDA. The output control circuits 9 are further configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the fourth output ends Out4 in response to signals of the second control signal ends VDDB, and transmit signals of the fifth power supply ends VGL5 to the third output ends Out3 in response to signals of the second control signal ends VDDB. The third output ends Out3 are configured to provide the pulse width modulation signals to the odd pixel driving circuit rows corresponding to the output control circuits, and the fourth output ends Out4 are configured to provide the pulse width modulation signals to the even pixel driving circuit rows corresponding to the output control circuits. The output control circuits 9 and the pixel driving circuit rows corresponding to the same shift register units correspond to each other. Figure 9 As shown in FIG. 8, the gate driving circuit can further include a plurality of cascaded shift register units PWM corresponding to the pixel driving circuit groups Pz, and a plurality of output control circuits 9 corresponding to the shift register units PWM. The shift register units PWM are configured to output the pulse width modulation signals through output ends. The output control circuits 9 are configured to be connected to the output ends of the corresponding shift register units PWM, fifth power supply ends VGL5, first control signal ends VDDA, second control signal ends VDDB, third output ends Out3, and fourth output ends Out4. The output control circuits 9 are configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the third output ends Out3 in response to signals of the first control signal ends VDDA, and transmit signals of the fifth power supply ends VGL5 to the fourth output ends Out4 in response to signals of the first control signal ends VDDA. The output control circuits 9 are further configured to transmit the pulse width modulation signals of the output ends of the shift register units PWM to the fourth output ends Out4 in response to signals of the second control signal ends VDDB, and transmit signals of the fifth power supply ends VGL5 to the third output ends Out3 in response to signals of the second control signal ends VDDB. The third output ends Out3 are configured to provide the pulse width modulation signals to the odd pixel driving circuit rows corresponding to the output control circuits, and the fourth output ends Out4 are configured to provide the pulse width modulation signals to the even pixel driving circuit rows corresponding to the output control circuits. The output control circuits 9 and the pixel driving circuit rows corresponding to the same shift register units correspond to each other.

[0079] In the example embodiment, the twenty-first transistor T21 to the twenty-fourth transistor T24 can be N-type transistors, and the fifth power supply end VGL5 can be a low-level signal end. The shift register unit in the gate drive circuit can be driven as shown in Figure 6a

[0080] As shown in Figure 10 , a timing diagram of each node in a driving method of the shift register unit shown in Figure 9 . Wherein VDDA is a timing diagram of the first control signal end, and VDDB is a timing diagram of the second control signal end. The driving method of the shift register unit can include two driving periods: a first driving period t1 and a second driving period t2. In the first driving period t1, a low-level signal is input to the first control signal end VDDA, a high-level signal is input to the second control signal end VDDB, the twenty-first transistor T21 and the twenty-fourth transistor T24 are turned on, the twenty-second transistor T22 and the twenty-third transistor T23 are turned off, and the plurality of output control circuits 9 transmit the pulse width modulation signal output by the shift register unit to the odd pixel drive circuit row. In the second driving period t2, a high-level signal is input to the first control signal end VDDA, a low-level signal is input to the second control signal end VDDB, the twenty-first transistor T21 and the twenty-fourth transistor T24 are turned off, the twenty-second transistor T22 and the twenty-third transistor T23 are turned on, and the plurality of output control circuits 9 transmit the pulse width modulation signal output by the shift register unit to the even pixel drive circuit row. Thus, the display panel can realize the time-sharing conduction of the first transistor in the odd pixel drive circuit row and the first transistor in the even pixel drive circuit row, thereby improving the threshold voltage shift problem of the first transistor. The first driving period t1 and the second driving period t2 described above can include one frame or multiple frames. The voltage of the high-level stage of the first control signal end VDDA and the second control signal end VDDB can be equal to the voltage of the second power supply end VGH in the shift register unit, and the voltage of the low-level stage of the first control signal end VDDA and the second control signal end VDDB can be equal to the voltage of the third power supply end LVGL in the shift register unit.

[0081] The example embodiment also provides a display panel driving method for driving the display panel described above, the display panel driving method comprising:

[0082] The pulse width modulation signal is provided to a pixel drive circuit sub-group in the same pixel drive circuit group in the same frame, a part of the pixel drive circuit rows in the pixel drive circuit group form the pixel drive circuit sub-group, and the pulse width modulation signal is provided to different pixel drive circuit sub-groups in the same pixel drive circuit group in at least part of different frames.

[0083] ​The above has been described in detail for the driving method, and will not be repeated here.

[0084] The present exemplary embodiments also provide a display device, wherein the display device can include the display panel described above. The display device can be a display device of a mobile phone, a tablet computer, or a television.

[0085] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure that come within the scope of the following claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0086] It should be understood that the present disclosure is not limited to the precise structures herein described and illustrated in the drawings and that various modifications and changes can be made therein without departing from the scope thereof. The scope of the present disclosure is indicated by the appended claims rather than by the specification and figures alone.

Claims

1. A display panel, wherein, The display panel comprises: a plurality of pixel driving circuits, the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect, the plurality of pixel driving circuits form a plurality of pixel driving circuit groups, each pixel driving circuit group comprises a plurality of pixel driving circuit rows, the pixel driving circuit row comprises a plurality of pixel driving circuits arranged along the first direction, the pixel driving circuit comprises: a driving circuit connected to a first node, a second node and a third node, configured to input a driving current to the third node through the second node in response to a signal of the first node; a first switch unit having a first end connected to a first power supply end and a second end connected to the second node, configured to connect the first power supply end and the second node in response to a pulse width modulation signal; wherein, in the same pixel driving circuit group, the second end of any first switch unit is connected to the second end of at least one first switch unit in each pixel driving circuit row.

2. The display panel of claim 1, wherein, The driving circuit comprises: a driving transistor having a first pole connected to the second node, a second pole connected to the third node and a gate connected to the first node; The first switch unit comprises: a first transistor having a first pole connected to the first power supply end, a second pole connected to the second node and a gate connected to a pulse width modulation signal end; The pixel driving circuit further comprises: a second transistor having a first pole connected to a data signal end, a second pole connected to the first node and a gate connected to a first gate drive signal end; a third transistor having a first pole connected to the third node, a second pole connected to a sensing signal end and a gate connected to a second gate drive signal end; a capacitor connected between the first node and the third node.

3. The display panel of claim 1, wherein, The display panel further comprises: a gate drive circuit, the gate drive circuit comprises a plurality of output ends, the output ends are arranged correspondingly to the pixel driving circuit rows, and the output ends are configured to provide the pulse width modulation signal to the control end of the first switch unit in the pixel driving circuit row corresponding to the output end; The gate drive circuit is configured to provide the pulse width modulation signal to a pixel driving circuit subgroup in the same pixel driving circuit group in the same frame, a part of the pixel driving circuit rows in the pixel driving circuit group form the pixel driving circuit subgroup, and the gate drive circuit is configured to provide the pulse width modulation signal to different pixel driving circuit subgroups in the same pixel driving circuit group in at least part of different frames.

4. The display panel of claim 1, wherein, The pixel driving circuit group comprises a plurality of pixel driving circuit rows adjacent in the second direction, and the second ends of the first switch units in the plurality of pixel driving circuits arranged in the second direction in the same pixel driving circuit group are connected to each other.

5. The display panel of claim 3, wherein, The pixel driving circuit subgroup comprises one pixel driving circuit row, the pixel driving circuit group comprises an odd pixel driving circuit row located in an odd row and an even pixel driving circuit row located in an even row, and two pixel driving circuit rows in the pixel driving circuit group are arranged adjacent in the second direction; The gate driving circuit is configured to provide the pulse width modulation signal to the odd pixel driving circuit rows or the even pixel driving circuit rows in the same frame, and the gate driving circuit is configured to provide the pulse width modulation signal to the odd pixel driving circuit rows in at least part of the frames, and to provide the pulse width modulation signal to the even pixel driving circuit rows in at least part of the frames. 6.The display panel of claim 5, wherein, The gate driving circuit comprises: a first gate driving circuit connected with a first signal input line, a first clock signal line and a second clock signal line, and configured to provide the pulse width modulation signal to the odd pixel driving circuit rows in response to signals of the first signal input line, the first clock signal line and the second clock signal line; a second gate driving circuit connected with a second signal input line, the first clock signal line and the second clock signal line, and configured to provide the pulse width modulation signal to the even pixel driving circuit rows in response to signals of the second signal input line, the first clock signal line and the second clock signal line.

7. The display panel of claim 6, wherein, The first gate driving circuit comprises a plurality of cascaded shift register units, and the second gate driving circuit comprises a plurality of cascaded shift register units. The shift register unit comprises: a first input circuit connected with a signal input end, a first clock signal end and a fourth node, and configured to transmit a signal of the signal input end to the fourth node in response to a signal of the first clock signal end; a second input circuit connected with a second power supply end, a second clock signal end, a fifth node and the signal input end, and configured to transmit a signal of the second power supply end to the fifth node in response to a signal of the second clock signal end, and to transmit a signal of the second clock signal end to the fifth node in response to a signal of the signal input end; a pull-up circuit connected with the first clock signal end, the fifth node and a sixth node, and configured to transmit a signal of the first clock signal end to the sixth node in response to signals of the fifth node and the first clock signal end; a pull-down circuit connected with the fourth node, a third power supply end and the sixth node, and configured to transmit a signal of the third power supply end to the sixth node in response to a signal of the fourth node; a first output circuit connected with the fourth node, a first output end and the second power supply end, and configured to transmit a signal of the second power supply end to the first output end in response to a signal of the fourth node; a second output circuit connected with the sixth node, the third power supply end and the first output end, and configured to transmit a signal of the third power supply end to the first output end in response to a signal of the sixth node.

8. The display panel of claim 7, wherein, The first input circuit comprises: a fourth transistor with a first electrode connected with the signal input end, a second electrode connected with a seventh node and a gate electrode connected with the first clock signal end; a fifth transistor with a first electrode connected with the seventh node, a second electrode connected with the fourth node and a gate electrode connected with the first clock signal end; The second input circuit comprises: a seventh transistor with a first electrode connected with the second power supply end, a second electrode connected with the fifth node and a gate electrode connected with the second clock signal end; An eighth transistor has a first electrode connected to the fifth node, a second electrode connected to an eighth node, and a gate electrode connected to the signal input terminal; A ninth transistor has a first electrode connected to the eighth node, a second electrode connected to the second clock signal terminal, and a gate electrode connected to the signal input terminal.

9. The display panel of claim 8, wherein, The shift register unit further comprises: A first isolation circuit is connected to the second power terminal, a fourth node, and a seventh node, and is configured to transmit a signal of the second power terminal to the seventh node in response to a signal of the fourth node; A second isolation circuit is connected to the eighth node, the second power terminal, and a fifth node, and is configured to transmit a signal of the second power terminal to the eighth node in response to a signal of the fifth node.

10. The display panel of claim 9, wherein, The first isolation circuit comprises: A sixth transistor has a first electrode connected to the seventh node, a second electrode connected to the second power terminal, and a gate electrode connected to the fourth node; The second isolation circuit comprises: A tenth transistor has a first electrode connected to the second power terminal, a second electrode connected to the eighth node, and a gate electrode connected to the fifth node.

11. The display panel of claim 7, wherein, The pull-up circuit comprises: An eleventh transistor has a first electrode connected to the first clock signal terminal, a second electrode connected to a ninth node, and a gate electrode connected to the fifth node; A twelfth transistor has a first electrode connected to the ninth node, a second electrode connected to the sixth node, and a gate electrode connected to the first clock signal terminal; A first capacitor is connected to the fifth node; The pull-down circuit comprises: A thirteenth transistor has a first electrode connected to the third power terminal, a second electrode connected to the sixth node, and a gate electrode connected to the fourth node.

12. The display panel of claim 7, wherein The first output circuit is further connected to a second output terminal, and is configured to transmit a signal of the second power terminal to the second output terminal in response to a signal of the fourth node; The second output circuit is further connected to the second output terminal and a fourth power terminal, and is configured to transmit a signal of the fourth power terminal to the second output terminal in response to a signal of the sixth node; The first output terminal or the second output terminal forms an output terminal of the gate drive circuit.

13. The display panel of claim 12, wherein, The effective driving level of the first input circuit, the second input circuit, the pull-up circuit, the first output circuit, and the second output circuit is a high level; The second power terminal is a high level signal terminal, the fourth power terminal and the third power terminal are both low level signal terminals, and the voltage of the third power terminal is lower than the voltage of the fourth power terminal.

14. The display panel of claim 12, wherein, The first output circuit comprises: A fourteenth transistor has a first electrode connected to the second power terminal, a second electrode connected to the first output terminal, and a gate electrode connected to the fourth node; A fifteenth transistor has a first electrode connected to the second power terminal, a second electrode connected to the second output terminal, and a gate electrode connected to the fourth node; A second capacitor is connected to the fourth node; The second output circuit comprises: A sixteenth transistor has a first electrode connected to the third power terminal, a second electrode connected to the first output terminal, and a gate electrode connected to the sixth node; A seventeenth transistor has a first electrode connected to the fourth power terminal, a second electrode connected to the second output terminal, and a gate electrode connected to the sixth node; A third capacitor is connected to the sixth node.

15. The display panel of claim 9, wherein, The second output circuit comprises: A sixteenth transistor, a first electrode of which is connected to the seventh node, a second electrode of which is connected to the first output terminal, and a gate of which is connected to the sixth node; A twenty-fifth transistor, a first electrode of which is connected to the seventh node, a second electrode of which is connected to the third power terminal, and a gate of which is connected to the sixth node; A third capacitor, connected to the sixth node.

16. The display panel of claim 7, wherein, The shift register unit further comprises: A reset circuit, connected to the fourth node, the first clock signal terminal, the reset signal terminal, the second power terminal, and the sixth node, configured to transmit a signal of the first clock signal terminal to the fourth node in response to a signal of the reset signal terminal, and configured to transmit a signal of the second power terminal to the sixth node in response to a signal of the reset signal terminal.

17. The display panel of claim 16, wherein, The first input circuit comprises: A fourth transistor, a first electrode of which is connected to the signal input terminal, a second electrode of which is connected to the seventh node, and a gate of which is connected to the first clock signal terminal; A fifth transistor, a first electrode of which is connected to the seventh node, a second electrode of which is connected to the fourth node, and a gate of which is connected to the first clock signal terminal; The shift register unit further comprises: A first isolation circuit, connected to the second power terminal, the fourth node, and the seventh node, configured to transmit a signal of the second power terminal to the seventh node in response to a signal of the fourth node; The reset circuit comprises: An eighteenth transistor, a first electrode of which is connected to the fourth node, a second electrode of which is connected to the tenth node, and a gate of which is connected to the reset signal terminal; A nineteenth transistor, a first electrode of which is connected to the tenth node, a second electrode of which is connected to the first clock signal terminal, and a gate of which is connected to the reset signal terminal; A twentieth transistor, a first electrode of which is connected to the second power terminal, a second electrode of which is connected to the sixth node, and a gate of which is connected to the reset signal terminal; The seventh node is connected to the tenth node.

18. The display panel of claim 7, wherein, In the first gate drive circuit: The first output terminal of the shift register unit of the current stage is connected to the signal input terminal of the shift register unit of the adjacent next stage; The first signal input line is connected to the signal input terminal of the shift register unit of the first stage in the first gate drive circuit; The first clock signal line is connected to the first clock signal terminal of the odd-numbered stage shift register unit and the second clock signal terminal of the even-numbered stage shift register unit in the first gate drive circuit, and the second clock signal line is connected to the first clock signal terminal of the even-numbered stage shift register unit and the second clock signal terminal of the odd-numbered stage shift register unit in the first gate drive circuit; In the second gate drive circuit: The first output terminal of the shift register unit of the current stage is connected to the signal input terminal of the shift register unit of the adjacent next stage; The second signal input line is connected to the signal input terminal of the shift register unit of the first stage in the second gate drive circuit; The first clock signal line is connected to the first clock signal terminal of the odd-numbered stage shift register unit and the second clock signal terminal of the even-numbered stage shift register unit in the second gate drive circuit, and the second clock signal line is connected to the first clock signal terminal of the even-numbered stage shift register unit and the second clock signal terminal of the odd-numbered stage shift register unit in the second gate drive circuit.

19. The display panel of claim 5, wherein, The gate drive circuit comprises: a plurality of cascaded shift register units, which are arranged correspondingly with the pixel drive circuit groups, and are used to output the pulse width modulation signals through output ends; a plurality of output control circuits, which are arranged correspondingly with the shift register units, and are connected with the output ends, fifth power supply ends, first control signal ends, second control signal ends, third output ends and fourth output ends of the corresponding shift register units, and are used to transmit the pulse width modulation signals of the output ends of the shift register units to the third output ends and transmit signals of the fifth power supply ends to the fourth output ends in response to signals of the first control signal ends, and are used to transmit the pulse width modulation signals of the output ends of the shift register units to the fourth output ends and transmit signals of the fifth power supply ends to the third output ends in response to signals of the second control signal ends; wherein the third output ends and the fourth output ends form output ends of the gate drive circuit, the third output ends are used to provide the pulse width modulation signals to odd pixel drive circuit rows corresponding to the output control circuits, and the fourth output ends are used to provide the pulse width modulation signals to even pixel drive circuit rows corresponding to the output control circuits.

20. The display panel of claim 19, wherein, The output control circuit comprises: a twenty-first transistor, whose first pole is connected with an output end of the corresponding shift register unit, whose second pole is connected with the third output end, and whose gate is connected with the first control signal end; a twenty-second transistor, whose first pole is connected with an output end of the corresponding shift register unit, whose second pole is connected with the fourth output end, and whose gate is connected with the second control signal end; a twenty-third transistor, whose first pole is connected with the fifth power supply end, whose second pole is connected with the third output end, and whose gate is connected with the second control signal end; a twenty-fourth transistor, whose first pole is connected with the fifth power supply end, whose second pole is connected with the fourth output end, and whose gate is connected with the first control signal end.

21. A display panel driving method, wherein, The display panel drive method is used to drive the display panel of any one of claims 1-20, and comprises: providing the pulse width modulation signals to a pixel drive circuit subgroup in the same pixel drive circuit group in the same frame, and providing the pulse width modulation signals to different pixel drive circuit subgroups in the same pixel drive circuit group in at least partially different frames.

22. A display device comprising: The display device comprises the display panel of any one of claims 1-20.

Images