Method, device and apparatus for generating a quantum chip layout, and method and apparatus for optimizing a device

Abstract

The application relates to the technical field of quantum chips, and discloses a quantum chip layout generation method and device, a device optimization method and equipment, which comprises the following steps: determining the single-arm length of a bit capacitor based on the area of a theoretical capacitance value or a bit capacitance; generating the layout of the bit capacitor by using the single-arm length and a first drawing template; determining the length of a resonant cavity based on a theoretical resonant frequency; generating the layout of the resonant cavity by using the length of the resonant cavity and a second drawing module; and merging the layout of the bit capacitor and the layout of the resonant cavity by using a layout template to form a quantum chip layout, wherein the layout template comprises first position information and second position information, the first position information is position information of the layout of a target device, the second position information is relative position information between the layout of the bit capacitor and the layout of the resonant cavity, and the target device is the bit capacitor or the resonant cavity. The application can reduce the design work of the quantum chip layout and improve the generation efficiency of the quantum chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum chip, and particularly relates to a quantum chip layout generation method and device, a device optimization method and equipment. BACKGROUND

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. The quantum computer has the characteristics of fast running speed and strong information processing capability. Among them, the superconducting quantum chip, as the core device of the quantum computer, is the key to the performance of the quantum computer. At present, the Xmon type superconducting quantum bit is mostly used in the superconducting quantum chip, and mainly consists of a bit capacitor (i.e. a cross capacitor), a superconducting quantum interference device (SQUID), a measurement resonant cavity and a control line. The SQUID is formed by two Josephson junctions.

[0003] At present, in the design process of the quantum chip layout, the designer needs to calculate the geometric size of the bit capacitor and the resonant cavity, and draw the layout of the bit capacitor and the layout of the resonant cavity on the substrate (substrate) based on the obtained geometric size in the layout design tool. This operation process is relatively cumbersome, and the design efficiency of the quantum chip layout is low. SUMMARY

[0004] Therefore, the present application provides a quantum chip layout generation method and device, a device optimization method and equipment to solve the problem of low design efficiency of the quantum chip layout.

[0005] In a first aspect, the present application provides a quantum chip layout generation method, which comprises: determining the single-arm length of a bit capacitor based on a theoretical capacitance value or the area of the bit capacitor; generating the layout of the bit capacitor by using the single-arm length and a first drawing template, wherein the first drawing template is a drawing template of the bit capacitor; determining the length of a resonant cavity based on a theoretical resonant frequency; generating the layout of the resonant cavity by using the length of the resonant cavity and a second drawing template, wherein the second drawing template is a drawing template of the resonant cavity; and merging the layout of the bit capacitor and the layout of the resonant cavity by using a layout template to form a quantum chip layout, wherein the layout template comprises first position information and second position information, the first position information is the position information of the layout of a target device, the second position information is the relative position information between the layout of the bit capacitor and the layout of the resonant cavity, and the target device is the bit capacitor or the resonant cavity.

[0006] The method for generating a quantum chip layout provided in this embodiment includes: generating a layout of a bit capacitor based on a single-arm length and a first drawing template; generating a layout of a resonant cavity based on a length of the resonant cavity and a second drawing template; and merging the layout of the bit capacitor and the layout of the resonant cavity by using a layout template to form a layout of a quantum chip. Through the above steps, a designer only needs to set some initial parameters to automatically generate the layout of the quantum chip, thereby greatly reducing the design work of the layout of the quantum chip, effectively reducing the demand for personnel, and improving the generation efficiency of the layout of the quantum chip.

[0007] In an optional implementation, the determining the single-arm length of the bit capacitor based on the area of the theoretical capacitance value or the bit capacitor includes: determining the single-arm length of the bit capacitor based on the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value; or determining the single-arm length of the bit capacitor based on a first parameter and the theoretical capacitance value, the first parameter being a ratio of the first single-arm width to the second single-arm width; or determining the single-arm length of the bit capacitor based on the area and the first single-arm width.

[0008] In this embodiment, the way of determining the single-arm length of the bit capacitor can be flexibly selected according to actual conditions, thereby avoiding a situation that the layout of the bit capacitor cannot be generated due to an unknown parameter.

[0009] In an optional implementation, the determining the single-arm length of the bit capacitor based on the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value includes: determining the single-arm length based on the first single-arm width, the second single-arm width, and the theoretical capacitance value by using the following formula:

[0010]

[0011] wherein L is the single-arm length, C is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε is a substrate dielectric constant, W is the first single-arm width, and W is the second single-arm width. t r gap

[0012] In an optional implementation, the determining the single-arm length of the bit capacitor based on the first parameter and the theoretical capacitance value includes: determining the single-arm length based on the first parameter and the theoretical capacitance value by using the following formula:

[0013]

[0014] wherein L is the single-arm length, C is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε is a substrate dielectric constant, W is the first single-arm width, and W is the second single-arm width. t ​​​wherein, γ is a preset cavity frequency offset value, ε is a preset substrate dielectric constant, n is the first parameter. r wherein, γ is a preset cavity frequency offset value, ε is a preset substrate dielectric constant, n is the first parameter.

[0015] In an optional implementation, the determining the single-arm length of the bit capacitor based on the area and the first single-arm width comprises: determining the single-arm length based on the area of the bit capacitor and the first single-arm width by the following formula:

[0016]

[0017] wherein, L is the single-arm length, S is the area, and W is the first single-arm width.

[0018] In an optional implementation, the determining the length of the resonant cavity based on the theoretical resonant frequency comprises: determining the length of the resonant cavity based on the theoretical resonant frequency, the speed of the microwave in free space, and the dielectric constant of the substrate.

[0019] In an optional implementation, after the generating the layout of the bit capacitor by using the single-arm length and the first drawing template, the method further comprises: inputting the layout of the bit capacitor into a first simulation module, determining a simulation capacitance value of the bit capacitor based on an output of the first simulation module; in a case where a first difference between the simulation capacitance value and the theoretical capacitance value is greater than or equal to a preset capacitance value, adjusting the layout of the bit capacitor so that the first difference is less than the preset capacitance value; after the generating the layout of the resonant cavity by using the length of the resonant cavity and a second drawing module, the method further comprises: inputting the layout of the resonant cavity into a second simulation module, determining a simulation resonant frequency of the resonant cavity based on an output of the second simulation module; in a case where a second difference between the simulation resonant frequency and the theoretical resonant frequency is greater than or equal to a preset resonant frequency, adjusting the layout of the resonant cavity so that the second difference is less than the preset resonant frequency; and the merging the layout of the bit capacitor and the layout of the resonant cavity by using the layout template comprises: merging the adjusted layout of the bit capacitor and the adjusted layout of the resonant cavity by using the layout template.

[0020] The method for generating a quantum chip layout provided in this embodiment can verify whether the capacitance value of the layout of the bit capacitor reaches the theoretical capacitance value by using a first simulation module and whether the resonant frequency of the layout of the bit resonant cavity reaches the theoretical resonant frequency by using a second simulation module before generating the quantum chip layout, so that the operation steps of actual verification can be reduced, the design cycle of the quantum chip layout can be shortened, and the cost can be reduced.

[0021] In an optional implementation, the method further includes: determining, based on the layout of the bit capacitor, a geometric parameter of the bit capacitor, the geometric parameter including at least one of a single-arm length of the bit capacitor, a first single-arm width of the bit capacitor, a second single-arm width of the bit capacitor, a first parameter, and an area of the bit capacitor; and determining, based on the geometric parameter, an actual capacitance value of the bit capacitor.

[0022] The method for generating a quantum chip layout provided in the embodiment can determine an actual capacitance value of a bit capacitor based on the layout of the bit capacitor after determining the layout of the bit capacitor, and thus can facilitate a designer to quickly learn the actual capacitance value of the bit capacitor in each quantum chip layout.

[0023] In an optional implementation, the determining, based on the layout of the bit capacitor, of the geometric parameter of the bit capacitor includes: determining coordinate information of a plurality of pixel points corresponding to an image of the layout of the bit capacitor; and determining the geometric parameter based on the coordinate information of the plurality of pixel points.

[0024] In an optional implementation, the method further includes: determining, based on the layout of the resonant cavity, a length of the resonant cavity; and determining, based on the length of the resonant cavity, an actual resonant frequency of the resonant cavity.

[0025] The method for generating a quantum chip layout provided in the embodiment can determine an actual resonant frequency of a resonant cavity based on the layout of the resonant cavity after determining the layout of the resonant cavity, and thus can facilitate a designer to quickly learn the actual resonant frequency of the resonant cavity in each quantum chip layout.

[0026] In an optional implementation, the determining, based on the layout of the resonant cavity, of the length of the resonant cavity includes: determining coordinate information of a plurality of pixel points corresponding to an image of the layout of the resonant cavity; and determining the length of the resonant cavity based on the coordinate information of the plurality of pixel points.

[0027] In a second aspect, the present application provides a device for generating a quantum chip layout, the device comprising: a first determining module configured to determine a single-arm length of a bit capacitor based on an area of the bit capacitor or a theoretical capacitance value; a first processing module configured to generate a layout of the bit capacitor by using the single-arm length and a first drawing template, the first drawing template being a drawing template of the bit capacitor; a second determining module configured to determine a length of a resonant cavity based on a theoretical resonant frequency; a second processing module configured to generate a layout of the resonant cavity by using the length of the resonant cavity and a second drawing module, the second drawing template being a drawing template of the resonant cavity; and a drawing module configured to combine the layout of the bit capacitor and the layout of the resonant cavity to form a quantum chip layout by using a layout template, the layout template comprising first position information and second position information, the first position information being position information of a target device, the second position information being relative position information between the layout of the bit capacitor and the layout of the resonant cavity, the target device being the bit capacitor or the resonant cavity.

[0028] In an optional implementation, the first determining module comprises: a first determining unit configured to determine the single-arm length of the bit capacitor based on a first single-arm width of the bit capacitor, a second single-arm width of the bit capacitor, and the theoretical capacitance value; or a second determining unit configured to determine the single-arm length of the bit capacitor based on a first parameter and the theoretical capacitance value, the first parameter being a ratio of the first single-arm width to the second single-arm width; or a third determining unit configured to determine the single-arm length of the bit capacitor based on an area of the bit capacitor, the first single-arm width, and the theoretical capacitance value.

[0029] In an optional implementation, the first determining unit comprises: a first determining sub-unit configured to determine the single-arm length by the following formula based on the first single-arm width, the second single-arm width, and the theoretical capacitance value:

[0030]

[0031] wherein L is the single-arm length, C t is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε r is a substrate dielectric constant, W is the first single-arm width, and W gap is the second single-arm width.

[0032] In an optional implementation, the second determining unit comprises: a second determining sub-unit configured to determine the single-arm length by the following formula based on the first parameter and the theoretical capacitance value:

[0033]

[0034] wherein L is the single-arm length, S is the area of the bit capacitor, and W is the first single-arm width. t wherein C is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε is a substrate dielectric constant, and n is the first parameter. r wherein C is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε is a substrate dielectric constant, and n is the first parameter.

[0035] In an optional implementation, the third determining unit comprises a third determining sub-unit, configured to determine the single-arm length based on the area of the bit capacitor and the first single-arm width according to the following formula:

[0036]

[0037] wherein L is the single-arm length, S is the area of the bit capacitor, and W is the first single-arm width.

[0038] In an optional implementation, the second determining module comprises a fourth determining unit, configured to determine the length of the resonant cavity based on the theoretical resonant frequency, the speed of microwave in free space, and the dielectric constant of the substrate.

[0039] In an optional implementation, the apparatus further comprises a third processing module, configured to input the layout of the bit capacitor into a first simulation module, and determine a simulation capacitance value of the bit capacitor based on an output of the first simulation module; a first adjusting module, configured to, in a case where a first difference between the simulation capacitance value and the theoretical capacitance value is greater than or equal to a preset capacitance value, adjust the layout of the bit capacitor so that the first difference is less than the preset capacitance value; a fourth processing module, configured to input the layout of the resonant cavity into a second simulation module, and determine a simulation resonant frequency of the resonant cavity based on an output of the second simulation module; a second adjusting module, configured to, in a case where a second difference between the simulation resonant frequency and the theoretical resonant frequency is greater than or equal to a preset resonant frequency, adjust the layout of the resonant cavity so that the second difference is less than the preset resonant frequency; and the drawing module comprises a first drawing unit, configured to combine the adjusted layout of the bit capacitor and the adjusted layout of the resonant cavity by using the layout template.

[0040] In an optional implementation, the apparatus further comprises a third determining module, configured to determine a geometric parameter of the bit capacitor based on the layout of the bit capacitor, the geometric parameter comprising at least one of a single-arm length of the bit capacitor, a first single-arm width of the bit capacitor, a second single-arm width of the bit capacitor, a first parameter, and an area of the bit capacitor; and a fourth determining module, configured to determine an actual capacitance value of the bit capacitor based on the geometric parameter.

[0041] In an optional implementation, the third determining module further includes: a fifth determining unit, configured to determine coordinate information of a plurality of pixel points corresponding to an image of the layout of the bit capacitor; and a sixth determining unit, configured to determine the geometric parameter based on the coordinate information of the plurality of pixel points.

[0042] In an optional implementation, the apparatus further includes: a fifth determining module, configured to determine a length of the resonant cavity based on the layout of the resonant cavity; and a sixth determining module, configured to determine an actual resonant frequency of the resonant cavity based on the length of the resonant cavity.

[0043] In an optional implementation, the fifth determining module further includes: a seventh determining unit, configured to determine coordinate information of a plurality of pixel points corresponding to an image of the layout of the resonant cavity; and an eighth determining unit, configured to determine the length of the resonant cavity based on the coordinate information of the plurality of pixel points.

[0044] In a third aspect, the present application provides an optimization method of a quantum chip layout generation apparatus, applied to a client, the client including a first apparatus, the first apparatus being the quantum chip layout generation apparatus of the second aspect or any of the possible implementation modes thereof, the first apparatus being configured with a first version number, the method including: obtaining a second version number configured in a second apparatus, the second apparatus being the quantum chip layout generation apparatus stored in a server; in a case where the second version number is greater than the first version number, obtaining the second apparatus; and updating the first apparatus based on the second apparatus.

[0045] The optimization method of the quantum chip layout generation apparatus provided in the present embodiment can update the quantum chip layout generation apparatus loaded by the client in real time, improve the use performance of the generation apparatus, and facilitate the rapid update and maintenance of the generation apparatus.

[0046] In a fourth aspect, the present application provides an optimization apparatus of a quantum chip layout generation apparatus, the apparatus including: a first obtaining module, configured to obtain a second version number configured in a second apparatus, the second apparatus being the quantum chip layout generation apparatus stored in a server; a second obtaining module, configured to obtain the second apparatus in a case where the second version number is greater than a first version number; and an updating module, configured to update the first apparatus based on the second apparatus.

[0047] In a fifth aspect, the present application provides a computer device, comprising a memory and a processor, which are connected with each other in communication, and the memory stores computer instructions, and the processor executes the method of the first aspect or any of the corresponding embodiments thereof, or the method of the third aspect or any of the corresponding embodiments thereof by executing the computer instructions.

[0048] In a sixth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the method of the first aspect or any of the corresponding embodiments thereof, or the method of the third aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0050] Figure 1 is a flowchart of a method for generating a quantum chip layout according to an embodiment of the present application;

[0051] Figure 2 is a schematic diagram of a bit capacitance layout according to an embodiment of the present application;

[0052] Figure 3 is a schematic diagram of a resonant cavity layout according to an embodiment of the present application;

[0053] Figure 4 is a flowchart of another method for generating a quantum chip layout according to an embodiment of the present application;

[0054] Figure 5 is a flowchart of still another method for generating a quantum chip layout according to an embodiment of the present application;

[0055] Figure 6 is a structural block diagram of a quantum chip layout generation device according to an embodiment of the present application;

[0056] Figure 7 is a flowchart of an optimization method of a quantum chip layout generation device according to an embodiment of the present application;

[0057] Figure 8 is a structural block diagram of an optimization device of a quantum chip layout generation device according to an embodiment of the present application;

[0058] Figure 9 Fig. 1 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0060] The present application provides a method for generating a quantum chip layout, which can be applied to a terminal device such as a computer.

[0061] The method for generating a quantum chip layout provided by the present application can automatically generate a quantum chip layout by only setting some initial parameters by a designer, greatly reducing the design work of the quantum chip layout, and effectively reducing the personnel demand and improving the generation efficiency of the quantum chip layout.

[0062] According to the embodiments of the present application, a method for generating a quantum chip layout is provided. It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0063] In the present embodiment, a method for generating a quantum chip layout is provided, which can be applied to the above-mentioned mobile terminal such as a mobile phone, a tablet computer and the like. Figure 1 Fig. 1 is a flowchart of a method for generating a quantum chip layout according to an embodiment of the present application, which comprises the following steps as shown in Fig. 1: Figure 1

[0064] In step S101, the length of a single arm of a bit capacitor is determined based on the area of a theoretical capacitance value or a bit capacitance.

[0065] The theoretical capacitance value is a preset value, which can be input by a designer through a man-machine interactive device (such as a mouse, a keyboard or a touch screen, etc.) according to the demand. For example, the theoretical capacitance value can be 20 Farad (F) or 40 F, etc.

[0066] Specifically, the length of a single arm of a bit capacitor (also called a cross capacitor) can be the straight line distance between point a and point b in the bit capacitor as shown in Fig. 2. Figure 2

[0067] ​​In step S102, a layout of the bit capacitor is generated by using the single-arm length and a first drawing template.

[0068] The first drawing template is a drawing template of the bit capacitor.

[0069] Specifically, after the single-arm length of the bit capacitor is determined, the single-arm length can be input into the first drawing template, and the first drawing template outputs a generated layout of the bit capacitor according to the single-arm length. For example, the layout of the bit capacitor can be as shown in FIG. 2B. Figure 2

[0070] In step S103, a length of the resonant cavity is determined based on the theoretical resonant frequency.

[0071] The theoretical resonant frequency is a preset value, which can be input by a designer through a human-computer interaction device according to a requirement. For example, the theoretical resonant frequency can be 6.31 gigahertz (GHz) or 6.34 GHz, etc. Specifically, the length l of the resonant cavity can be a curve length from point c to point d in the resonant cavity as shown in FIG. 3B. Figure 3

[0072] For example, the resonant cavity can be a quarter-wavelength superconducting resonant cavity (coplanar waveguide resonant cavity). The coplanar waveguide resonant cavity is widely used for reading the state information of the superconducting quantum bit due to high design freedom, simple preparation process, convenient coupling with the quantum bit, easy integration, and avoidance of some uncontrollable deviations of capacitance and inductance.

[0073] In step S104, a layout of the resonant cavity is generated by using the length of the resonant cavity and a second drawing template.

[0074] The second drawing template is a drawing template of the bit capacitor.

[0075] Specifically, after the length of the resonant cavity is determined, the length of the resonant cavity can be input into the second drawing template, and the second drawing template outputs a generated layout of the resonant cavity according to the length of the resonant cavity. For example, the layout of the resonant cavity can be as shown in FIG. 4B. Figure 3 Figure 3 The dashed box in FIG. 4B is a finger portion of the resonant cavity. The influence of the finger portion of the resonant cavity on the resonant frequency can be ignored.

[0076] In step S105, the layout of the quantum chip is formed by merging the layout of the bit capacitor and the layout of the resonant cavity by using a layout template.

[0077] ​​​The layout template includes first position information and second position information. The first position information is position information of a layout of a target device. The target device is a bit capacitor or a resonant cavity. That is, the first position information is position information of a layout of a bit capacitor, or the first position information is position information of a layout of a resonant cavity. The second position information is relative position information between the layout of the bit capacitor and the layout of the resonant cavity. For example, the position information can be coordinate information of a plurality of pixel points in an image of the layout of the bit capacitor. The relative position information can be a difference between first coordinate information and second coordinate information. The first coordinate information can be coordinate information of a first pixel point, which is one of a plurality of pixel points corresponding to the layout of the bit capacitor. The second coordinate information can be coordinate information of a second pixel point, which is one of a plurality of pixel points corresponding to the layout of the resonant cavity.

[0078] Specifically, after determining the layout of the target device, position information of the layout of the target device on the substrate can be further determined, and the position information of the target device is output to a record document. The record document forms a layout template based on the second position information and the first position information. Then, other devices are laid out on the substrate by using the layout template. When the target device is a bit capacitor, the other device is a resonant cavity. When the target device is a resonant cavity, the other device is a bit capacitor.

[0079] For example, after determining the layout of the bit capacitor and the position information of the layout of the bit capacitor on the substrate, the position coordinates of the layout of the bit capacitor can be output to a record document, and the second position information can be set in the record document to form a layout template. Then, when the resonant cavity is laid out, the position coordinates output by the layout template are directly referenced to realize automatic layout of the resonant cavity, and thus a quantum chip layout is formed.

[0080] For example, the position information of the layout of the target device on the substrate can be randomly determined, or the position information of the layout of the target device on the substrate can be configured in advance by a designer.

[0081] It should be understood that, since the relative positions of the resonant cavity and the bit capacitor are fixed in the existing structure of the quantum chip, a parent-child dynamic relationship can be formed between the bit capacitor and the resonant cavity. The target device can be set as a parent, and the other device can be set as a child. The parent can change with the child, or can not change with the child. The child can change with the parent, or can not change with the parent. That is, when the parent changes in position due to structure or other reasons, the position of the child can change according to the parent, which provides convenience for modification and optimization of the quantum chip layout.

[0082] The method for generating a quantum chip layout provided by the embodiment generates a layout of a bit capacitor based on a single-arm length and a first drawing template, generates a layout of a resonant cavity based on a length of the resonant cavity and a second drawing template, and merges the layout of the bit capacitor and the layout of the resonant cavity by using a layout template to form a layout of a quantum chip. Through the above steps, a designer only needs to set some initial parameters to automatically generate a quantum chip layout, which greatly reduces the design work of the quantum chip layout, effectively reduces the demand for personnel, and improves the generation efficiency of the quantum chip layout.

[0083] The implementation of step S101 (determining the single-arm length of the bit capacitor based on the theoretical capacitance value or the area of the bit capacitor) in the embodiment is described in detail below.

[0084] In a first mode, the single-arm length of the bit capacitor is determined based on the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value.

[0085] Specifically, in the case where the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value are known, the single-arm length of the bit capacitor can be determined according to a first corresponding relationship. The first corresponding relationship is used to represent the corresponding relationship between the first single-arm width, the second single-arm width, and the theoretical capacitance value and the single-arm length.

[0086] In some optional embodiments, the first corresponding relationship can be a corresponding relationship table of the first single-arm width, the second single-arm width, and the theoretical capacitance value and the single-arm length, or a mapping function between the first single-arm width, the second single-arm width, the theoretical capacitance value, and the single-arm length.

[0087] For example, the first corresponding relationship can be as shown in formula (1). Specifically, in the case where the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value are known, the single-arm length of the bit capacitor is determined by the following formula (1).

[0088]

[0089] wherein L is the single-arm length of the bit capacitor, C t is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε r is a substrate dielectric constant, and W is the first single-arm width of the bit capacitor, i.e., the single-arm width of the bit capacitor. As shown in FIG. 1, the straight-line distance between the two inner side walls of the single arm of the bit capacitor is the single-arm width W. Figure 2 gap W is the second single-arm width of the bit capacitor, i.e., the distance from the bit capacitor to the ground. As shown in FIG. 1, the straight-line distance between the inner side wall and the outer side wall of the single arm of the bit capacitor is the distance W Figure 2 gap from the bit capacitor to the ground.​​

[0090] In a second mode, a single-arm length of the bit capacitor is determined based on the first parameter and the theoretical capacitance value.

[0091] The first parameter can be a ratio between the first single-arm width and the second single-arm width. For example, if the first single-arm width is 24 micrometers (um) and the second single-arm width is also 24 um, the first parameter is 1 = 24 um / 24 um.

[0092] Specifically, in a case where the first parameter and the theoretical capacitance value are known, the single-arm length of the bit capacitor can be determined according to a second correspondence relationship. The second correspondence relationship is used to represent a correspondence between the first parameter and the theoretical capacitance value and the single-arm length.

[0093] In some optional embodiments, the second correspondence relationship can be a correspondence table of the first parameter and the theoretical capacitance value and the single-arm length, or a mapping function among the first parameter, the theoretical capacitance value and the single-arm length.

[0094] For example, the second correspondence relationship can be shown in formula (2). Specifically, in a case where the first parameter and the theoretical capacitance value are known, the single-arm length of the bit capacitor can be determined by formula (2) as follows.

[0095]

[0096] wherein L is the single-arm length of the bit capacitor, C t is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε r is a substrate dielectric constant, n is the first parameter, n = W / W gap , W is the first single-arm width of the bit capacitor, and W gap is the second single-arm width of the bit capacitor.

[0097] In a case where the single-arm length of the bit capacitor is determined by the second mode, the step S102 is specifically generating a layout of the bit capacitor by using the single-arm length, a target width and the first drawing template. The target width is the first single-arm width or the second single-arm width. For example, the target width is an empirical value, for example, the target width can be 24 um. The target width can be input into a quantum chip layout generation device by a designer through a human-computer interaction device.

[0098] In a third mode, a single-arm length of the bit capacitor is determined based on an area of the bit capacitor and the first single-arm width.

[0099] Specifically, in a case where the area of the bit capacitor and the first single-arm width are known, the single-arm length of the bit capacitor can be determined according to a third correspondence relationship. The third correspondence relationship is used to represent the correspondence relationship between the area and the first single-arm width and the single-arm length.

[0100] In some optional embodiments, the third correspondence relationship can be a correspondence relationship table of the area and the first single-arm width and the single-arm length, or a mapping function among the area, the first single-arm width and the single-arm length.

[0101] For example, the third correspondence relationship can be shown in formula (3). Specifically, in a case where the first single-arm width of the bit capacitor, the area of the bit capacitor and the theoretical resonant frequency are known, the single-arm length of the bit capacitor can be determined by formula (3) as follows.

[0102]

[0103] wherein L is the single-arm length of the bit capacitor, S is the area of the bit capacitor, and W is the first single-arm width of the bit capacitor. For example, as shown in formula (2), the area S of the bit capacitor is 4LW+S1. S1 is the area of the rectangular frame shown in formula (1), S1=W Figure 2 Figure 2 2 .

[0104] In a case where the single-arm length of the bit capacitor is determined by the third mode, the step S102 is specifically to generate the layout of the bit capacitor by using the single-arm length, the second single-arm width and the first drawing template. The second single-arm width can be an empirical value. For example, the second single-arm width can be 24 um.

[0105] In this embodiment, the mode of determining the single-arm length of the bit capacitor can be flexibly selected according to actual conditions, so as to avoid the case where the layout of the bit capacitor cannot be generated due to unknown parameters.

[0106] For example, the first correspondence relationship, the second correspondence relationship and / or the third correspondence relationship can be pre-stored in the quantum chip layout generation device.

[0107] The implementation mode of the step S103 (determining the length of the resonant cavity based on the theoretical resonant frequency) of this embodiment will be described in detail below.

[0108] For example, the length of the resonant cavity can be determined based on the theoretical resonant frequency, the speed of the microwave in free space and the dielectric constant of the substrate.

[0109] Specifically, in a case where the theoretical resonant frequency, the speed of the microwave in free space and the dielectric constant of the substrate are known, the length of the resonant cavity can be determined by formula (4) as follows.

[0110] ​​

[0111] wherein, l is the length of the resonant cavity, c is the speed of microwave in free space, ε r is the dielectric constant of the substrate, f t is the theoretical resonant frequency. Exemplarily, the substrate can be sapphire, in the case of sapphire as the substrate, ε r = 10. The speed of microwave in free space is a constant value, c = 3 x 10 8 m / s.

[0112] In the embodiment, a method for generating a quantum chip layout is provided, which can be used in the mobile terminal as described above, such as a mobile phone, a tablet computer, etc. Figure 4 is a flowchart of another method for generating a quantum chip layout according to an embodiment of the present application, as shown in the figure, the method comprises the following steps: Figure 4

[0113] In step S401, the length of a single arm of the bit capacitor is determined based on the theoretical capacitance value or the area of the bit capacitor.

[0114] For details, please refer to step S101 of the embodiment shown in the figure, which will not be repeated here. Figure 1

[0115] In step S402, the layout of the bit capacitor is generated by using the length of the single arm and a first drawing template.

[0116] For details, please refer to step S102 of the embodiment shown in the figure, which will not be repeated here. Figure 1

[0117] In step S403, the layout of the bit capacitor is input into a first simulation module, and the simulation capacitance value of the bit capacitor is determined based on the output of the first simulation module.

[0118] wherein, the first simulation module is used to determine the capacitance value (denoted as simulation capacitance value) of the bit capacitor based on the layout of the bit capacitor. Exemplarily, the first simulation module can be a simulation application program such as Comsol.

[0119] In step S404, in the case that the first difference between the simulation capacitance value and the theoretical capacitance value is greater than or equal to a preset capacitance value, the layout of the bit capacitor is adjusted so that the first difference is less than the preset capacitance value.

[0120] ​​​Specifically, after the simulation capacitance value of the layout of the bit capacitor is determined by the first simulation module, if the first difference between the simulation capacitance value and the theoretical capacitance value is greater than or equal to the preset capacitance value, the layout of the bit capacitor is adjusted (for example, the geometric parameter value of the single-arm length, the first single-arm width or the second single-arm width of the bit capacitor is reduced). Then, the adjusted layout of the bit capacitor is input into the first simulation module again, and the simulation capacitance value of the bit capacitor is determined again until the first difference is less than the preset capacitance value.

[0121] The preset capacitance value can be configured by a designer, for example, the preset capacitance value can be 2F.

[0122] For example, assuming that the preset capacitance value is 2F and the theoretical capacitance value is 40F, if the first generated layout of the bit capacitor is input into the first simulation module, the obtained simulation capacitance value is 37F, at this time (40F-37F) > 2F, that is, the first difference is greater than the preset capacitance value, then the layout of the bit capacitor is adjusted (for example, the single-arm length is increased), and the second generated layout of the bit capacitor is obtained. If the second generated layout of the bit capacitor is input into the first simulation module, the obtained simulation capacitance value is 39F, at this time (40F-39F) < 2F, that is, the first difference is less than the preset capacitance value, then the adjustment of the layout of the bit capacitor is stopped. If the second generated layout of the bit capacitor is input into the first simulation module, the obtained simulation capacitance value is 38F, at this time (40F-38F) = 2F, that is, the first difference is equal to the preset capacitance value, then the adjustment of the layout of the bit capacitor is continued until the first difference is less than the preset capacitance value.

[0123] In step S405, the length of the resonant cavity is determined based on the theoretical resonant frequency.

[0124] For details, please refer to Figure 1 In step S103 of the embodiment shown, details are not repeated here.

[0125] In step S406, the layout of the resonant cavity is generated by using the length of the resonant cavity and the second drawing module.

[0126] For details, please refer to Figure 1 In step S104 of the embodiment shown, details are not repeated here.

[0127] In step S407, the layout of the resonant cavity is input into the second simulation module, and the simulation resonant frequency of the resonant cavity is determined based on the output of the second simulation module.

[0128] The second simulation module is used to determine the resonant frequency (denoted as a simulation resonant frequency) of the resonant cavity based on the layout of the resonant cavity. For example, the second simulation module can be a simulation application program such as sonnet based on the method of moments or HFSS based on the finite element method.

[0129] Step S408, in a case that the second difference between the simulated resonant frequency and the theoretical resonant frequency is greater than or equal to the preset resonant frequency, adjusting the layout of the resonant cavity so that the second difference is less than the preset resonant frequency.

[0130] Specifically, after determining the simulated resonant frequency of the resonant cavity by the second simulation module, if the second difference between the simulated resonant frequency and the theoretical resonant frequency is greater than or equal to the preset resonant frequency, adjusting the layout of the resonant cavity (for example, reducing the length of the gradient resonant cavity). Then, inputting the adjusted layout of the resonant cavity into the second simulation module again, determining the simulated resonant frequency of the resonant cavity again until the second difference is less than the preset resonant frequency.

[0131] The preset resonant frequency can be configured by a designer, for example, the preset resonant frequency can be 20 Hz or 30 Hz.

[0132] Specifically, the process of adjusting the layout of the resonant cavity is similar to the process of adjusting the layout of the bit capacitance, which will not be described in detail here.

[0133] Step S409, merging the adjusted layout of the bit capacitance and the adjusted layout of the resonant cavity by using the layout template to form the layout of the quantum chip.

[0134] Specifically, in a case that the first difference is less than the preset capacitance value and the second difference is less than the preset resonant frequency, merging the adjusted layout of the bit capacitance and the adjusted layout of the resonant cavity according to the layout template again.

[0135] The method for generating the layout of the quantum chip provided in the embodiment can reduce the operation steps of actual verification, shorten the design cycle of the layout of the quantum chip, and reduce the cost by verifying whether the capacitance value of the layout of the bit capacitance reaches the theoretical capacitance value through the first simulation module and verifying whether the resonant frequency of the layout of the bit resonant cavity reaches the theoretical resonant frequency through the second simulation module before generating the layout of the quantum chip.

[0136] In the embodiment, a method for generating the layout of the quantum chip is provided, which can be used in the mobile terminal such as a mobile phone, a tablet computer and the like. Figure 5 is a flow diagram of another method for generating the layout of the quantum chip according to an embodiment of the application, as shown in Figure 5 The method comprises the following steps:

[0137] Step S501, determining the single-arm length of the bit capacitance based on the theoretical capacitance value or the area of the bit capacitance.

[0138] For details, refer to the step S101 of the embodiment shown in Figure 1 which will not be described here.

[0139] In step S502, a layout of the bit capacitor is generated by using the single-arm length and the first drawing template.

[0140] For details, please refer to Figure 1 In step S102 of the embodiment shown, no further elaboration is given here.

[0141] In step S503, the length of the resonant cavity is determined based on the theoretical resonant frequency.

[0142] For details, please refer to Figure 1 In step S103 of the embodiment shown, no further elaboration is given here.

[0143] In step S504, a layout of the resonant cavity is generated by using the length of the resonant cavity and the second drawing template.

[0144] For details, please refer to Figure 1 In step S104 of the embodiment shown, no further elaboration is given here.

[0145] In step S505, the layout of the quantum chip is formed by merging the layout of the bit capacitor and the layout of the resonant cavity by using the layout template.

[0146] For details, please refer to Figure 1 In step S105 of the embodiment shown, no further elaboration is given here.

[0147] In step S506, the geometric parameters of the bit capacitor are determined based on the layout of the bit capacitor.

[0148] The geometric parameters include at least one of the single-arm length of the bit capacitor, the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, the first parameter, and the area of the bit capacitor.

[0149] In some optional embodiments, the geometric parameters such as the single-arm length, the first single-arm width, and the second single-arm width of the bit capacitor can be determined by a measurement tool.

[0150] In another optional embodiment, step S506 includes:

[0151] In step a1, the coordinate information of a plurality of pixel points corresponding to an image of the layout of the bit capacitor is determined.

[0152] Specifically, a two-dimensional coordinate system is established with any one vertex in the graph corresponding to the layout of the bit capacitor in the image as the origin, and the coordinate information of the pixel points corresponding to the internal curves of the graph is extracted to obtain N coordinate information. For example, the N coordinate information can be (x0, y0), (x1, y1),..., (xN, yN). Wherein, N is an integer greater than or equal to 12. N N

[0153] ​​Step a2, determining the geometric parameter based on the coordinate information of the plurality of pixel points.

[0154] Exemplarily, in the case that the geometric parameter is the area, the area of the bit capacitor can be determined by the following formula (5).

[0155]

[0156] wherein S is the area of the bit capacitor, (x i , y i ) represents the coordinate information of the i-th pixel point, (x i+1 , y i+1 ) is the coordinate information of the i+1-th pixel point. The coordinate information of the i-th pixel point is the horizontal relative distance and the vertical relative distance between the i-th pixel point and the 0-th pixel point (coordinate zero or coordinate origin).

[0157] Step S507, determining the actual capacitance value of the bit capacitor based on the geometric parameter.

[0158] Exemplarily, in the case that the single-arm length, the first single-arm width and the second single-arm width of the bit capacitor are known, the actual capacitance value of the bit capacitor can be determined by the following formula (6).

[0159]

[0160] wherein C a is the actual capacitance value, L is the single-arm length of the bit capacitor, γ is a preset cavity frequency offset value, ε r is the substrate dielectric constant, W is the first single-arm width of the bit capacitor, and W gap is the second single-arm width of the bit capacitor.

[0161] Exemplarily, in the case that the area, the first single-arm width and the second single-arm width of the bit capacitor are known, the actual capacitance value of the bit capacitor can be determined by the following formula (7).

[0162]

[0163] wherein C a is the actual capacitance value, L is the single-arm length of the bit capacitor, S is the area of the bit capacitor, γ is a preset cavity frequency offset value, ε r is the substrate dielectric constant, W is the first single-arm width of the bit capacitor, and W gap is the second single-arm width of the bit capacitor.

[0164] Exemplarily, in the case that the single-arm length and the first parameter of the bit capacitor are known, the actual capacitance value of the bit capacitor can be determined by the following formula (8).

[0165] Exemplarily, in the case that the single-arm length and the first parameter of the bit capacitor are known, the actual capacitance value of the bit capacitor can be determined by the following formula (8).

[0166] wherein C is the actual capacitance value, L is the single-arm length of the bit capacitance, n is the first parameter, γ is a preset cavity frequency offset value, ε is the substrate dielectric constant, and W is the second single-arm width of the bit capacitance. a r

[0167] Exemplarily, in a case where the area, the single-arm length, and the second single-arm width of the bit capacitance are known, the actual capacitance value of the bit capacitance can be determined by the following formula (9).

[0168]

[0169] wherein C is the actual capacitance value, L is the single-arm length of the bit capacitance, S is the area of the bit capacitance, γ is a preset cavity frequency offset value, ε is the substrate dielectric constant, and W is the second single-arm width of the bit capacitance. a r gap

[0170] In step S508, the length of the resonant cavity is determined based on the layout of the resonant cavity.

[0171] In some optional embodiments, the length of the resonant cavity can be determined by a measurement tool.

[0172] In some other optional embodiments, step S508 comprises:

[0173] In step b1, coordinate information of a plurality of pixel points corresponding to an image of the layout of the resonant cavity is determined.

[0174] Specifically, a two-dimensional coordinate system is established with any vertex in the pattern corresponding to the layout of the resonant cavity in the image as the origin, and coordinate information of pixel points corresponding to internal curves of the pattern is extracted to obtain M coordinate information. Exemplarily, the M coordinate information can be (x0, y0), (x1, y1),..., (xM-1, yM-1). Wherein M is an integer greater than or equal to 2. M M

[0175] In step b2, the length of the resonant cavity is determined based on the coordinate information of the plurality of pixel points.

[0176] Exemplarily, after the coordinate information of the plurality of pixel points is determined, the length of the resonant cavity can be determined by the following formula (10).

[0177]

[0178] wherein l is the length of the resonant cavity, (x0, y0), (x1, y1),..., (xM-1, yM-1) are the coordinate information of the plurality of pixel points, and M is an integer greater than or equal to 2. i i ​​​​​​​​represents coordinate information of the i-th pixel point, (x i+1 , y i+1 ) is coordinate information of the i+1-th pixel point. The coordinate information of the i-th pixel point is a horizontal relative distance and a vertical relative distance between the i-th pixel point and the 0-th pixel point (coordinate zero or coordinate origin).

[0179] In step S509, the actual resonance frequency of the resonant cavity is determined based on the length of the resonant cavity.

[0180] Specifically, after the length of the resonant cavity is determined, the actual resonance frequency of the resonant cavity can be determined by the following formula (11).

[0181]

[0182] where f a is the actual resonance frequency, c is the speed of microwave in free space, c = 3 x 10 8 m / s, l is the length of the resonant cavity, and ε r is the dielectric constant of the substrate.

[0183] The method for generating a quantum chip layout provided in this embodiment can facilitate designers to quickly understand the actual capacitance values of the bit capacitances and the actual resonance frequencies of the resonant cavities in various quantum chip layouts after the layout of the bit capacitances and the layout of the resonant cavities are determined.

[0184] In this embodiment, a device for generating a quantum chip layout is also provided, which is used to implement the above-described embodiments and preferred embodiments, and details are not repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0185] This embodiment provides a device for generating a quantum chip layout, as shown in FIG. 6, the device comprises: Figure 6

[0186] The first determining module 601 is configured to determine the single-arm length of the bit capacitance based on the theoretical capacitance value or the area of the bit capacitance.

[0187] The first processing module 602 is configured to generate the layout of the bit capacitance by using the single-arm length and a first drawing template, the first drawing template being a drawing template of the bit capacitance.

[0188] The second determining module 603 is configured to determine the length of the resonant cavity based on the theoretical resonance frequency. ​

[0189] The second processing module 604 is configured to generate a layout of the resonant cavity by using the length of the resonant cavity and a second drawing module, and the second drawing module is a drawing template of the resonant cavity.

[0190] The drawing module 605 is configured to combine the layout of the bit capacitor and the layout of the resonant cavity by using a layout template to form a quantum chip layout, the layout template comprises first position information and second position information, the first position information is position information of a target device, the second position information is relative position information between the layout of the bit capacitor and the layout of the resonant cavity, and the target device is the bit capacitor or the resonant cavity.

[0191] In some optional embodiments, the first determining module 601 comprises:

[0192] The first determining unit is configured to determine the single-arm length of the bit capacitor based on the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, and the theoretical capacitance value; or

[0193] The second determining unit is configured to determine the single-arm length of the bit capacitor based on the first parameter and the theoretical capacitance value, and the first parameter is a ratio of the first single-arm width to the second single-arm width; or

[0194] The third determining unit is configured to determine the single-arm length of the bit capacitor based on the area and the first single-arm width.

[0195] In some optional embodiments, the first determining unit comprises:

[0196] The first determining sub-unit is configured to determine the single-arm length by the following formula based on the first single-arm width, the second single-arm width, and the theoretical capacitance value:

[0197]

[0198] wherein, L is the single-arm length, C t is the theoretical capacitance value, γ is a preset cavity frequency offset value, ε r is a substrate dielectric constant, W is the first single-arm width, and W gap is the second single-arm width.

[0199] In some optional embodiments, the second determining unit comprises:

[0200] The second determining sub-unit is configured to determine the single-arm length by the following formula based on the first parameter and the theoretical capacitance value:

[0201]

[0202] wherein, L is the single-arm length, C t is the theoretical capacitance value, γ is a preset cavity frequency offset value, εr wherein k is a dielectric constant of the substrate, n is a first parameter.

[0203] In some alternative embodiments, the third determining unit comprises:

[0204] The third determining sub-unit is configured to determine the single-arm length of the bit capacitor based on the area of the bit capacitor and the first single-arm width according to the following formula:

[0205]

[0206] wherein L is the single-arm length, S is the area, and W is the first single-arm width.

[0207] In some alternative embodiments, the second determining module 603 comprises:

[0208] The fourth determining unit is configured to determine the length of the resonant cavity based on the theoretical resonant frequency, the propagation speed of the free-space electromagnetic wave, and the dielectric constant of the substrate.

[0209] In some alternative embodiments, the apparatus further comprises:

[0210] The third processing module is configured to input the layout of the bit capacitor into the first simulation module, and determine the simulation capacitance value of the bit capacitor based on the output of the first simulation module.

[0211] The first adjusting module is configured to, in a case where a first difference between the simulation capacitance value and the theoretical capacitance value is greater than or equal to a preset capacitance value, adjust the layout of the bit capacitor so that the first difference is less than the preset capacitance value.

[0212] The fourth processing module is configured to input the layout of the resonant cavity into the second simulation module, and determine the simulation resonant frequency of the resonant cavity based on the output of the second simulation module.

[0213] The second adjusting module is configured to, in a case where a second difference between the simulation resonant frequency and the theoretical resonant frequency is greater than or equal to a preset resonant frequency, adjust the layout of the resonant cavity so that the second difference is less than the preset resonant frequency.

[0214] The drawing module 605 comprises:

[0215] The first drawing unit is configured to merge the adjusted layout of the bit capacitor and the adjusted layout of the resonant cavity by using the layout template.

[0216] In some alternative embodiments, the apparatus further comprises:

[0217] The third determining module is configured to determine the geometric parameters of the bit capacitor based on the layout of the bit capacitor, the geometric parameters comprising at least one of the single-arm length of the bit capacitor, the first single-arm width of the bit capacitor, the second single-arm width of the bit capacitor, the first parameter, and the area of the bit capacitor.

[0218] The fourth determining module is configured to determine an actual capacitance value of the bit capacitance based on the geometric parameter.

[0219] In some optional embodiments, the third determining module further includes:

[0220] The fifth determining unit is configured to determine coordinate information of a plurality of pixel points corresponding to an image of the layout of the bit capacitance.

[0221] The sixth determining unit is configured to determine the geometric parameter based on the coordinate information of the plurality of pixel points.

[0222] In some optional embodiments, the apparatus further includes:

[0223] The fifth determining module is configured to determine the length of the resonant cavity based on the layout of the resonant cavity.

[0224] The sixth determining module is configured to determine the actual resonant frequency of the resonant cavity based on the length of the resonant cavity.

[0225] In some optional embodiments, the fifth determining module further includes:

[0226] The seventh determining unit is configured to determine coordinate information of a plurality of pixel points corresponding to an image of the layout of the resonant cavity.

[0227] The eighth determining unit is configured to determine the length of the resonant cavity based on the coordinate information of the plurality of pixel points.

[0228] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be described here.

[0229] The quantum chip layout generation apparatus in the embodiment is presented in the form of a functional unit. The unit refers to an Application Specific Integrated Circuit (ASIC), a processor and a memory executing one or more software or fixed programs, and / or other devices that can provide the above functions.

[0230] The embodiment of the present application further provides an optimization method of a quantum chip layout generation apparatus, which can be used for a client. The client includes a first apparatus, and the first apparatus can be the quantum chip layout generation apparatus provided in any of the above-mentioned embodiments. The first apparatus is configured with a first version number. The first version number is the version number of the quantum chip layout generation apparatus currently configured by the client. For example, the version number can be 3.0.

[0231] For example, the client can be a computer, a computer terminal, or a mobile phone terminal.

[0232] Figure 7 This is a schematic flowchart illustrating an optimization method for a quantum chip layout generation apparatus according to an embodiment of the present invention. Figure 7 As shown, the method includes the following steps:

[0233] Step S701: Obtain the second version number configured in the second device.

[0234] The second device is a quantum chip layout generation device stored in the server, and the second version number is the version number of the quantum chip layout generation device currently stored in the server. For example, the version number could be 3.2. Exemplarily, the second device can be stored in the server in XML data exchange format.

[0235] For example, a client can obtain the version number configured in the second device from the server using the GetVer function command.

[0236] Step S702: If the second version number is greater than the first version number, obtain the second device.

[0237] For example, if the second version number is determined to be 3.2 and the first version number is determined to be 3.0, the client obtains the second device from the server.

[0238] Step S703: Update the first device based on the second device.

[0239] Specifically, after acquiring the second device, the first device is replaced by the second device, enabling designers to design the quantum chip layout using the latest version of the quantum chip layout generation device.

[0240] The optimization method for the quantum chip layout generation device provided in this embodiment obtains the second version number configured in the second device, and updates the first device based on the second device when the second version number is greater than the first version number. This enables real-time updates of the quantum chip layout generation device loaded on the client, improves the performance of the generation device, and facilitates rapid updates and maintenance of the generation device.

[0241] This embodiment also provides an optimization device for a quantum chip layout generation apparatus, which is used to implement... Figure 7 The embodiments and preferred embodiments shown have already been described and will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0242] This embodiment provides an optimized apparatus for generating quantum chip layouts, such as... Figure 8 As shown, the device includes:

[0243] The first acquisition module 801 is used to acquire the second version number configured in the second device, which is a quantum chip layout generation device stored in the server.

[0244] The second acquisition module 802 is used to acquire the second device when the second version number is greater than the first version number;

[0245] Update module 803 is used to update the first device based on the second device.

[0246] This invention also provides a computer device having the above-described features. Figure 6 The apparatus for generating the quantum chip layout shown or the above Figure 8 An optimized apparatus for generating the quantum chip layout shown.

[0247] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 910, memory 920, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take the 910 processor as an example.

[0248] The processor 910 may be a central processing unit, a network processor, or a combination thereof. The processor 910 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0249] The memory 920 stores instructions executable by at least one processor 910 to cause the at least one processor 910 to perform the method shown in the above embodiments.

[0250] The memory 920 can include a program storage area and a data storage area, where the program storage area can store an operating system, application programs required by at least one function, and the data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 920 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 920 can optionally include a memory disposed remotely from the processor 910, which can be connected to the computer device through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0251] The memory 920 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state disk; and the memory 920 can also include a combination of the above-mentioned kinds of memories.

[0252] The computer device further includes an input device 930 and an output device 940. The processor 910, the memory 920, the input device 930, and the output device 940 can be connected through a bus or other means, Figure 9 For example, by way of example, through a bus connection.

[0253] The input device 930 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like. The output device 940 can include a display device, an auxiliary lighting device (e.g., an LED), a tactile feedback device (e.g., a vibration motor), and the like. The above-mentioned display device includes, but is not limited to, a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0254] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer codes stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer codes, when the software or computer codes are accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0255] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A method for generating a quantum chip layout, characterized in that, The method includes: The length of a single arm of the bit capacitor is determined based on the theoretical capacitance value or the area of ​​the bit capacitor. Using the single-arm length and the first drawing template, the layout of the bit capacitor is generated, wherein the first drawing template is the drawing template of the bit capacitor; The length of the resonant cavity is determined based on the theoretical resonant frequency; Using the length of the resonant cavity and a second drawing template, a layout of the resonant cavity is generated, wherein the second drawing template is the drawing template for the resonant cavity; The layout of the bit capacitor and the layout of the resonant cavity are merged using a layout template to form a quantum chip layout. The layout template includes first position information and second position information. The first position information is the position information of the layout of the target device, and the second position information is the relative position information between the layout of the bit capacitor and the layout of the resonant cavity. The target device is either the bit capacitor or the resonant cavity. Based on the layout of the bit capacitor, the geometric parameters of the bit capacitor are determined. The geometric parameters include at least one of the following: the length of a single arm of the bit capacitor, the width of a first single arm of the bit capacitor, the width of a second single arm of the bit capacitor, a first parameter, and the area of ​​the bit capacitor. Based on the geometric parameters, the actual capacitance value of the bit capacitor is determined.

2. The method according to claim 1, characterized in that, Determining the single-arm length of the bit capacitor based on the theoretical capacitance value or the area of ​​the bit capacitor includes: The length of one arm of the bit capacitor is determined based on the width of the first single arm, the width of the second single arm, and the theoretical capacitance value; or, Based on the first parameter and the theoretical capacitance value, the length of a single arm of the bit capacitor is determined, where the first parameter is the ratio of the width of the first single arm to the width of the second single arm; or, The length of the single arm of the bit capacitor is determined based on the area and the width of the first single arm.

3. The method according to claim 2, characterized in that, Determining the single-arm length of the bit capacitor based on the first single-arm width, the second single-arm width, and the theoretical capacitance value includes: Based on the width of the first single arm, the width of the second single arm, and the theoretical capacitance value, the length of the single arm is determined by the following formula: in, The length of the single arm, The theoretical capacitance value is... The preset cavity frequency offset value, The dielectric constant of the substrate is . The width of the first single arm. This is the width of the second single arm.

4. The method according to claim 2, characterized in that, Determining the single-arm length of the bit capacitor based on the first parameter and the theoretical capacitance value includes: Based on the first parameter and the theoretical capacitance value, the length of the single arm is determined using the following formula: in, The length of the single arm, The theoretical capacitance value is... The preset cavity frequency offset value, The dielectric constant of the substrate is . This refers to the first parameter.

5. The method according to claim 2, characterized in that, Determining the single-arm length of the bit capacitor based on the area and the width of the first single arm includes: Based on the area of ​​the bit capacitor and the width of the first single arm, the length of the single arm is determined by the following formula: in, The length of the single arm, The area is... The width of the first single arm.

6. The method according to claim 1, characterized in that, The determination of the resonant cavity length based on the theoretical resonant frequency includes: The length of the resonant cavity is determined based on the theoretical resonant frequency, the microwave velocity in free space, and the dielectric constant of the substrate.

7. The method according to any one of claims 1 to 6, characterized in that, After generating the layout of the bit capacitor using the single-arm length and the first drawing template, the method further includes: The layout of the bit capacitor is input into the first simulation module, and the simulated capacitance value of the bit capacitor is determined based on the output of the first simulation module. If the first difference between the simulated capacitance value and the theoretical capacitance value is greater than or equal to a preset capacitance value, the layout of the bit capacitor is adjusted so that the first difference is less than the preset capacitance value. After generating the layout of the resonant cavity using the length of the resonant cavity and the second drawing template, the method further includes: The layout of the resonant cavity is input into the second simulation module, and the simulated resonant frequency of the resonant cavity is determined based on the output of the second simulation module. If the second difference between the simulated resonant frequency and the theoretical resonant frequency is greater than or equal to the preset resonant frequency, the layout of the resonant cavity is adjusted so that the second difference is less than the preset resonant frequency. The method of merging the layout of the bit capacitor and the layout of the resonant cavity using a layout template includes: The layout of the bit capacitor and the layout of the resonant cavity are merged and adjusted using the layout template.

8. The method according to any one of claims 1 to 6, characterized in that, The determination of the geometric parameters of the bit capacitor based on the layout includes: Determine the coordinate information of multiple pixels corresponding to the layout image of the bit capacitor; The geometric parameters are determined based on the coordinate information of the multiple pixels.

9. The method according to any one of claims 1 to 6, characterized in that, The method further includes: Based on the layout of the resonant cavity, the length of the resonant cavity is determined; The actual resonant frequency of the resonant cavity is determined based on its length.

10. The method according to claim 9, characterized in that, Determining the length of the resonant cavity based on its layout includes: Determine the coordinate information of multiple pixels corresponding to the layout of the resonant cavity; The length of the resonant cavity is determined based on the coordinate information of the multiple pixels.

11. A device for generating a quantum chip layout, characterized in that, The device includes: The first determining module is used to determine the length of a single arm of the bit capacitor based on the theoretical capacitance value or the area of ​​the bit capacitor. The first processing module is used to generate the layout of the bit capacitor using the single arm length and the first drawing template, wherein the first drawing template is the drawing template of the bit capacitor; The second determining module is used to determine the length of the resonant cavity based on the theoretical resonant frequency; The second processing module is used to generate a layout of the resonant cavity using the length of the resonant cavity and a second drawing template, wherein the second drawing template is a drawing template for the resonant cavity; A drawing module is used to merge the layout of the bit capacitor and the layout of the resonant cavity using a layout template to form a quantum chip layout. The layout template includes first position information and second position information. The first position information is the position information of the target device, and the second position information is the relative position information between the layout of the bit capacitor and the layout of the resonant cavity. The target device is the bit capacitor or the resonant cavity. The third determining module is used to determine the geometric parameters of the bit capacitor based on the layout of the bit capacitor. The geometric parameters include at least one of the following: the length of a single arm of the bit capacitor, the width of a first single arm of the bit capacitor, the width of a second single arm of the bit capacitor, a first parameter, and the area of ​​the bit capacitor. The fourth determining module is used to determine the actual capacitance value of the bit capacitor based on the geometric parameters.

12. An optimization method for a quantum chip layout generation device, characterized in that, Applied to a client, the client includes a first device, the first device being the quantum chip layout generation device of claim 11, the first device being configured with a first version number, and the method comprising: Obtain the second version number configured in the second device, which is a quantum chip layout generation device stored in the server; If the second version number is greater than the first version number, obtain the second device; The first device is updated based on the second device.

13. An optimization device for a quantum chip layout generation apparatus, characterized in that, Applied to a client, the client includes a first device, the first device being the quantum chip layout generation device of claim 11, the first device being configured with a first version number, and the optimization device including: The first acquisition module is used to acquire the second version number configured in the second device, which is a quantum chip layout generation device stored in the server; The second acquisition module is used to acquire the second device when the second version number is greater than the first version number; An update module is used to update the first device based on the second device.

14. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 10, or to perform the method of claim 12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 10, or to perform the method of claim 12.

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