PCB bare board defect detection method, device and equipment and storage medium

Abstract

The present application relates to the technical field of PCB defect detection, and discloses a PCB bare board defect detection method, device, equipment and storage medium, the method comprises the following steps: obtaining a PCB bare board picture to be detected; inputting the PCB bare board picture to be detected into a PCB bare board defect detection model for defect detection, and outputting a defect detection result, wherein the PCB bare board defect detection model is obtained based on a YOLOv5 algorithm model, a convolution block attention mechanism is added between each C3 module and CBS module, and the number of convolution modules and up-sampling layers is increased in the backbone layer to increase the preset scale prediction head in the prediction layer. Through the defect detection of the PCB bare board defect detection model with the convolution block attention mechanism and the preset scale prediction head, the problems of high cost and low efficiency of artificial detection, poor small defect detection effect of machine detection and easy to miss detection are solved, the small target detection capability is improved, and the detection precision is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCB defect detection, and in particular to a PCB bare board defect detection method, device, equipment and storage medium. BACKGROUND

[0002] PCB is the core component of electronic products, and the quality of PCB will directly affect the performance of electronic equipment, and its quality inspection is the key to meet the growing quality demand of electronic manufacturing industry. In the actual production process, due to the complexity of the process, the PCB surface defects, short circuit, open circuit, notch, burr, welding point, and missing welding, etc. Each process may be affected by artificial, environment and equipment, and defects such as excess copper. There are many defects in the production process of PCB, and many production links of PCB must increase quality inspection, therefore, PCB defect detection is an important link in the industrial production process, and efficient and rapid defect detection can reduce the production cost of manufacturers and improve the quality of PCB. At present, the traditional manual detection method is mainly used for PCB detection, and the traditional detection technology needs to be completed manually on the production line for PCB defect detection, and a magnifying glass or a microscope is needed to check various defects on the circuit board. This method has high labor cost and low efficiency, and the existing machine detection still has defects when directly applied to PCB detection, small defect detection effect is poor, and it is easy to miss detection, which cannot meet the requirements of PCB detection. SUMMARY

[0003] The main purpose of the present application is to provide a PCB bare board defect detection method, device, equipment and storage medium, which aims to solve the technical problems of high cost and low efficiency of manual detection in the prior art, poor small defect detection effect of machine detection, and easy to miss detection.

[0004] To achieve the above purpose, the present application provides a PCB bare board defect detection method, which comprises the following steps:

[0005] Obtain a PCB bare board picture to be detected;

[0006] Input the PCB bare board picture to be detected into a PCB bare board defect detection model for defect detection, and output the defect detection result of the PCB bare board picture to be detected, wherein the PCB bare board defect detection model is obtained by increasing a convolution block attention mechanism between each C3 module and CBS module in the neck layer of a YOLOv5 algorithm model, and increasing the number of convolution modules and up-sampling layers in the backbone layer of the YOLOv5 algorithm model, so as to increase the prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model, and the convolution block attention mechanism is used to enhance the mastering ability of the PCB bare board defect detection model to the key information in the PCB bare board feature map.

[0007] Optionally, the PCB bare board defect detection model comprises an input layer, a backbone layer, a neck layer, and a prediction layer, the PCB bare board picture to be detected is input into the PCB bare board defect detection model for defect detection, and a defect detection result of the PCB bare board picture to be detected is output, comprising:

[0008] The PCB bare board picture to be detected is input into the input layer for preprocessing to obtain a preprocessed PCB bare board picture to be detected, wherein the preprocessing comprises at least one of data enhancement, adaptive anchor frame calculation, and adaptive picture scaling, and the data enhancement comprises at least one of random cropping, random scaling, and random arrangement;

[0009] The preprocessed PCB bare board picture to be detected is input into the backbone layer for feature extraction to obtain a PCB bare board feature map to be fused;

[0010] The PCB bare board feature map to be fused is input into the neck layer for feature fusion to obtain a PCB bare board feature map to be detected;

[0011] The PCB bare board feature map to be detected is input into the prediction layer for detection to obtain the defect detection result of the PCB bare board picture to be detected.

[0012] Optionally, the preprocessed PCB bare board picture to be detected is input into the backbone layer for feature extraction to obtain a PCB bare board feature map to be fused, comprising:

[0013] The preprocessed PCB bare board picture to be detected is input into the convolution module of the backbone layer for feature extraction to obtain an initial PCB bare board feature map;

[0014] The initial PCB bare board feature map is down-sampled to obtain PCB bare board feature maps of different sizes, wherein the PCB bare board feature maps of different sizes comprise at least a first PCB bare board feature map, a second PCB bare board feature map, a third PCB bare board feature map, and a fourth PCB bare board feature map, the size of the first PCB bare board feature map is twice the size of the second PCB bare board feature map, the size of the second PCB bare board feature map is twice the size of the third PCB bare board feature map, and the size of the third PCB bare board feature map is twice the size of the fourth PCB bare board feature map;

[0015] The first PCB bare board feature map, the second PCB bare board feature map, the third PCB bare board feature map, and the fourth PCB bare board feature map are taken as the PCB bare board feature map to be fused.

[0016] Optionally, the PCB bare board feature map to be fused is input into the neck layer for feature fusion to obtain a PCB bare board feature map to be detected, comprising:

[0017] The fourth PCB bare board feature map is fused and spliced with the third PCB bare board feature map after being twice up-sampled to obtain a first fused PCB bare board feature map;

[0018] The first fused PCB bare board feature map is fused and spliced with the second PCB bare board feature map after being twice up-sampled to obtain a second fused PCB bare board feature map;

[0019] The second fused PCB bare board feature map is fused and spliced with the first PCB bare board feature map after being twice up-sampled to obtain a third fused PCB bare board feature map;

[0020] The third fused PCB bare board feature map is fused and spliced with the first PCB bare board feature map after being twice up-sampled to obtain a fourth fused PCB bare board feature map;

[0021] The fourth fused PCB bare board feature map is twice down-sampled after being adaptively refined in feature by a convolution block attention mechanism, and the fourth fused PCB bare board feature map after being twice down-sampled is fused and spliced with the third fused PCB bare board feature map to obtain a first to-be-detected PCB bare board feature map;

[0022] The first to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined in feature by a convolution block attention mechanism, and the first to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the second fused PCB bare board feature map to obtain a second to-be-detected PCB bare board feature map;

[0023] The second to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined in feature by a convolution block attention mechanism, and the second to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the first fused PCB bare board feature map to obtain a third to-be-detected PCB bare board feature map;

[0024] The third to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined in feature by a convolution block attention mechanism, and the third to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the fourth PCB bare board feature map to obtain a fourth to-be-detected PCB bare board feature map;

[0025] The first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map are taken as to-be-detected PCB bare board feature maps.

[0026] Optionally, the detection layer includes a first prediction head, a second prediction head, a third prediction head, and a fourth prediction head, and the inputting the to-be-detected PCB bare board feature map into the prediction layer for detection to obtain a defect detection result of the to-be-detected PCB bare board picture includes:

[0027] The first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map are input into the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head respectively, wherein the scales of the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map correspond to the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head respectively.

[0028] Optionally, before the inputting the to-be-detected PCB bare board picture into the PCB bare board defect detection model for defect detection and outputting a defect detection result of the to-be-detected PCB bare board picture, the method further includes:

[0029] An initial PCB bare board defect detection model is constructed based on a YOLOv5 algorithm model, wherein the initial PCB bare board defect detection model includes an input layer, a backbone layer, a neck layer, and a prediction layer.

[0030] A convolution block attention mechanism is added between each C3 module and CBS module in the neck layer of the initial PCB bare board defect detection model, and the number of convolution layers and up-sampling layers is increased in the backbone layer of the initial PCB bare board defect detection model, so that a preset scale prediction head is added in the prediction layer to obtain an improved PCB bare board defect detection model, wherein the preset scale prediction head is the fourth prediction head.

[0031] A PCB bare board defect dataset is obtained, and the PCB bare board defect dataset is divided into a training set and a test set according to a preset proportion.

[0032] The improved PCB bare board defect detection model is trained according to the training set to obtain a trained PCB bare board defect detection model.

[0033] The trained PCB bare board defect detection model is tested according to the test set and a confidence is calculated.

[0034] The confidence is compared with a confidence threshold.

[0035] If the confidence is greater than or equal to the confidence threshold, the training is stopped, and the trained PCB bare board defect detection model with the current confidence is taken as the PCB bare board defect detection model.

[0036] If the confidence is less than a confidence threshold, return and continue to perform the step of training the improved PCB bare board defect detection model according to the training set to obtain a trained PCB bare board defect detection model until the confidence reaches the confidence threshold.

[0037] Optionally, the obtaining of the PCB bare board defect data set comprises:

[0038] Obtaining a plurality of PCB bare board defect pictures;

[0039] Performing an expansion operation on the plurality of PCB bare board defect pictures to obtain expanded PCB bare board defect pictures, wherein the expansion operation comprises at least one of random rotation, horizontal translation, vertical translation, scaling, horizontal inversion, and random enhancement of picture brightness;

[0040] Taking the expanded PCB bare board defect pictures as the PCB bare board defect data set.

[0041] In addition, to achieve the above-mentioned purpose, the present application further proposes a PCB bare board defect detection device, which comprises:

[0042] An obtaining module is configured to obtain a to-be-detected PCB bare board picture;

[0043] A detection module is configured to input the to-be-detected PCB bare board picture into a PCB bare board defect detection model for defect detection and output a defect detection result of the to-be-detected PCB bare board picture, wherein the PCB bare board defect detection model is obtained based on a YOLOv5 algorithm model, a convolution block attention mechanism is added between each C3 module and CBS module in the neck layer of the YOLOv5 algorithm model, and the number of convolution modules and up-sampling layers is increased in the backbone layer of the YOLOv5 algorithm model so as to increase a prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model, and the convolution block attention mechanism is used to enhance the mastering ability of the PCB bare board defect detection model to key information in a PCB bare board feature map.

[0044] In addition, to achieve the above-mentioned purpose, the present application further proposes a PCB bare board defect detection device, which comprises: a memory, a processor, and a PCB bare board defect detection program stored on the memory and executable on the processor, wherein the PCB bare board defect detection program is configured to implement the steps of the PCB bare board defect detection method as described above.

[0045] In addition, in order to achieve the above-mentioned purpose, the application further provides a storage medium, wherein the storage medium stores a PCB bare board defect detection program, and the PCB bare board defect detection program realizes the steps of the PCB bare board defect detection method when executed by a processor.

[0046] The application obtains a to-be-detected PCB bare board picture, inputs the to-be-detected PCB bare board picture into a PCB bare board defect detection model for defect detection, and outputs a defect detection result, wherein the PCB bare board defect detection model is obtained by increasing a convolution block attention mechanism between each C3 module and CBS module and increasing the number of convolution layers and up-sampling layers in a backbone layer based on a YOLOv5 algorithm model to increase a preset scale prediction head in a prediction layer. In this way, the PCB bare board defect detection model with the convolution block attention mechanism and the preset scale prediction head is used for defect detection, which solves the problems of high cost and low efficiency of manual detection, poor detection effect of small defects by machines, and easy omission, improves the small target detection capability, and has high detection precision. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 is a structural schematic diagram of a PCB bare board defect detection device related to a hardware running environment of an embodiment scheme of the application;

[0048] Figure 2 is a flowchart of a first embodiment of a PCB bare board defect detection method of the application;

[0049] Figure 3 is a flowchart of a second embodiment of a PCB bare board defect detection method of the application;

[0050] Figure 4 is a feature map diagram in the second embodiment of the PCB bare board defect detection method of the application;

[0051] Figure 5 is a PCB bare board defect detection model in the second embodiment of the PCB bare board defect detection method of the application;

[0052] Figure 6 is a structural block diagram of a first embodiment of a PCB bare board defect detection device of the application.

[0053] The implementation, functional features and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0054] It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0055] Reference Figure 1 , Figure 1A PCB bare board defect detection equipment structural schematic diagram of a hardware running environment involved in an embodiment of the present application is shown.

[0056] As shown in Figure 1 , the PCB bare board defect detection equipment can include a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to realize the connection and communication between the components. The user interface 1003 can include a display, an input unit such as a keyboard, and can also include a standard wired interface and a wireless interface. The network interface 1004 can optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wi-Fi) interface). The memory 1005 can be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk memory. The memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0057] Those skilled in the art can understand that Figure 1 the structure shown in the above description does not constitute a limitation on the PCB bare board defect detection equipment, and can include more or fewer components than the diagram, or combine certain components, or different component arrangements.

[0058] As shown in Figure 1 , the memory 1005 as a storage medium can include an operating system, a network communication module, a user interface module, and a PCB bare board defect detection program.

[0059] In the PCB bare board defect detection equipment shown in Figure 1 , the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the PCB bare board defect detection equipment of the present application can be arranged in the PCB bare board defect detection equipment, and the PCB bare board defect detection equipment calls the PCB bare board defect detection program stored in the memory 1005 through the processor 1001, and executes the PCB bare board defect detection method provided by the embodiment of the present application.

[0060] The present application provides a PCB bare board defect detection method, which is described with reference to Figure 2 , Figure 2 A flowchart of a first embodiment of the PCB bare board defect detection method of the present application is shown.

[0061] In this embodiment, the PCB bare board defect detection method comprises the following steps:

[0062] Step S10: Obtain a PCB bare board picture to be detected.

[0063] It should be noted that the execution subject of the present embodiment is a PCB bare board defect detection device, and can also be other devices that can achieve the same or similar functions. The present embodiment takes a mitosis cell detection device as an example for illustration.

[0064] Step S20: input the PCB bare board picture to be detected into a PCB bare board defect detection model for defect detection, and output a defect detection result of the PCB bare board picture to be detected, wherein the PCB bare board defect detection model is obtained based on a YOLOv5 algorithm model, by adding a convolution block attention mechanism between each C3 module and CBS module in the neck layer of the YOLOv5 algorithm model, and by increasing the number of convolution modules and up-sampling layers in the backbone layer of the YOLOv5 algorithm model to increase the prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model, the convolution block attention mechanism is used to enhance the mastery ability of the PCB bare board defect detection model to the key information in the PCB bare board feature map.

[0065] It should be noted that the PCB bare board defect detection model is obtained based on a YOLOv5 algorithm model, by adding a convolution block attention mechanism between each C3 module and CBS module in the neck layer of the YOLOv5 algorithm model, and by increasing the number of convolution modules and up-sampling layers in the backbone layer of the YOLOv5 algorithm model to increase the prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model, the PCB bare board defect detection model comprises an input layer, a backbone layer, a neck layer, and a prediction layer, the neck layer comprises an SPP (Spatial Pyramid Pooling) structure, an FPN (Feature Pyramid Network) structure, and a P-Net (Path Aggregation Network) structure, the FPN (Feature Pyramid Network) structure and the P-Net (Path Aggregation Network) structure both comprise C3 modules and CBS modules. The convolution block attention mechanism (CBAM) between each C3 module and CBS module is used to improve the attention of the network model to small targets, and the number of convolution layers and up-sampling layers is increased to extract multi-scale feature maps. The C3 module is a residual structure that can realize cross-scale connection and enable the model to learn more features. The neck layer further comprises a sampling layer Unsample and a concatenation layer Concat. The sampling layer Unsample does not change the channel number of the feature map, but increases the width and height of the feature map. The concatenation layer Concat does not change the size of the feature map, but increases the channel number of the feature map.

[0066] It can be understood that the defect detection result of the output PCB bare board picture to be detected includes marking the position of the PCB bare board defect by a marking box and marking the category of the PCB bare board defect by a label, wherein the category of the PCB bare board defect includes mouse bite, hole, open circuit, short circuit, burr, excess copper, etc., and the embodiment is not specifically limited thereto.

[0067] In the embodiment, the PCB bare board defect detection model is obtained based on a YOLOv5 algorithm model, a convolution block attention mechanism is added between each C3 module and CBS module, and the number of convolution layers and up-sampling layers is increased in the backbone layer to increase the preset scale of the prediction head in the prediction layer. Through the above manner, the PCB bare board defect detection model with the convolution block attention mechanism and the preset scale of the prediction head is used for defect detection, which solves the problems of high cost and low efficiency of artificial detection, poor detection effect of small defects by machine detection and easy to miss detection, improves the small target detection capability, and has high detection precision.

[0068] Reference Figure 3 , Figure 3 The flowchart of the second embodiment of the PCB bare board defect detection method is shown.

[0069] Based on the above first embodiment, in the step S20 of the PCB bare board defect detection method, the following steps are included.

[0070] Step S201: inputting the PCB bare board picture to be detected into the input layer for preprocessing to obtain a preprocessed PCB bare board picture to be detected, wherein the preprocessing includes at least one of data enhancement, adaptive anchor frame calculation and adaptive picture scaling, and the data enhancement includes at least one of random cropping, random scaling and random arrangement.

[0071] It should be noted that the data enhancement, i.e. mosaic data enhancement, includes random cropping, random scaling and random arrangement, i.e. the input PCB bare board picture to be detected is randomly cropped into four pictures, and after random scaling, only a part of the area of each picture and the corresponding detection frame information are taken, which are randomly spliced and combined into a new picture, thereby enriching the information of the detected object.

[0072] It can be understood that the adaptive anchor frame calculation is to sample a large number of regions in the input PCB bare board picture to be detected, to judge whether the regions contain the target of interest, and to adjust the region boundary to more accurately predict the real boundary box of the target. Different models may use different region sampling methods. Anchor frame: a plurality of boundary boxes with different scaling ratios and width-height ratios are generated with each pixel as the center.

[0073] It is worth noting that adaptive picture scaling, that is, uniformly scaling the size of the input to-be-detected PCB bare board picture to the same size, the shrinkage ratio of the length and width should adopt the same ratio. The picture input during model training does not undergo adaptive picture scaling, but adaptive picture scaling is used during detection. The detection effect after adaptive picture is better.

[0074] Step S202: inputting the pre-processed to-be-detected PCB bare board picture to the backbone layer for feature extraction to obtain a to-be-fused PCB bare board feature map.

[0075] It is worth noting that the pre-processed to-be-detected PCB bare board picture is subjected to convolution by the convolution layer and then down-sampling to obtain PCB bare board feature maps of different sizes, which are to-be-fused PCB bare board feature maps.

[0076] Further, in order to perform feature extraction, the step S202 includes: performing feature extraction on the pre-processed to-be-detected PCB bare board picture by the convolution module of the backbone layer to obtain an initial PCB bare board feature map; down-sampling the initial PCB bare board feature map to obtain PCB bare board feature maps of different sizes, wherein the PCB bare board feature maps of different sizes at least include a first PCB bare board feature map, a second PCB bare board feature map, a third PCB bare board feature map and a fourth PCB bare board feature map, the size of the first PCB bare board feature map is 2 times the size of the second PCB bare board feature map, the size of the second PCB bare board feature map is 2 times the size of the third PCB bare board feature map, and the size of the third PCB bare board feature map is 2 times the size of the fourth PCB bare board feature map; and taking the first PCB bare board feature map, the second PCB bare board feature map, the third PCB bare board feature map and the fourth PCB bare board feature map as to-be-fused PCB bare board feature maps.

[0077] It is worth noting that the backbone layer in the PCB bare board defect detection model includes a Focus layer, a convolution module (CBS) and a C3 module. The Focus layer converts the width and height information of the to-be-detected PCB bare board picture into channel information. Specifically, in the to-be-detected PCB bare board picture, one pixel is obtained every other pixel, at which time four independent feature layers are obtained, and then the feature layers are stacked to reduce the calculation amount of the model and improve the detection speed of the model. The convolution module, that is, the standard convolution block CBS, is a basic module in the convolutional neural network, which is composed of a convolution layer (Conv), a batch normalization BatchNormalization layer (BN) and a SiLU activation function. The C3 module is a residual structure that can realize cross-scale connection and enable the model to learn more features.

[0078] In a specific implementation, for example, the input to-be-detected PCB bare board picture size is 640x640, after the slicing operation by the Focus layer and the convolution by the convolution module, the initial PCB bare board feature map with a size of 320x320 is obtained through the C3 module, and after the initial PCB bare board feature map with a size of 320x320 is down-sampled, the first PCB bare board feature map with a size of 160x160, the second PCB bare board feature map with a size of 80x80, the third PCB bare board feature map with a size of 40x40 and the fourth PCB bare board feature map with a size of 20x20 are obtained.

[0079] Step S203: inputting the to-be-fused PCB bare board feature map to the neck layer to perform feature fusion, and obtaining a to-be-detected PCB bare board feature map.

[0080] It should be noted that the SPP (Spatial Pyramid Pooling) structure of the neck layer performs maximum pooling operation on the to-be-fused PCB bare board feature map in four scales, and then the to-be-fused PCB bare board feature map is up-sampled and fused by the FPN (Feature Pyramid Network) structure, and then down-sampled and fused by the P-Net (Path Aggregation Network) structure, to obtain the to-be-detected PCB bare board feature map.

[0081] Further, in order to perform feature fusion, the step S203 includes: fusing and splicing the fourth PCB bare board feature map after two times of up-sampling with the third PCB bare board feature map, to obtain a first fused PCB bare board feature map; fusing and splicing the first fused PCB bare board feature map after two times of up-sampling with the second PCB bare board feature map, to obtain a second fused PCB bare board feature map;

[0082] The second fusion PCB bare board feature map is fused and spliced with the first PCB bare board feature map after being twice up-sampled to obtain a third fusion PCB bare board feature map; the third fusion PCB bare board feature map is fused and spliced with the first PCB bare board feature map after being twice up-sampled to obtain a fourth fusion PCB bare board feature map; the fourth fusion PCB bare board feature map is twice down-sampled after being adaptively refined by the convolution block attention mechanism, and the fourth fusion PCB bare board feature map after being twice down-sampled is fused and spliced with the third fusion PCB bare board feature map to obtain a first to-be-detected PCB bare board feature map; the first to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined by the convolution block attention mechanism, and the first to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the second fusion PCB bare board feature map to obtain a second to-be-detected PCB bare board feature map; the second to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined by the convolution block attention mechanism, and the second to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the first fusion PCB bare board feature map to obtain a third to-be-detected PCB bare board feature map; the third to-be-detected PCB bare board feature map is twice down-sampled after being adaptively refined by the convolution block attention mechanism, and the third to-be-detected PCB bare board feature map after being twice down-sampled is fused and spliced with the fourth PCB bare board feature map to obtain a fourth to-be-detected PCB bare board feature map; the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map and the fourth to-be-detected PCB bare board feature map are taken as to-be-detected PCB bare board feature maps.

[0083] It should be noted that the SPP (spatial pyramid pooling) structure of the neck layer performs maximum pooling operations on the to-be-fused PCB bare board feature maps in four scales, inputs the fourth PCB bare board feature map with a size of 20x20 to the FPN (feature pyramid network) structure, fuses and splices the third PCB bare board feature map with a size of 40x40 after being twice up-sampled by the sampling layer, and obtains the first fusion PCB bare board feature map with a size of 40x40 through the C3 module. Through repeated operations, the second fusion PCB bare board feature map with a size of 80x80, the third fusion PCB bare board feature map with a size of 160x160 and the fourth fusion PCB bare board feature map with a size of 320x320 are obtained. The scales of the two shallow feature maps of 160x160 and 320x320 are introduced to realize multi-scale detection and improve the fusion of deep semantic and low-level semantic information.

[0084] It can be understood that the fourth fused PCB bare board feature map with a size of 320x320 is input into a P-Net (path aggregation network) structure, and after adaptive refinement of features by a convolution block attention mechanism and two times of down-sampling, the fourth fused PCB bare board feature map is fused and spliced with the third fused PCB bare board feature map with a size of 160x160, and a first to-be-detected PCB bare board feature map with a size of 160x160 is obtained through a C3 module, a prediction head Head4 is added to a corresponding prediction layer, and the operation is repeated to obtain a second to-be-detected PCB bare board feature map with a size of 80x80, a third to-be-detected PCB bare board feature map with a size of 40x40, and a fourth to-be-detected PCB bare board feature map with a size of 20x20, as shown in Figure 4 . Figure 4 is a feature map diagram in the PCB bare board defect detection method.

[0085] Step S204: inputting the to-be-detected PCB bare board feature map into the prediction layer for detection to obtain a defect detection result of the to-be-detected PCB bare board picture.

[0086] Further, the detection layer includes a first prediction head, a second prediction head, a third prediction head, and a fourth prediction head, and the step S204 includes: inputting the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map into the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head respectively, wherein the scales of the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map correspond to the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head respectively.

[0087] It should be noted that the scale of the first to-be-detected PCB bare board feature map is consistent with the scale output by the first prediction head, both being 160x160, the scale of the second to-be-detected PCB bare board feature map is consistent with the scale output by the second prediction head, both being 80x80, the scale of the third to-be-detected PCB bare board feature map is consistent with the scale output by the third prediction head, both being 40x40, and the scale of the fourth to-be-detected PCB bare board feature map is consistent with the scale output by the fourth prediction head, both being 20x20.

[0088] As shown in Figure 5 , Figure 5As shown in FIG. 1, the PCB bare board defect detection model structure in the PCB bare board defect detection method of the embodiment includes a Focus layer, a convolution module (CBS), a C3 module, a CBS module, a sampling layer Unsample, and a splicing layer Concat. There is a CBAM attention mechanism (Convolution Block Attention Mechanism) between the C3 module and the CBS module. An input is a picture of a PCB bare board to be detected. After slicing operation by the Focus layer, convolution by the convolution module, and output of a feature map after the C3 module, the feature map is sequentially down-sampled, up-sampled, and fused and spliced. After down-sampling and fusion splicing, the feature map to be detected with scales of 160x160x255, 80x80x255, 40x40x255, and 20x20x255 is output.

[0089] Further, before the step of inputting the picture of the PCB bare board to be detected into the PCB bare board defect detection model for defect detection and outputting a defect detection result of the picture of the PCB bare board to be detected, the method further includes the following steps: constructing an initial PCB bare board defect detection model based on a YOLOv5 algorithm model, wherein the initial PCB bare board defect detection model includes an input layer, a backbone layer, a neck layer, and a prediction layer; adding a convolution block attention mechanism between each C3 module and CBS module in the neck layer of the initial PCB bare board defect detection model and increasing the number of convolution layers and up-sampling layers in the backbone layer of the initial PCB bare board defect detection model to increase a preset scale prediction head in the prediction layer, thereby obtaining an improved PCB bare board defect detection model, wherein the preset scale prediction head is the fourth prediction head; obtaining a PCB bare board defect data set and dividing the PCB bare board defect data set into a training set and a test set according to a preset proportion; training the improved PCB bare board defect detection model according to the training set to obtain a trained PCB bare board defect detection model; testing the trained PCB bare board defect detection model according to the test set and calculating a confidence; comparing the confidence with a confidence threshold; if the confidence is greater than or equal to the confidence threshold, stopping the training and taking the trained PCB bare board defect detection model with the current confidence as the PCB bare board defect detection model; and if the confidence is less than the confidence threshold, returning to and continuing to perform the step of training the improved PCB bare board defect detection model according to the training set to obtain the trained PCB bare board defect detection model until the confidence reaches the confidence threshold.

[0090] It should be noted that the convolution block attention mechanism, that is, the CBAM attention mechanism, is added after each C3 module and before the CBS module in the neck layer, that is, the attention mechanism is added between two times of feature fusion, so as to improve the attention of the network model to small targets, and after the CBAM attention mechanism is added, the feature operation of the feature map is strengthened before feature fusion, so that the entire network model can improve the anti-interference ability of useless information, pay attention to important features, and perform feature fusion operation on the important features. In this way, the feature map after fusion can contain more useful information, improve the precision of small target detection, and reduce the calculation amount of the model and improve the calculation speed of the model.

[0091] It can be understood that the confidence represents the accuracy of the model prediction, for example, the accuracy of the PCB bare board defect detection model after training improvement is 90%.

[0092] Further, the plurality of PCB bare board defect pictures are obtained, and an expansion operation is performed on the plurality of PCB bare board defect pictures to obtain expanded PCB bare board defect pictures, wherein the expansion operation includes at least one of random rotation, horizontal translation, vertical translation, scaling, horizontal inversion, and random enhancement of picture brightness; and the expanded PCB bare board defect pictures are used as a PCB bare board defect dataset.

[0093] It should be noted that the plurality of PCB bare board defect pictures are obtained by photographing the PCB bare board with defects, and the photographed pictures are all regular rectangles with small inclination angles.

[0094] It can be understood that expanding the PCB bare board defect pictures can enrich the sample data of the dataset and improve the effect of model training.

[0095] In this embodiment, the to-be-detected PCB bare board picture is input to the input layer for preprocessing to obtain a preprocessed to-be-detected PCB bare board picture, wherein the preprocessing includes at least one of data enhancement, adaptive anchor frame calculation, and adaptive picture scaling, and the data enhancement includes at least one of random cropping, random scaling, and random arrangement; the preprocessed to-be-detected PCB bare board picture is input to the backbone layer for feature extraction to obtain a to-be-fused PCB bare board feature map; the to-be-fused PCB bare board feature map is input to the neck layer for feature fusion to obtain a to-be-detected PCB bare board feature map; and the to-be-detected PCB bare board feature map is input to the prediction layer for detection to obtain a defect detection result of the to-be-detected PCB bare board picture. In this way, the to-be-detected PCB bare board picture is preprocessed to enhance the features, and then feature extraction and fusion are performed, so as to improve the small target detection capability and the accuracy of model prediction.

[0096] Reference Figure 6 , Figure 6 is a structural block diagram of a first embodiment of the PCB bare board defect detection device of the present application.

[0097] As shown in Figure 6 , the PCB bare board defect detection device provided by the embodiment of the present application comprises:

[0098] The acquisition module 10 is configured to acquire a picture of a PCB bare board to be detected.

[0099] The detection module 20 is configured to input the picture of the PCB bare board to be detected into a PCB bare board defect detection model to perform defect detection, and output a defect detection result of the picture of the PCB bare board to be detected, wherein the PCB bare board defect detection model is obtained by increasing a convolution block attention mechanism between each C3 module and a CBS module in a neck layer of a YOLOv5 algorithm model and increasing the number of convolution modules and up-sampling layers in a backbone layer of the YOLOv5 algorithm model so as to increase a preset scale of a prediction head in a prediction layer of the YOLOv5 algorithm model, and the convolution block attention mechanism is configured to enhance the mastering ability of the PCB bare board defect detection model to key information in a PCB bare board feature map.

[0100] The embodiment acquires a picture of a PCB bare board to be detected, inputs the picture of the PCB bare board to be detected into a PCB bare board defect detection model to perform defect detection, and outputs a defect detection result, wherein the PCB bare board defect detection model is obtained by increasing a convolution block attention mechanism between each C3 module and a CBS module in a YOLOv5 algorithm model and increasing the number of convolution layers and up-sampling layers in a backbone layer so as to increase a preset scale of a prediction head in a prediction layer. Through the above manner, the defect detection is performed by the PCB bare board defect detection model with the increased convolution block attention mechanism and the preset scale of the prediction head, thereby solving the problems of high cost and low efficiency of artificial detection, poor detection effect of small defects by machine detection, and easy to miss detection, improving the small target detection capability and the detection precision.

[0101] In an embodiment, the PCB bare board defect detection model comprises an input layer, a backbone layer, a neck layer, and a prediction layer, and the detection module 20 is further configured to input the to-be-detected PCB bare board picture into the input layer for preprocessing to obtain a preprocessed to-be-detected PCB bare board picture, wherein the preprocessing comprises at least one of data enhancement, adaptive anchor frame calculation, and adaptive picture scaling, and the data enhancement comprises at least one of random cropping, random scaling, and random arrangement; input the preprocessed to-be-detected PCB bare board picture into the backbone layer for feature extraction to obtain to-be-fused PCB bare board feature maps; input the to-be-fused PCB bare board feature maps into the neck layer for feature fusion to obtain to-be-detected PCB bare board feature maps; and input the to-be-detected PCB bare board feature maps into the prediction layer for detection to obtain a defect detection result of the to-be-detected PCB bare board picture.

[0102] In an embodiment, the detection module 20 is further configured to perform feature extraction on the preprocessed to-be-detected PCB bare board picture by a convolution module of the backbone layer to obtain initial PCB bare board feature maps; perform down-sampling on the initial PCB bare board feature maps to obtain PCB bare board feature maps of different sizes, wherein the PCB bare board feature maps of different sizes comprise at least a first PCB bare board feature map, a second PCB bare board feature map, a third PCB bare board feature map, and a fourth PCB bare board feature map, the size of the first PCB bare board feature map is 2 times the size of the second PCB bare board feature map, the size of the second PCB bare board feature map is 2 times the size of the third PCB bare board feature map, and the size of the third PCB bare board feature map is 2 times the size of the fourth PCB bare board feature map; and take the first PCB bare board feature map, the second PCB bare board feature map, the third PCB bare board feature map, and the fourth PCB bare board feature map as to-be-fused PCB bare board feature maps.

[0103] In an embodiment, the detection module 20 is further configured to perform upsampling on the fourth PCB bare board feature map by a factor of two, and fuse the upsampling fourth PCB bare board feature map with the third PCB bare board feature map to obtain a first fused PCB bare board feature map; perform upsampling on the first fused PCB bare board feature map by a factor of two, and fuse the upsampling first fused PCB bare board feature map with the second PCB bare board feature map to obtain a second fused PCB bare board feature map; perform upsampling on the second fused PCB bare board feature map by a factor of two, and fuse the upsampling second fused PCB bare board feature map with the first PCB bare board feature map to obtain a third fused PCB bare board feature map; perform upsampling on the third fused PCB bare board feature map by a factor of two, and fuse the upsampling third fused PCB bare board feature map with the first PCB bare board feature map to obtain a fourth fused PCB bare board feature map; perform adaptive feature refinement on the fourth fused PCB bare board feature map by a convolution block attention mechanism, and perform downsampling on the fourth fused PCB bare board feature map by a factor of two; fuse the downsampling fourth fused PCB bare board feature map with the third fused PCB bare board feature map to obtain a first to-be-detected PCB bare board feature map; perform adaptive feature refinement on the first to-be-detected PCB bare board feature map by a convolution block attention mechanism, and perform downsampling on the first to-be-detected PCB bare board feature map by a factor of two; fuse the downsampling first to-be-detected PCB bare board feature map with the second fused PCB bare board feature map to obtain a second to-be-detected PCB bare board feature map; perform adaptive feature refinement on the second to-be-detected PCB bare board feature map by a convolution block attention mechanism, and perform downsampling on the second to-be-detected PCB bare board feature map by a factor of two; fuse the downsampling second to-be-detected PCB bare board feature map with the first fused PCB bare board feature map to obtain a third to-be-detected PCB bare board feature map; perform adaptive feature refinement on the third to-be-detected PCB bare board feature map by a convolution block attention mechanism, and perform downsampling on the third to-be-detected PCB bare board feature map by a factor of two; fuse the downsampling third to-be-detected PCB bare board feature map with the fourth PCB bare board feature map to obtain a fourth to-be-detected PCB bare board feature map; and use the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map as the to-be-detected PCB bare board feature map.

[0104] In an embodiment, the detection layer includes a first prediction head, a second prediction head, a third prediction head, and a fourth prediction head, and the detection module 20 is further configured to input the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map into the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head, respectively, wherein the first to-be-detected PCB bare board feature map, the second to-be-detected PCB bare board feature map, the third to-be-detected PCB bare board feature map, and the fourth to-be-detected PCB bare board feature map have a one-to-one correspondence with the first prediction head, the second prediction head, the third prediction head, and the fourth prediction head, respectively.

[0105] In an embodiment, the detection module 20 is further configured to construct an initial PCB bare board defect detection model based on a YOLOv5 algorithm model, wherein the initial PCB bare board defect detection model comprises an input layer, a backbone layer, a neck layer, and a prediction layer; a convolution block attention mechanism is added between each C3 module and CBS module in the neck layer of the initial PCB bare board defect detection model, and the number of convolution layers and up-sampling layers is increased in the backbone layer of the initial PCB bare board defect detection model, so that a preset scale prediction head is added in the prediction layer to obtain an improved PCB bare board defect detection model, wherein the preset scale prediction head is the fourth prediction head; a PCB bare board defect dataset is obtained, and the PCB bare board defect dataset is divided into a training set and a test set according to a preset proportion; the improved PCB bare board defect detection model is trained based on the training set to obtain a trained PCB bare board defect detection model; the trained PCB bare board defect detection model is tested based on the test set, and a confidence is calculated; the confidence is compared with a confidence threshold; if the confidence is greater than or equal to the confidence threshold, the training is stopped, and the trained PCB bare board defect detection model with the current confidence is taken as the PCB bare board defect detection model; if the confidence is less than the confidence threshold, the step of training the improved PCB bare board defect detection model based on the training set to obtain the trained PCB bare board defect detection model is returned and continuously executed until the confidence reaches the confidence threshold.

[0106] In an embodiment, the detection module 20 is further configured to obtain a plurality of PCB bare board defect pictures; and perform an expansion operation on the plurality of PCB bare board defect pictures to obtain expanded PCB bare board defect pictures, wherein the expansion operation comprises at least one of random rotation, horizontal translation, vertical translation, scaling, horizontal inversion, and random enhancement of picture brightness; and the expanded PCB bare board defect pictures are taken as a PCB bare board defect dataset.

[0107] In addition, to achieve the above-mentioned purposes, the present application further provides a PCB bare board defect detection device, which comprises a memory, a processor, and a PCB bare board defect detection program stored in the memory and capable of running on the processor, wherein the PCB bare board defect detection program is configured to implement the steps of the PCB bare board defect detection method as described above.

[0108] Since the PCB bare board defect detection device adopts all the technical solutions of the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0109] In addition, the embodiment of the present application further provides a storage medium, wherein the storage medium stores a PCB bare board defect detection program, and the PCB bare board defect detection program is executed by a processor to realize the steps of the PCB bare board defect detection method.

[0110] Since the storage medium adopts all the technical solutions of the above embodiments, it has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0111] It should be understood that the above is only for illustration, and does not constitute any limitation on the technical solutions of the present application. In specific applications, those skilled in the art can set it up according to the needs, and the present application does not limit this.

[0112] It should be noted that the above-described workflow is only illustrative and does not limit the scope of protection of the present application. In actual application, those skilled in the art can select part or all of them to achieve the purpose of the embodiment scheme according to actual needs, which is not limited here.

[0113] In addition, technical details not described in detail in the embodiment can be referred to the PCB bare board defect detection method provided by any embodiment of the present application, which will not be repeated here.

[0114] In addition, it should be noted that in this paper, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or system. Without more limitations, the element defined by the sentence "includes a" does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0115] The above embodiment number of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0116] Those skilled in the art can clearly understand the above-mentioned embodiment method can be realized by means of software and the necessary general hardware platform, of course, can also be through hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application essentially or say the part of the prior art contribution can be embodied in the form of software products, the computer software product is stored in a storage medium (such as read only memory (Read Only Memory, ROM) / RAM, disk, optical disk), including a number of instructions to make a terminal device (may be a mobile phone, computer, server, or network equipment, etc.) executes the method described in various embodiments of the present application.

[0117] The above is only the preferred embodiment of the present application, not therefore limit the patent scope of the present application, any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for detecting defects in bare PCB boards, characterized in that, The method includes: Obtain images of the bare PCB board to be inspected; The bare PCB image to be detected is input into the bare PCB defect detection model for defect detection, and the defect detection result of the bare PCB image is output. The bare PCB defect detection model is based on the YOLOv5 algorithm model. A convolutional block attention mechanism is added between each C3 module and CBS module in the neck layer of the YOLOv5 algorithm model, and the number of convolutional modules and upsampling layers is increased in the backbone layer of the YOLOv5 algorithm model to add a prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model. The convolutional block attention mechanism is used to enhance the ability of the bare PCB defect detection model to grasp key information in the feature map of the bare PCB. The PCB bare board defect detection model includes an input layer, a backbone layer, a neck layer, and a prediction layer. The prediction layer includes a first prediction head, a second prediction head, a third prediction head, and a fourth prediction head. The model inputs the image of the bare PCB to be detected into the PCB bare board defect detection model for defect detection and outputs the defect detection results of the image, including: The convolution module of the backbone layer extracts features from the preprocessed PCB bare board image to obtain an initial PCB bare board feature map. The initial PCB bare board feature map is downsampled to obtain PCB bare board feature maps of different sizes. The PCB bare board feature maps of different sizes include at least a first PCB bare board feature map, a second PCB bare board feature map, a third PCB bare board feature map, and a fourth PCB bare board feature map. The size of the first PCB bare board feature map is twice that of the second PCB bare board feature map, the size of the second PCB bare board feature map is twice that of the third PCB bare board feature map, and the size of the third PCB bare board feature map is twice that of the fourth PCB bare board feature map. The first PCB bare board feature map, the second PCB bare board feature map, the third PCB bare board feature map, and the fourth PCB bare board feature map are used as the PCB bare board feature maps to be fused. The first, second, third, and fourth bare PCB feature maps to be detected are input into the first, second, third, and fourth prediction heads, respectively. The scales of the first, second, third, and fourth bare PCB feature maps to be detected correspond one-to-one with the first, second, third, and fourth prediction heads, respectively.

2. The method as described in claim 1, characterized in that, The step of inputting the bare PCB image to be detected into the PCB bare board defect detection model for defect detection and outputting the defect detection result of the bare PCB image includes: The bare PCB image to be detected is input into the input layer for preprocessing to obtain a preprocessed bare PCB image to be detected. The preprocessing includes at least one of data augmentation, adaptive anchor frame calculation and adaptive image scaling. The data augmentation includes at least one of random cropping, random scaling and random arrangement. The preprocessed PCB bare board image to be detected is input into the backbone layer for feature extraction to obtain the PCB bare board feature map to be fused. The feature map of the bare PCB to be fused is input into the neck layer for feature fusion to obtain the feature map of the bare PCB to be detected; The feature map of the bare PCB to be detected is input into the prediction layer for detection, and the defect detection result of the bare PCB image is obtained.

3. The method as described in claim 2, characterized in that, The step of inputting the bare PCB feature map to be fused into the neck layer for feature fusion to obtain the bare PCB feature map to be detected includes: The fourth PCB bare board feature map is upsampled by 2 times and then fused and stitched with the third PCB bare board feature map to obtain the first fused PCB bare board feature map. The first fused PCB bare board feature map is upsampled by 2 times and then fused and stitched with the second PCB bare board feature map to obtain the second fused PCB bare board feature map. The second fused PCB bare board feature map is upsampled by 2 times and then fused and stitched with the first PCB bare board feature map to obtain the third fused PCB bare board feature map. The third fused PCB bare board feature map is upsampled by 2 times and then fused and stitched with the first PCB bare board feature map to obtain the fourth fused PCB bare board feature map. The fourth fused PCB bare board feature map is adaptively refined through a convolutional block attention mechanism and then downsampled by a factor of 2. The downsampled fourth fused PCB bare board feature map is then fused and stitched with the third fused PCB bare board feature map to obtain the first PCB bare board feature map to be detected. The first PCB bare board feature map to be detected is adaptively refined through a convolutional block attention mechanism and then downsampled by a factor of 2. The first PCB bare board feature map to be detected after being downsampled by a factor of 2 is then fused and stitched with the second fused PCB bare board feature map to obtain the second PCB bare board feature map to be detected. The second PCB bare board feature map to be detected is adaptively refined through a convolutional block attention mechanism and then downsampled by a factor of 2. The downsampled second PCB bare board feature map to be detected is then fused and stitched with the first fused PCB bare board feature map to obtain the third PCB bare board feature map to be detected. The third PCB bare board feature map to be detected is adaptively refined through a convolutional block attention mechanism and then downsampled by a factor of 2. The downsampled third PCB bare board feature map to be detected is then fused and stitched with the fourth PCB bare board feature map to obtain the fourth PCB bare board feature map to be detected. The first, second, third, and fourth bare PCB feature maps to be detected are used as the bare PCB feature maps to be detected.

4. The method as described in claim 3, characterized in that, Before inputting the bare PCB image to be detected into the PCB bare board defect detection model for defect detection and outputting the defect detection result of the bare PCB image, the method further includes: An initial PCB bare board defect detection model is constructed based on the YOLOv5 algorithm model, wherein the initial PCB bare board defect detection model includes an input layer, a backbone layer, a neck layer, and a prediction layer. In the initial PCB bare board defect detection model, a convolutional block attention mechanism is added between each C3 module and CBS module in the neck layer, and the number of convolutional layers and upsampling layers is increased in the backbone layer of the initial PCB bare board defect detection model, so that a prediction head of a preset scale is added to the prediction layer to obtain an improved PCB bare board defect detection model, wherein the prediction head of the preset scale is the fourth prediction head. Obtain a PCB bare board defect dataset and divide the PCB bare board defect dataset into a training set and a test set according to a preset ratio; The improved PCB bare board defect detection model is trained based on the training set to obtain the trained PCB bare board defect detection model. The trained PCB bare board defect detection model is tested and the confidence level is calculated based on the test set. The confidence level is compared with the confidence threshold; If the confidence level is greater than or equal to the confidence threshold, training is stopped, and the trained PCB bare board defect detection model with the current confidence level is used as the PCB bare board defect detection model. If the confidence level is less than the confidence threshold, then return and continue to execute the step of training the improved PCB bare board defect detection model based on the training set to obtain the trained PCB bare board defect detection model, until the confidence level reaches the confidence threshold.

5. The method as described in claim 4, characterized in that, The process of obtaining the PCB bare board defect dataset includes: Obtain a number of images showing defects in bare PCB boards. An augmentation operation is performed on the aforementioned number of PCB bare board defect images to obtain augmented PCB bare board defect images. The augmentation operation includes at least one of random rotation, horizontal translation, vertical translation, scaling, horizontal flipping, and random enhancement of image brightness. The expanded PCB bare board defect images are used as the PCB bare board defect dataset.

6. A PCB bare board defect detection device according to any one of claims 1-5, characterized in that, The PCB bare board defect detection device includes: The acquisition module is used to acquire images of the bare PCB board to be inspected. The detection module is used to input the bare PCB image to be detected into the PCB bare board defect detection model for defect detection, and output the defect detection result of the bare PCB image. The bare PCB defect detection model is based on the YOLOv5 algorithm model. A convolutional block attention mechanism is added between each C3 module and CBS module in the neck layer of the YOLOv5 algorithm model, and the number of convolutional modules and upsampling layers is increased in the backbone layer of the YOLOv5 algorithm model to add a prediction head of a preset scale in the prediction layer of the YOLOv5 algorithm model. The convolutional block attention mechanism is used to enhance the ability of the bare PCB defect detection model to grasp key information in the feature map of the bare PCB.

7. A PCB bare board defect detection device, characterized in that, The PCB bare board defect detection device includes: a memory, a processor, and a PCB bare board defect detection program stored in the memory and executable on the processor, wherein the PCB bare board defect detection program is configured to implement the PCB bare board defect detection method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium stores a PCB bare board defect detection program, which, when executed by a processor, implements the PCB bare board defect detection method as described in any one of claims 1 to 5.

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