Access heat map generation method, memory device, and non-transitory computer readable medium

Abstract

This application relates to access heat map generation at a memory device. In some examples, a memory device can maintain a register for tracking where access operations occur, for which a plurality of fields of the register can map access operations to addresses of the memory device. In some cases, in response to a first access operation performed to a first address of the memory device, the memory device can increment a first field and a second field of the register, and in response to a second access operation performed to a second address of the memory device, the memory device can increment the first field and a third field of the register. In some examples, the memory device can maintain a second register having a set of fields each indicating a respective address for which access occurs satisfying a threshold.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 831,270, filed June 2, 2022, entitled “ACCESS HEATMAP GENERATION AT A MEMORY DEVICE,” by Meeramohideen Mohamed, et al., assigned to the present assignee, and expressly incorporated herein by reference. TECHNICAL FIELD

[0003] The technical field relates to access heatmap generation at a memory device. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communications devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically denoted by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any one of which can be stored. To access stored information, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state stored in the memory device. To store information, a component can write (e.g., program, set, designate) a state in the memory device.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, or NOR and NAND memory devices, etc. Memory cells can be described in relation to a volatile or non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time even in the absence of an external power source. Memory cells configured in a volatile configuration can lose a stored state when disconnected from an external power source. SUMMARY

[0006] A method is described. The method can include performing, at a memory device, one or more access operations each associated with a respective address of a plurality of addresses of the memory device; modifying, in a register of the memory device comprising a plurality of fields, for each of the one or more access operations, a respective value of each field of a plurality of sets of fields of the plurality of fields associated with the respective address; receiving, from a host device, an information request associated with access operation occurrences at the memory device; and transmitting, by the memory device, an indication of the respective value of at least one field of the plurality of fields to the host device based on the information request.

[0007] An apparatus is described. The apparatus can include a memory device; and a controller coupled with the memory device and configured to cause the apparatus to perform one or more access operations each associated with a respective address of a plurality of addresses of the memory device; modify, in a register comprising a plurality of fields, for each of the one or more access operations, a respective value of each field of a plurality of sets of fields of the plurality of fields associated with the respective address; receive, from a host device, an information request associated with access operation occurrences at the memory device; and transmit, based on the information request, an indication of the respective value of at least one field of the plurality of fields to the host device.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium can store code including instructions executable by a processor of an electronic device to cause the electronic device to perform one or more access operations each associated with a respective address of a plurality of addresses of a memory device; modify, in a register of the memory device comprising a plurality of fields, for each of the one or more access operations, a respective value of each field of a plurality of sets of fields of the plurality of fields associated with the respective address; receive, from a host device, an information request associated with access operation occurrences at the memory device; and transmit, by the memory device, an indication of the respective value of at least one field of the plurality of fields to the host device based on the information request. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein.

[0010] Figure 2 An example of a memory die that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein.

[0011] Figure 3 An example of a system that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein.

[0012] Figure 4An example of a process flow that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein.

[0013] Figure 5 An example of a block diagram of a memory device that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein.

[0014] Figure 6 A flow diagram of one or more methods that support access heat map generation at a memory device is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] In some memory implementations, a host device and one or more memory devices coupled with the host device can be configured to support monitoring access operation occurrences (e.g., number of access operations, number of read operations, number of write operations, count of operations, frequency of operations) of data stored at the memory devices. For example, a memory device can include a table having an entry for each data address (e.g., each data page), and can set (e.g., adjust, increment) an entry of the table when an access operation is performed at the corresponding address (e.g., in response to an access command). However, such a table can occupy memory device storage resources (e.g., associated with the number of entries of the table), or can involve memory device processing or signaling load (e.g., maintaining the table, communicating information of the table), among other resource usage. Additionally or alternatively, a host device can include a table having a flag (e.g., an indication of a recent access) for each data address, and based on a command to transfer an access data address, the host device can set a corresponding flag to indicate the address was accessed. However, such techniques can not accurately indicate a number of access operations (e.g., number of access operations in a sampled time interval), for example, in cases where the host device issues multiple access commands for the same address, or in cases where the memory device can be accessed by another host device, among other cases.

[0016] According to examples disclosed herein, a memory device associated with a set of addresses (e.g., memory addresses, logical addresses, physical addresses) can include a storage location, such as a register (e.g., an access count register), for tracking storage locations at which access operations occur, for which access operations of a given address (e.g., a given page) of the memory device can be mapped to a plurality of fields, such as a plurality of fields of the register (e.g., according to a plurality of mapping functions for each address), and for which each field can be associated with access operations of a respective subset of addresses of the memory device. For example, in response to a first access operation performed to a first address of the memory device, the memory device can increment a first field and a second field of the register (e.g., according to a first set of mappings associated with the first address), and in response to a second access operation performed to a second address of the memory device, the memory device can increment the first field and a third field of the register (e.g., according to a second set of mappings associated with the second address). In some examples, such techniques can be supplemented by the memory device maintaining a second storage location (e.g., a second register) having a set of fields each indicating a respective address that has been most recently accessed (e.g., within a sampling interval according to a first-in-first-out policy).

[0017] The memory device can provide values of one or more fields (e.g., such registers) to a host device, which can infer relative access frequencies of respective addresses of the memory device based on the values of the one or more fields. For example, for implementations in which each field of the register indicates a number of access operations associated with a respective set of addresses (e.g., in which the fields are associated with partially overlapping subsets of addresses), a minimum value of a plurality of fields associated with a given address can indicate a maximum number of access operations that can have been performed to the given address. In some examples, various aspects of such monitoring at the memory device can be configurable, including such configuration in response to signaling from a host device, which can support various aspects of such monitoring in response to different operating conditions in a related system. According to these and other examples, the described techniques for monitoring access operation occurrences at a memory device can be implemented to reduce resource utilization (e.g., to reduce monitoring storage size or complexity, to reduce monitoring signaling complexity, to reduce monitoring processing load, to reduce monitoring power consumption), or to improve access operation monitoring accuracy, as well as other advantages as compared to other techniques for monitoring access operation occurrences.

[0018] As described with reference to Figure 1 and 2 features of the disclosure are first described in the context of a system and a die. Features of the disclosure are described in the context of a system and a process flow as described with reference to Figures 3-4 Features of the disclosure are described in the context of a system and a process flow as described with reference to Figures 5-6The apparatus diagrams and flowcharts described relate to access heat map generation at a memory device and describe these and other features of the disclosure with reference to them.

[0019] Figure 1 An example of a system 100 that supports access heat map generation at a memory device is shown in accordance with the examples disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device, such as the memory device 110.

[0020] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, a networked device, a vehicle controller, and the like. The memory device 110 can be a component of the system 100 for storing data of one or more other components of the system 100.

[0021] Portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor (e.g., circuitry, processing circuitry, processing component) within a device that uses memory to perform processes within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, a networked device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or any combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host (e.g., the host device 105).

[0022] The memory device 110 can be a standalone device or component for providing physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configured to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 can be used to support one or more of modulation schemes to modulate signals, various pin configurations for transmitting signals, various form factors for physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other functionality.

[0023] Memory device 110 can be used to store data for components of host device 105. In some examples, memory device 110 (e.g., operating as an auxiliary-type device to host device 105, operating as an append-type device to host device 105) can respond and execute commands provided by host device 105 through external memory controller 120. Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0024] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of host device 105 can be coupled with each other using bus 135.

[0025] Processor 125 can be used to provide functionality (e.g., control functionality) for system 100 or host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by or be part of processor 125.

[0026] BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0027] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a capacity (e.g., a desired capacity, a specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a set of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more sections), where each memory cell can be used to store one or more bits of data. A memory device 110 that includes two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0028] Memory die 160 can be an example of a two-dimensional (2D) array of memory cells, or can be an example of a three-dimensional (3D) array of memory cells. In some examples, 2D memory die 160 can include a single memory array 170. In some examples, 3D memory die 160 can include two or more memory arrays 170 that can be stacked one on top of another or positioned in close proximity to one another (e.g., with respect to a substrate). In some examples, memory arrays 170 in 3D memory die 160 can be referred to or otherwise include different sets (e.g., decks, levels, tiers, dies). 3D memory die 160 can include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high stacked memory arrays). In some 3D memory die 160, different decks can share common access lines, such that some decks can share one or more of a word line, a digit line, or a plate line.

[0029] Device memory controller 155 can include components (e.g., circuitry, logic) that can be used to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations and can be used to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be used to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0030] In some examples, the memory device 110 can communicate information (e.g., data, commands, or both) with the host device 105. For example, the memory device 110 can receive a write command indicating that the memory device 110 is to store data received from the host device 105 or receive a read command indicating that the memory device 110 is to provide data stored in the memory die 160 to the host device 105, among other types of information communications.

[0031] The local memory controller 165 (e.g., local to the memory die 160) can include components (e.g., circuitry, logic) that can be used to control operations of the memory die 160. In some examples, the local memory controller 165 can be used to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165 or the external memory controller 120 that can perform the various functions described herein. Thus, the local memory controller 165 can be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver to receive signals (e.g., from the external memory controller 120), a transmitter to transmit signals (e.g., to the external memory controller 120), a decoder to decode or demodulate received signals, an encoder to encode or modulate signals to be transmitted, or various other components that can be used to support operations of the described device memory controller 155 or local memory controller 165, or both.

[0032] The external memory controller 120 can be used to enable the transfer of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105, such as the processor 125 and the memory device 110). The external memory controller 120 can handle (e.g., translate, translate) communication messages exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105 or the functions thereof described herein can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software implemented by the processor 125 or other components of the system 100 or the host device 105 or some combination thereof. While the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0033] Components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be used to support communication between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device 110. Each channel 115 can include one or more signal paths (e.g., transmission media, conductors) between terminals associated with components of the system 100. A signal path can be an example of an electrically conductive path for carrying a signal. For example, a channel 115 can be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host device 105 and a second terminal at the memory device 110. A terminal can be an example of an electrically conductive input or output point of a device of the system 100, and a terminal can be used to act as part of a channel.

[0034] The channels 115 (and associated signal paths and terminals) can be dedicated to transferring one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling can be transferred on the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on a rising edge and a falling edge of a clock signal).

[0035] In some instances of the system 100, the host device 105 and the one or more memory devices 110 coupled with the host device 105 can be configured to support monitoring access operation occurrences (e.g., a number of access operations, a number of read operations, a number of write operations) for data stored at the memory devices 110. For example, the memory devices 110 can include a table having an entry for each data address (e.g., each data page), and can set (e.g., adjust, increment) an entry of the table upon performing an access operation for the corresponding address (e.g., in response to an access command). However, such a table can occupy storage resources of the memory devices 110 (e.g., associated with a number of entries of the table), or can involve processing or signaling loads of the memory devices 110 (e.g., maintaining the table, communicating information of the table), among other resource usage. Additionally or alternatively, the host device 105 can include a table having a flag (e.g., an indication of a recent access) for each data address, and based on a command to transfer an access data address, the host device 105 can set a corresponding flag to indicate the address was accessed. However, such techniques can not accurately indicate a number of access operations, for example, in a case where the host device 105 issues multiple access commands for a same address, or in a case where the memory device 110 can be accessed by another host device 105, among other cases.

[0036] According to examples as disclosed herein, a memory device 110 associated with a set of addresses (e.g., of a set of one or more memory dies 160) can include a storage location for tracking access operation occurrences, such as a register (e.g., an access count register), for which access operations for a given address (e.g., a given page) of the memory device 110 can be mapped to a plurality of fields, such as a plurality of fields of the register (e.g., according to a plurality of mapping functions per address), and for which each field can be associated with access operations for a respective subset of addresses of the memory device 110. For example, in response to a first access operation performed for a first address of the memory device 110, the memory device 110 (e.g., a device memory controller 155, a local memory controller 165) can increment a first field and a second field of the register (e.g., according to a first set of mappings associated with the first address), and in response to a second access operation performed for a second address of the memory device 110, the memory device 110 can increment the first field and a third field of the register (e.g., according to a second set of mappings associated with the second address). In some instances, such techniques can be supplemented by the memory device 110 (e.g., the device memory controller 155, the local memory controller 165) maintaining a second storage location (e.g., a second register) having a set of fields each indicating a respective address that has been most recently accessed (e.g., within a sampling interval, according to a first-in-first-out policy).

[0037] The one or more memory devices 110 can provide values for one or more fields of such registers, for example, to the host device 105 (e.g., an external memory controller 120), which can infer, based on the values of the one or more fields, relative access frequencies for respective addresses of the one or more memory devices 110. For example, for implementations in which each field of the register indicates a number of access operations associated with a respective set of addresses (e.g., in which the fields are associated with partially overlapping subsets of addresses), the minimum value of the multiple fields associated with a given address can indicate a maximum number of access operations that can have been performed for the given address. In some examples, the host device 105 can perform an evaluation based on such minimum values associated with respective addresses to determine a distribution of data across various portions of memory included in the one or more memory devices 110. For example, based on values of such registers, the host device 105 can support storing data that is accessed relatively frequently (e.g., “hot” data) in relatively faster portions of memory (e.g., relatively faster memory devices 110 or memory dies 160, relatively higher performance or higher tier memory devices 110 or memory dies 160), such as a cache, and can store data that is accessed relatively infrequently (e.g., “cold” data) in relatively slower portions of memory (e.g., relatively slower memory devices 110 or memory dies 160, relatively lower performance or lower tier memory devices 110 or memory dies 160), such as non-volatile memory, among other techniques. In some examples, such registers can be configured based on indications (e.g., commands, requests) from the host device 105, which can support dynamic access operation monitoring in response to various operating conditions of the system 100. In accordance with these and other examples, the described techniques for monitoring access operation occurrences at memory devices 110 can be implemented to reduce resource utilization (e.g., to reduce monitoring storage size or complexity, to reduce monitoring signaling complexity, to reduce monitoring processing load, to reduce monitoring power consumption), or to improve access operation monitoring accuracy, among other advantages over other techniques for monitoring access operation occurrences.

[0038] Figure 2 An example of a memory die 200 that supports access heat map generation at a memory device is shown in accordance with examples disclosed herein. The memory die 200 can be a reference to the memory die 160 of FIG. 1, for example. The memory die 200 includes a memory array 210, a memory controller 220, and a register 230. The memory array 210 can include a plurality of memory devices 110, such as the memory devices 110 of FIG. 1, for example. The memory controller 220 can be a reference to the memory controller 120 of FIG. 1, for example. The register 230 can be a reference to the register 130 of FIG. 1, for example. The register 230 can include one or more fields 232, such as the fields 132 of FIG. 1, for example. The register 230 can be configured to store values for the one or more fields 232, such as the values 132 of FIG. 1, for example. The register 230 can be configured to store values for the one or more fields 232 based on access operation occurrences at the memory array 210, such as the access operation occurrences 131 of FIG. 1, for example. The register 230 can be configured to store values for the one or more fields 232 based on access operation occurrences at the memory array 210 in accordance with the techniques described herein, for example. Figure 1An example of a memory die 160 is depicted. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205 that are programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, the memory cells 205 can be used to store one bit of information (e.g., a logical 0 or a logical 1) at a time. In some examples, the memory cells 205 (e.g., multi-level memory cells) can be used to store more than one bit of information at a time (e.g., logical 00, logical 01, logical 10, logical 11). In some examples, the memory cells 205 can be arranged in an array, as described with reference to Figure 1 A memory array 170 is depicted.

[0039] In some examples, the memory cells 205 can store an electrical charge representing a programmable state in a capacitor. DRAM architectures can include a capacitor that includes a dielectric material to store an electrical charge representing a programmable state. The memory cells 205 can include a logical storage component (e.g., a capacitor 230) and a switching component 235 (e.g., a cell selection component). The capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor 230 can be coupled with a voltage source 240, which can be a cell plate reference voltage, such as Vpl, or can be a ground voltage, such as Vgnd. Other storage devices and components are possible in other examples of the memory die 200 according to the examples disclosed herein. For example, some examples of the memory cells 205 can implement a non-linear dielectric material in the capacitor 230, such as in a ferroelectric memory architecture. In some other examples, a logical state can be stored as a physical state of a programmable material (e.g., material state, resistance state, atomic arrangement, atomic distribution), such as in a material memory architecture (e.g., phase change memory, threshold memory, MRAM, RRAM). In some other examples, the memory die 200 according to the examples disclosed herein can store one or more logical states using various arrangements of one or more transistors, such as in NAND memory, SRAM memory, and other architectures. SS In some examples, the memory cells 205 can store an electrical charge representing a programmable state in a capacitor. DRAM architectures can include a capacitor that includes a dielectric material to store an electrical charge representing a programmable state. The memory cells 205 can include a logical storage component (e.g., a capacitor 230) and a switching component 235 (e.g., a cell selection component). The capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor 230 can be coupled with a voltage source 240, which can be a cell plate reference voltage, such as Vpl, or can be a ground voltage, such as Vgnd. Other storage devices and components are possible in other examples of the memory die 200 according to the examples disclosed herein. For example, some examples of the memory cells 205 can implement a non-linear dielectric material in the capacitor 230, such as in a ferroelectric memory architecture. In some other examples, a logical state can be stored as a physical state of a programmable material (e.g., material state, resistance state, atomic arrangement, atomic distribution), such as in a material memory architecture (e.g., phase change memory, threshold memory, MRAM, RRAM). In some other examples, the memory die 200 according to the examples disclosed herein can store one or more logical states using various arrangements of one or more transistors, such as in NAND memory, SRAM memory, and other architectures.

[0040] The memory die 200 can include access lines (e.g., word lines 210, digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line can be an electrically conductive line coupled with a memory cell 205 and can be used to perform an access operation on the memory cell 205. In some examples, a word line 210 can be referred to as a row line. In some examples, a digit line 215 can be referred to as a column line or a bit line. References to an access line, a row line, a column line, a word line, a digit line, or a bit line, or the like, can be interchanged without affecting understanding. The memory cells 205 can be located at intersections of the word lines 210 and the digit lines 215.

[0041] Operations such as reads and writes can be performed on memory cells 205 by activating an access line such as word line 210 or digit line 215. A single memory cell 205 can be accessed at the intersection of a biased word line 210 and digit line 215 (e.g., a voltage is applied to the word line 210 or digit line 215). The intersection of a word line 210 and digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as an address of a memory cell 205. Activating a word line 210 or digit line 215 can include applying a voltage to the respective line.

[0042] Access to memory cells 205 can be controlled by row decoder 220 or column decoder 225, or any combination thereof. For example, row decoder 220 can receive a row address from local memory controller 260 and activate a word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and can activate a digit line 215 based on the received column address.

[0043] Selection or deselection of a memory cell 205 can be accomplished by activating or deactivating a switching component 235 using a word line 210. Capacitor 230 can be coupled with a digit line 215 using switching component 235. For example, when switching component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switching component 235 is activated, capacitor 230 can be coupled with digit line 215.

[0044] Sensing component 245 can be used to detect a state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sensing component 245 can include one or more sense amplifiers to amplify or otherwise convert a signal generated as a result of accessing memory cell 205. Sensing component 245 can compare the detected signal from memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output 255) and can be indicated to another component of a memory device (e.g., memory device 110) that includes memory die 200.

[0045] Local memory controller 260 can control access to memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). Local memory controller 260 can be a reference Figure 1An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be used to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to a host (e.g., the host device 105) based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate a target word line 210 and a target digit line 215. The local memory controller 260 can also generate and control various signals (e.g., voltages, currents) used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can vary and can be different for the various operations discussed in operating the memory die 200.

[0046] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 can be used to perform other access operations not listed herein or other operations related to operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0047] The local memory controller 260 can be used to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired state (e.g., a logic state, a charge state). The local memory controller 260 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a signal (e.g., a write pulse, a write voltage) to the digit line 215 during the write operation to store a particular state (e.g., a charge) in the capacitor 230 of the memory cell 205. The signal used as part of the write operation can include one or more voltage levels for a duration of time.

[0048] The local memory controller 260 can be used to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a state (e.g., a logic state, a charge state) stored in a memory cell 205 of the memory die 200 can be evaluated (e.g., read, determined, identified). The local memory controller 260 can identify a target memory cell 205 on which to perform the read operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal (e.g., a charge, a voltage) to the sense component 245 in response to biasing the access lines. The sense component 245 can amplify the signal. The local memory controller 260 can activate the sense component 245 (e.g., latch the sense component) and compare the signal received from the memory cell 205 to a reference (e.g., the reference 250). Based on the comparison, the sense component 245 can determine a logic state stored on the memory cell 205.

[0049] According to examples disclosed herein, a memory die 200 can be associated with a set of addresses (e.g., pages, row addresses, addresses associated with respective word lines 210 or groups of word lines 210), and the memory die 200 (e.g., local memory controller 260) or a memory device 110 including the memory die 200 can include a register to track access operation occurrences for which access operations to a given address of the memory die 200 can be mapped to multiple fields of the register, and for which each field can be associated with access operations to a respective subset of addresses of the memory die 200. For example, in response to a first access operation performed to a first address of the memory die 200, a first field and a second field of the register can be incremented, and in response to a second access operation performed to a second address of the memory die 200, the first field and a third field of the register can be incremented. Such techniques can be implemented at the memory die 200 or a memory device 110 including the memory die 200 or some combination thereof to reduce resource utilization (e.g., reduce monitoring storage size or complexity, reduce monitoring signaling complexity, reduce monitoring processing load, reduce monitoring power consumption), or improve access operation monitoring accuracy, among other advantages as compared to other techniques for monitoring access operation occurrences.

[0050] Figure 3 An example of a system 300 to support access heat map generation at a memory device is shown in accordance with examples disclosed herein. The system 300 can include a host device 105-a and a memory device 110-a, which can be examples of the host device 105 and the memory device 110 described with reference to Figure 1 The described examples of corresponding devices. In some examples, the system 300 can be configured to support aspects of an industry standard (e.g., a specification, such as the Compute Express Link (CXL) specification), in which case the host device 105-a and the memory device 110-a can perform operations or signaling in accordance with aspects of the industry standard. Although illustrated with a single memory device 110-a, the system 300 can operate in accordance with various memory systems or subsystems, which can include various sets of one or more memory arrays (e.g., memory array 170) arranged among one or more memory dies (e.g., memory die 160, memory die 200) of one or more memory devices 110, each of which can be associated with various characteristics (e.g., performance tiers, access latencies, throughput, power consumption, cost).

[0051] Memory device 110-a and host device 105-a can be configured to monitor access operation occurrences (e.g., a number of read operations, a number of write operations, a number of read operations and write operations, a measure of memory stress) of data units stored at memory device 110-a. For example, to support this monitoring, memory device 110-a (e.g., device memory controller 155, local memory controller 165) can maintain a register 305 (e.g., an access register, an access count register, a page access register, a page-based heat map, a page access bloom, a table, an array) that can track a number of access commands for various data units stored at memory device 110-a. Register 305 can include a set of fields 310, each of which can accumulate (e.g., count) a number of access operations performed to a respective subset of data units associated with memory device 110-a that are being monitored. In some examples, each field 310 can be configured as a counter that can store a value indicative of a number of access operations performed to a respective subset of data units. Register 305 can be an example of a data structure that supports indicating access patterns of memory device 110-a (e.g., indicating which addresses are more frequently accessed than other addresses).

[0052] Register 305 can operate according to a mapping filter 320 (e.g., an access count filter, a mapping tree, a hash tree, a count bloom filter) that maps each data unit associated with a respective identifier 325 (e.g., an index, a page index, an address), a plurality of fields 310. For example, mapping filter 320 can include a plurality of mapping functions 330 (e.g., k hash functions) such that an access operation associated with a given identifier 325 can be mapped to (e.g., accumulated, counted) a plurality of fields 310 (e.g., k fields 310). Each mapping function 330 can be configured to receive an identifier 325 as input and generate (e.g., using a hash function) an index of a field 310 as output. In such examples, each mapping function 330 can be configured to generate an index of a different field 310 for a given identifier 325. Thus, each identifier 325 can be associated with a respective set of a plurality of fields 310 (e.g., equal to a number of mapping functions 330 of mapping filter 320 or a number of fields 310 for each identifier 325), and each field 310 can be associated with a respective set of a plurality of identifiers 325 (e.g., a respective set of a plurality of addresses). The example of mapping filter 320 illustrates an example with three mapping functions 330 (e.g., k = 3) that can correspond to mapping a number of access operations of each identifier 325 to three fields 310, but other implementations of mapping filter 320 according to examples disclosed herein can include any number of two or more mapping functions 330.

[0053] The data units associated with the identifiers 325 can correspond to respective addresses or groups of addresses of the memory device 110-a. For example, each identifier 325 can be associated with one or more logical addresses, one or more physical addresses, or both, any of which can be used (e.g., as input) to maintain the registers 305. A physical address of a data unit can correspond to a physical location of a memory array of the memory device 110-a (e.g., a location of a set of memory cells 205, an address of a word line 210 or a set of word lines 210). A logical address of a data unit can correspond to a logical identifier of the data unit, which can be mapped to one or more physical addresses by way of a logical-to-physical mapping (e.g., an L2P mapping that can be maintained by the memory device 110-a). In some examples, a logical address can be maintained (e.g., kept constant) for a data unit despite the data unit moving from one physical address to another (e.g., due to various memory management techniques of the memory device 110-a). Thus, the host device 105-a can include an indication of a logical address for a given access operation, and the memory device 110-a can manage aspects of the L2P mapping that support the memory device 110-a accessing various physical addresses while maintaining a mapping of a given data unit to a respective logical address.

[0054] In some examples, the data units associated with each identifier 325 can correspond to pages of data, and an address (e.g., of an access operation) can be used to generate an identifier 325 of a page. In some examples, a bitwise operation (e.g., a bit shift, a right shift operator) can be used on a logical address to generate an identifier 325 associated with a page. For example, an identifier 325 can correspond to a page index, where a page index of a given address (e.g., a physical address, a logical address, a host physical address (HPA)) can be determined based on a bit shift operation on the given address (e.g., discarding a quantity of least significant bits of the given address). In some examples, a page can have a predetermined size (e.g., an amount of data), and the memory device 110-a can be configured to monitor and maintain an access count for a range of pages (e.g., a configurable range of pages, a contiguous range of pages). For example, a size of each page can be 4 kilobytes (KiB), and aligned to 4 KiB, and a page index (e.g., an identifier 325) associated with a given address can be calculated by performing a 12-bit right shift operator on the given address.

[0055] In some cases, a data page can be interleaved across multiple memory arrays (e.g., multiple memory arrays 170) of memory device 110-a. For example, a first portion of a page (e.g., one KiB of data) can be stored in a first memory array, a second portion of the page can be stored in a second memory array, a third portion of the page can be stored in a third memory array, and a fourth portion of the page can be stored in a fourth memory array. In such cases, for each memory array, the HPA of each portion of the page, and thus the identifier 325, can be the same. Accordingly, memory device 110-a can reuse the results of the mapping function 330 for each portion of the interleaved page.

[0056] Memory device 110-a can update register 305 based on various commands to access memory device 110-a. For example, in response to a command to access an address (e.g., a read command or a write command that can be a command received from host device 105-a or another host device 105, not shown), memory device 110-a can input an identifier 325 (e.g., a page index) corresponding to the address into mapping filter 320 (e.g., into a set of mapping functions 330), which the memory device can support incrementing a value of each field 310 associated with identifier 325 (e.g., incrementing the value by one). In some instances, multiple identifiers 325 can be associated with the same field 310 (e.g., can hash to the same field), such that a value of field 310 can represent a total number of access operations for all data units associated with field 310. Accordingly, memory device 110-a can support inferring a relative number of access operations for a data unit by selecting a minimum value of a set of fields 310 associated with the data unit, which can represent a maximum number of access operations associated with the data unit (e.g., assuming that other data units associated with the field 310 having the minimum value are not accessed or otherwise associated with a zero access count).

[0057] In some cases, an error rate (e.g., an accuracy, a probability that a minimum value is greater than an actual number of access operations performed for a data unit) of register 305 can be calculated according to a number of fields 310 of register 305, a number of mapping functions 330 (e.g., a number of mapping filters 320 per identifier 325), a number of identifiers 325 being monitored (e.g., a number of identifiers 325 of memory device 110-a or some monitored subset thereof), or any combination thereof. For example, host device 105-a can calculate a false positive rate, and can modify parameters of mapping filter 320 (e.g., via an indication to memory device 110-a) to reduce the false positive rate.

[0058] In some examples, the memory device 110-a can monitor the number of access operations according to a pre-cache policy or according to a post-cache policy. For example, if the memory device 110-a monitors according to a pre-cache policy, the memory device 110-a can update the register 305 based on access operations to pages stored in a cache of the memory device 110-a (e.g., cached data) and pages stored in a main array or other relatively longer latency (e.g., relative to the cache) storage of the memory device 110-a. Additionally or alternatively, if the memory device 110-a monitors according to a post-cache policy, the memory device 110-a can not update the register 305 based on access operations performed to data pages stored in the cache, but can update the register 305 based on access operations performed to pages stored in the main array or other relatively longer latency (e.g., relative to the cache) storage.

[0059] Additionally or alternatively, the memory device 110-a (e.g., the device memory controller 155, the local memory controller 165) can maintain a register 345. The register 345 can be used to track a set of data units (e.g., addresses) of the memory device 110-a for which an access characteristic satisfies a threshold. For example, the register 345 can be used to track some number of recently accessed data units (e.g., N recently accessed hot pages). The register 345 can include a set of fields 350, each of which can be configured to store an indication of an identifier 325. As part of monitoring access operations, the memory device 110-a can update the register 345 to reflect which addresses were frequently accessed during a monitoring period, or recently accessed during a monitoring period, among other access characteristics. In some examples, the register 305 and the register 345 can be collectively referred to as a heat map maintained or generated by the memory device 110-a.

[0060] For example, based on a data page access command, the memory device 110-a can estimate the access count for the page by identifying the minimum value from the set of fields 310 corresponding to the identifier 325 of the page (e.g., before, during, or after incrementing the set of fields 310). If the minimum value satisfies a threshold (e.g., if the minimum value of the fields 310 is greater than or equal to the threshold number, e.g., 10 accesses occurred), the memory device 110-a can add the identifier 325 of the page to the register 345. In some examples, the register 345 can operate according to a membership filter (e.g., a membership Bloom filter) such that, before adding the identifier 325 to the register 345, the memory device 110-a can determine whether the identifier 325 is already included in the register 345 (e.g., to avoid filling the register 345 with duplicate entries). If the identifier 325 is already included in the register 345, the memory device 110-a can refrain (e.g., prevent) from adding the identifier 325 to the register 345. In some examples, the register 345 can be implemented according to a ring buffer policy or other first-in-first-out (FIFO) policy (e.g., a ring buffer of size N to track N most recently accessed hot pages). For example, if the register 345 is full (e.g., if each field 350 of the register 345 includes an identifier 325), the memory device 110-a can remove the oldest entry in the register 345 and replace the associated field 350 with the new identifier 325.

[0061] In some cases, the memory device 110-a can not update the register 305, the register 345, or both, for every received access command of the set of monitored pages. For example, the memory device 110-a can update the register 305, the register 345, or both, according to a periodicity or proportion of access operations. That is, the memory device 110-a can update the register 305, the register 345, or both, once per access command period (e.g., once every three access command periods, once every four access command periods). In some cases, this periodicity can be referred to as a sampling ratio.

[0062] Host device 105-a (e.g., external memory controller 120) can transmit one or more indications 335 (e.g., via a command, a request of one or more channels 115) associated with monitoring of access operations by memory device 110-a. For example, indications 335 can include a command to monitor occurrences of access operations at memory device 110-a (e.g., a START MONITOR command to initiate a monitoring period at memory device 110-a). In some examples, such a command can include a set of parameters (e.g., for at least one monitoring period), which can include an indication of a threshold value (e.g., a threshold value for adding an identifier 325 to an access count of register 345, a “hot page” threshold value), an indication of one or more types of access operations to monitor (e.g., read operations, write operations, read and write operations), an indication of a set of pages to monitor (e.g., a range of addresses corresponding to a set of pages), a size of register 345 (e.g., a number of most recently accessed pages to monitor, a number of fields 350, a value of N), an indication to monitor pre-cache operations, or an indication to monitor post-cache operations, or any combination thereof, among other parameters. In some examples, a size of register 305 (e.g., a number of fields 310) can be configured during an initiation operation (e.g., by memory device 110-a, by host device 105-a). In some cases, a number of mapping functions 330 (e.g., a value of k) can be determined by memory device 110-a (e.g., by a memory controller of memory device 110-a). In some other examples, a size of register 305, a number of mapping functions 330, or both, can be included in a set of parameters signaled by host device 105-a.

[0063] In some cases (e.g., during a monitoring period), the indication 335 can include a request for information associated with access operation occurrences at the memory device 110-a (e.g., a request to retrieve information associated with a monitoring period from the memory device 110-a, a READ MONITOR command). In response to such an indication 335, the memory device 110-a can transmit information 340 (e.g., information associated with a monitoring period via one or more channels 115) to the host device 105-a. In different instances, the information 340 can include an indication of values of one or more fields 310 of the register 305 (e.g., each field 310 of the register 305, a requested subset of fields 310, e.g., associated with an identifier 325 indicated in the request), an indication of a number of fields 310 of the register 305, an indication of a size of the fields 310 of the register 305, an indication of a total number of access operations (e.g., to support an evaluation of accuracy or false positive rate for the register 305), an indication of an identifier 325 from one or more fields 350 of the register 345, an indication of a sampling ratio (e.g., to support an evaluation of global ordering of pages across different memory hierarchies), or any combination thereof. In some instances, a duration of a monitoring can be determined by the host device 105-a, and can correspond to a duration between a command to monitor access operation occurrences (e.g., a START MONITOR command) and a request for information associated with access operation occurrences (e.g., a READ MONITOR command).

[0064] Additionally or alternatively, the indication 335 can include an indication (e.g., a command, a request) to retrieve access operation information for a specified set of pages (e.g., a READ MONITOR PAGE RANGE to retrieve a subset of the monitored set of pages). For example, such an indication 335 can include an indication of a set of identifiers 325. In response to such an indication 335, the memory device 110-a can determine an access count value for each unit of data (e.g., each page) corresponding to the set of identifiers 325 (e.g., by selecting a minimum value of the set of fields 310 corresponding to each page), and can transmit a respective indication of the access count values to the host device 105-a. In some other instances, the memory device 110-a can return a value of each field 310 associated with the set of identifiers, which can support the host device 105-a to select a minimum value for each identifier 325.

[0065] In some examples, the host device 105-a can monitor data units that are larger than a page size (e.g., larger than 4 KiB). For example, the host device 105-a can configure a page size of the memory device 110-a (e.g., as part of a power-on or boot-up procedure of the memory device 110-a) to be an integer multiple of the page size (e.g., a larger power-of-two value within the confines of a controller of the memory device 110-a, such as 8 KiB or 16 KiB). Additionally or alternatively, the host device 105-a can monitor larger data units without changing the page size. For example, the host device 105-a can use statistics of access frequencies of a set of pages within a segment of interest, such as a minimum number of access operations of the set of pages, a maximum number of access operations of the set of pages, a median value of access operations of the set of pages, a mode of access operations of the set of pages, or any combination thereof.

[0066] In some examples, the host device 105-a (e.g., the external memory controller 120, the processor 125) can use the information 340 to generate and store the registers 365, the registers 355, or both (e.g., corresponding to portions of the registers 305 and portions of the registers 345 included in the information 340, respectively). In some cases, the host device 105-a can use an identifier 375 associated with a data unit (e.g., corresponding to the identifier 325) as an input to one or more mapping functions 360 to determine an estimated access count (e.g., an upper bound on the access count) for the data unit, each of the mapping functions can correspond to a respective mapping function 330 (e.g., share a corresponding mapping with the respective mapping function). For example, the mapping filter 380 can use a set of the mapping functions 360 to determine a set of fields 370 associated with the identifier 375, and can select an output value of the set (e.g., a minimum value) as the estimated access count. Additionally or alternatively, the host device 105-a can transmit an indication 335 (e.g., a command) to the memory device 110-a to compute the estimated access count. Accordingly, the memory device 110-a can compute the estimated access count and transmit the estimated access count to the host device 105-a.

[0067] Because host device 105-a can perform processing steps using register 365 (e.g., using processing capabilities of host device 105-a or its external memory controller 120 or processor 125 to determine estimated access counts or identify pages to transfer), the complexity of implementation at memory device 110-a can be reduced, such that memory device 110-a can implement portions of hot map generation that can not be efficiently or accurately performed at host device 105-a. For example, such techniques can reduce complexity at memory device 110-a by estimating access counts, sampling read accesses or write accesses over short intervals, and delegating at least some (e.g., a majority) of hot map processing to host device 105-a. Such techniques can also enable host device 105-a to monitor access counts for a given address range with higher accuracy than tracking access counts entirely in software. In some examples, host device 105-a can maintain an ordering of memory pages across multiple memory devices 110 (e.g., memory device 110-a and other memory devices 110, not shown, which can include a mix of CXL memory devices and non-CXL memory devices). That is, host device 105-a can generate a list of pages sorted by access count across multiple memory devices 110. Because memory device 110-a can track each access operation or access operations per cycle, the accuracy of register 305, and thus register 365, can be improved. Furthermore, by supporting configuration of register 305 by one or more indications, such techniques can also enable host device 105-a to manage aspects such as counter saturation, hot map accuracy, and other characteristics, which can include various adaptations in response to various operating conditions.

[0068] Figure 4 An example of a process flow 400 that supports access hot map generation at a memory device in accordance with examples disclosed herein is shown. Operations of process flow 400 can be performed by one or more host devices 105 (e.g., host device 105-b, host device 105-c, or both) and one or more memory devices 110 (e.g., memory device 110-b, memory device 110-c, or both), which can be the host devices 105 and memory devices 110 referred to with reference to Figures 1-3Examples of respective apparatuses are described. Aspects of process flow 400 can be implemented by one or more controllers (e.g., one or more respective controllers at host device 105 or memory device 110) and other components. Additionally or alternatively, aspects of process flow 400 can be implemented as instructions stored in memory (e.g., stored in memory of host device 105 or memory device 110 or respective firmware coupled with the host device or memory device). For example, the instructions, when executed by a controller, can cause the controller to perform one or more operations of process flow 400. In some cases, one or more host devices 105 and memory devices 110 can communicate with each other via interface 415 (e.g., a CXL interface, one or more channels 115).

[0069] At 420, in some examples, host device 105-b can select parameters for monitoring access commands (e.g., at memory device 110-b, at memory device 110-c, or both). For example, host device 105-b can determine a threshold for recently accessed pages (e.g., a threshold for access counts to add an identifier 325 to register 345), a number of recently accessed pages to monitor (e.g., at register 345), a type of access operations to monitor (e.g., read operations, write operations, or both), a set of addresses to monitor (e.g., a range of addresses corresponding to a set of pages), whether to monitor pre-cache operations or post-cache operations, or any combination thereof.

[0070] At 425, in some examples, host device 105-b can transmit a command to initiate monitoring access operations at memory device 110-b, which can be received by memory device 110-b. In some cases, the command can include an indication of one or more parameters selected at 420. Accordingly, memory device 110-b can initiate monitoring access commands for a set of pages indicated in the first command. For example, memory device 110-b can allocate a first register with a first set of fields (e.g., register 305 with fields 310), or a second register with a second set of fields (e.g., register 345 with fields 350), or both. In some examples, host device 105-b can send a similar command to memory device 110-c, which can include similar parameters or different parameters.

[0071] At 430, host device 105-b can transmit one or more commands (e.g., read commands, write commands, or both) to access memory device 110-b. Based on receiving the access commands at 430 (e.g., based on accessing the corresponding addresses), memory device 110-b can update the first register, the second register, or both, at 440. For example, memory device 110-b can input each identifier 325 associated with an address included in the access commands to a set of mapping functions 330 to determine a corresponding set of fields 310, and can increase the value of each field 310 of the corresponding set. In some examples, at 435, host device 105-c can transmit one or more commands to access memory device 110-b, which can also be responded to by memory device 110-b updating the first register (e.g., at 440).

[0072] In some examples, at 440, memory device 110-b can update the second register. For example, for each address (e.g., each identifier 325) associated with the access commands of 430, 435, or both, memory device 110-b can determine an estimated access count (e.g., by selecting the minimum value of the set of fields 310 corresponding to the identifier 325) and compare the estimated access count to a threshold (e.g., a threshold included in the set of parameters of the monitoring command of 425). If the estimated access count exceeds the threshold, memory device 110-b can add the identifier 425 to the second register (e.g., according to a first-in-first-out policy). In various examples, any of the operations of 430, 435, or 440 can be repeated any number of one or more times (e.g., within a monitoring interval).

[0073] At 445, host device 105-b can transmit a request for retrieving information about access operation monitoring, which can be received by memory device 110-b. In response to the request, at 450, memory device 110-b can transmit information associated with the monitoring (e.g., associated with a monitoring interval as monitored between receiving the monitoring command of 425 and the information request of 445), which can be received by host device 105-b. For example, memory device 110-b can transmit an indication of the first register, an indication of a number of fields of the first register, an indication of a total number of access operations (e.g., a sum of the values of the fields of the first register), an indication of the second register, an indication of a sampling ratio, or any combination thereof.

[0074] In some cases, the request of 445 can include a request to retrieve access operation information for a specified set of pages (e.g., a subset of the monitored set of pages). For example, the request of 445 can include an indication of the set of identifiers 325. In accordance with this request, the memory device 110-b can determine an estimated access count for each page corresponding to the set of identifiers 325 (e.g., by selecting the minimum value of the set of fields corresponding to each page), and at 450, the memory device 110-b can transmit an indication of the estimated access counts to the host device 105-b.

[0075] In some examples, in response to transmitting information at 450, the memory device 110-b can reset the first register, the second register, or both the first register and the second register at 455. For example, the memory device 110-b can set the values of the fields of the first register to an initial value (e.g., zero). Additionally or alternatively, the memory device 110-b can initialize the fields of the second register, for example, by removing identifiers from the fields of the second register.

[0076] At 460, the host device 105-b can process the information received at 450. For example, the host device 105-b can determine access operation counts for selected addresses of the set of monitored addresses (e.g., by selecting the minimum value of the set of fields 310 for the selected addresses, as applicable). In some cases, at 465, the host device 105-b can perform one or more operations based on the information of 460. In some examples, such operations can be configured to improve allocation of memory resources by the host device 105-b, for example, to migrate data to improve matching between data characteristics and memory characteristics (e.g., to allocate relatively higher levels of memory to relatively frequently accessed data, to allocate relatively lower levels of memory to relatively infrequently accessed data).

[0077] In some examples, the host device 105-b can divide a range of consecutive addresses (e.g., a set of pages having consecutive logical addresses) into one or more zones, which can refer to zones of the memory device 110-b, or zones of the memory device 110-b and one or more other memory devices 110 (e.g., a memory device 110-c), among other configurations. In some examples, it can be assumed that addresses within a zone have similar access patterns, such that the host device 105-b can generalize information for addresses of a selected zone to the entire zone. For example, it can be sufficient to monitor access operations for a random address within a zone. Thus, the host device 105-b can determine access operation information for each address of a zone by determining access operation information for selected addresses from each zone, for example, by transmitting an indication of the access operation information for the selected addresses.

[0078] In some such examples, each of the plurality of memory devices 110 can provide heat map information to the host device 105-b (e.g., access counts, metadata related to interpreting access counts), and the host device 105-b can look up the access counts for each address of interest and extrapolate the access counts for all addresses of interest. An alternative to reading the entire register 305 can include the host device 105-b querying each memory device 110 for a list of addresses and obtaining the access counts for the specified addresses. In some examples, such techniques can support the host device 105-b more accurately monitoring and ordering cold data (e.g., cold pages) to proactively reclaim the right candidate addresses and improve application performance, which can be more precise than the implementation of the host device 105-c tracking the page table entry bits in each sampling interval. In some examples, such techniques can improve efficiency by avoiding kernel page table scans, which can be computationally costly.

[0079] Additionally or alternatively, the host device 105-b can be implemented in a memory tiering management system that identifies memory hierarchies (e.g., performance hierarchies, latency hierarchies, throughput hierarchies, cost hierarchies, or other performance descriptions between memory regions). For example, the host device 105-b can be coupled with memory devices 110 including relatively fast DRAM storage devices and relatively slow solid state drive (SSD) storage devices, and the host device 105-b can use the information of 450 to perform migration or offload evaluation. In some examples, the host device 105-b can maintain a plurality of address lists, such as including a first list of addresses (e.g., pages) associated with active processes (e.g., active applications being run by the host device 105-b, such as by a processor 125) and a second list including free or unused addresses. The host device 105-b can obtain access operation information for the addresses of the first and second lists (e.g., by querying the memory devices 110-b or using the information received at 450), and can order or rank the addresses according to access counts.

[0080] In some instances, host device 105-b may transfer address-associated data based on access counts. For example, hot pages (e.g., active or inactive pages with relatively high access counts) of a first or second list may be transferred from the memory array of memory device 110-b to faster local memory (e.g., a cache), while cold pages (e.g., inactive pages with relatively low access counts) of a second list may be transferred from the memory array of memory device 110-b to a separate storage device, such as a non-volatile memory device coupled to host device 105-b (e.g., memory device 110-c). Therefore, at 470, host device 105-b can transmit a command to memory device 110-b to transfer page-associated data based on access counts from memory device 110-b. In various instances, this transfer may refer to a transfer between memory arrays of memory device 110-b, or a transfer between memory device 110-b and another memory device 110 (e.g., memory device 110-c, which may contain a relatively higher or lower level of memory than memory device 110-b). In some instances, in response to receiving the command at 470, memory device 110-b may transfer data to memory device 110-c at 475. In some instances, the relatively finer-grained monitoring provided by such techniques can support more accurate sorting of hot or cold data in the active and inactive kernel Least Recently Used (LRU) lists, which can support more efficient memory offloading or migration assessments than other techniques.

[0081] Figure 5 An example block diagram 500 of a memory device 520, generated according to an example disclosed herein, supports access heatmap generation at a memory device. The memory device 520 may be used as a reference. Figures 1-4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of components for performing various aspects of access heatmap generation at the memory device as described herein. For example, memory device 520 may include access operation component 525, register control component 530, receiving component 535, transmission component 540, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] The access operation component 525 can be configured as or otherwise support means for performing one or more access operations each associated with a respective address of a plurality of addresses of the memory device 520. The register control component 530 can be configured as or otherwise support means for modifying, in a register of the memory device 520 that includes a plurality of fields, for each access operation of the one or more access operations, a respective value of each field of a plurality of sets of the plurality of fields that is associated with the respective address. The receiving component 535 can be configured as or otherwise support means for receiving, from the host device, an information request associated with access operation occurrences at the memory device 520. The transmission component 540 can be configured as or otherwise support means for transmitting, to the host device, an indication of the respective value of at least one field of the plurality of fields based on the information request.

[0083] In some examples, each field of the plurality of fields of the register is associated with a respective set of a plurality of addresses.

[0084] In some examples, to support modifying the respective value of each field, the register control component 530 can be configured as or otherwise support means for modifying a value of a first field of the plurality of fields and a value of a second field of the plurality of fields based on an identifier of a first address associated with a first access operation of the one or more access operations. In some examples, to support modifying the respective value of each field, the register control component 530 can be configured as or otherwise support means for modifying a value of the first field of the plurality of fields and a value of a third field of the plurality of fields based on an identifier of a second address associated with a second access operation of the one or more access operations.

[0085] In some examples, a quantity of the plurality of fields of the register is less than a quantity of the plurality of addresses.

[0086] In some examples, the receiving component 535 can be configured as or otherwise support means for receiving a command to monitor access operation occurrences at the memory device 520 and can modify the respective value of each field based on the command.

[0087] In some examples, the command can include an indication of a quantity of fields of the register, an indication of a quantity of fields associated with each address of the plurality of addresses, an indication of a duration to monitor access operation occurrences, an indication of a range of addresses of the plurality of addresses, an indication of a periodicity to monitor access operation occurrences, or a combination thereof.

[0088] In some examples, the register control component 530 can be configured as or otherwise support means for determining that a minimum of the respective values of the plurality of sets of fields associated with the addresses for the plurality of addresses satisfies a threshold value. In some examples, the register control component 530 can be configured as or otherwise support means for writing an identifier of the address to a second field of a second register having a plurality of second fields.

[0089] In some examples, the receive component 535 can be configured as or otherwise support means for receiving a command including an indication of a number of second fields of a second register, an indication of a threshold value, or both, and can determine that the minimum satisfies the threshold value based on the command.

[0090] In some examples, the receive component 535 can be configured as or otherwise support means for receiving a second information request associated with an occurrence of an access operation at the memory device 520. In some examples, the transmit component 540 can be configured as or otherwise support means for transmitting an indication of a respective value of at least one second field of the plurality of second fields of the second register based on the second information request.

[0091] In some examples, the register control component 530 can be configured as or otherwise support means for resetting each field of the register and each second field of the second register based on receiving the information request or the second information request.

[0092] In some examples, to support writing the identifier of the address to the second field of the second register, the register control component 530 can be configured as or otherwise support means for writing the identifier of the address to the second field of the second register associated with an oldest value of the second register.

[0093] In some examples, the respective value of each field is modified based on the one or more access operations being performed as respective read operations, respective write operations, or a combination of respective read operations or write operations.

[0094] In some examples, the respective value of each field is modified based on the one or more access operations being performed as respective pre-cache operations.

[0095] In some examples, the respective value of each field is modified based on the one or more access operations being performed as respective post-cache operations.

[0096] In some examples, a first subset of the plurality of addresses is associated with a first memory die of the memory device 520, and a second subset of the plurality of addresses is associated with a second memory die of the memory device 520.

[0097] Figure 6 A flow diagram illustrating a method 600 that supports access heat map generation at a memory device in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a memory device or its components as described herein. For example, the operations of method 600 can be performed by a memory device as described with reference to Figs. 1-2 and 5A-5B by a processing circuitry 505 executing instructions 510 as stored in memory 515. Figures 1-5 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0098] At 605, the method can include performing, at the memory device, one or more access operations each associated with a respective address of a plurality of addresses of the memory device. The operations of 605 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 605 can be performed by an access operations component 525 as described with reference to Figs. 1-2 and 5A-5B. Figure 5

[0099] At 610, the method can include modifying, in a register of the memory device that includes a plurality of fields, for each access operation of the one or more access operations, a respective value of each field of a plurality of sets of fields of the plurality of fields that is associated with the respective address. The operations of 610 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 610 can be performed by a register control component 530 as described with reference to Figs. 1-2 and 5A-5B. Figure 5

[0100] At 615, the method can include receiving, from a host device, a request for information associated with access operation occurrences at the memory device. The operations of 615 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 615 can be performed by a receiving component 535 as described with reference to Figs. 1-2 and 5A-5B. Figure 5

[0101] At 620, the method can include transmitting, by the memory device to the host device based on the request for information, an indication of the respective value of at least one field of the plurality of fields. The operations of 620 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 620 can be performed by a transmitting component 540 as described with reference to Figs. 1-2 and 5A-5B. Figure 5

[0102] In some examples, an apparatus as described herein can perform one or more methods, such as method 600. An apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination of the following aspects of the disclosure for performing the following aspects of the disclosure:

[0103] ​​​​Aspect 1 : A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for performing, at a memory device, one or more access operations each associated with a respective address of a plurality of addresses of the memory device; modifying, in a register of the memory device that includes a plurality of fields, for each access operation of the one or more access operations, a respective value of each field of a plurality of sets of fields of the plurality of fields that is associated with the respective address; receiving, from a host device, an information request associated with access operation occurrences at the memory device; and transmitting, by the memory device to the host device based on the information request, an indication of the respective value of at least one field of the plurality of fields.

[0104] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, wherein each field of the plurality of fields of the register is associated with a respective set of addresses of the plurality of addresses.

[0105] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 -2, wherein modifying the respective value of each field includes operations, features, circuitry, logic, means, or instructions, or any combination thereof, for modifying a value of a first field of the plurality of fields and a value of a second field of the plurality of fields based on an identifier of a first address associated with a first access operation of the one or more access operations; and modifying the value of the first field of the plurality of fields and a value of a third field of the plurality of fields based on an identifier of a second address associated with a second access operation of the one or more access operations.

[0106] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 -3, wherein a number of the plurality of fields of the register is less than a number of the plurality of addresses.

[0107] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 -4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for receiving a command to monitor access operation occurrences at the memory device, wherein modifying the respective value of each field is based on the command.

[0108] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of Aspect 5, wherein the command includes an indication of a number of fields of the register, an indication of a number of fields associated with each address of the plurality of addresses, an indication of a duration to monitor access operation occurrences, an indication of a range of addresses of the plurality of addresses, an indication of a periodicity to monitor access operation occurrences, or a combination thereof.

[0109] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining, for an address of the plurality of addresses, that a minimum of the respective values of the plurality of sets of fields associated with the address satisfies the threshold; and writing an identifier of the address to a second field of a second register having a plurality of second fields.

[0110] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of aspect 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving a command including an indication of a number of the second fields of the second register, an indication of the threshold, or both, and determining that the minimum satisfies the threshold based on the command.

[0111] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7-8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving a second information request associated with an access operation occurrence at the memory device, transmitting an indication of a respective value of at least one second field of the plurality of second fields of the second register based on the second information request.

[0112] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of aspect 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for resetting each field of the register and each second field of the second register based on receiving the second information request.

[0113] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7-10, wherein writing the identifier of the address to the second field of the second register includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for writing the identifier of the address to a second field of the second register associated with an oldest value of the second register.

[0114] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-11, wherein the respective value of each field is modified based on the one or more access operations being performed as respective read operations, respective write operations, or a combination of read operations or write operations.

[0115] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-12, wherein the respective value of each field is modified based on the one or more access operations being performed as respective pre-cache operations.

[0116] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-13, wherein respective values of each field are modified based on the one or more access operations being performed as respective post-cache operations.

[0117] Aspect 15: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-14, wherein a first subset of the plurality of addresses is associated with a first memory die of the memory device and a second subset of the plurality of addresses is associated with a second memory die of the memory device.

[0118] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, features from two or more of the methods can be combined.

[0119] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it is to be understood that the signal can be represented

[0120] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or of a sub-region of the substrate, can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0121] The switching components (e.g., transistors) discussed herein can represent field effect transistors (FETs) and can include three-terminal components that include a source (e.g., source terminal), a drain (e.g., drain terminal), and a gate (e.g., gate terminal). The terminals can be connected to other electronic components by conductive material (e.g., metal, alloy). The source and drain can be conductive and can include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain can be separated by a channel of doped (e.g., lightly doped) semiconductor or a channel. If the channel is n-type (e.g., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (e.g., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to have conductivity. A transistor can be“turned on” or“activated” when a voltage greater than or equal to the transistor’s threshold voltage is applied to the transistor gate. A transistor can be“turned off’ or“deactivated” when a voltage less than the transistor’s threshold voltage is applied to the transistor gate.

[0122] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term“exemplary” used herein means“serving as an example, instance, or illustration,” and not “preferred” over other instances. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0123] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by adding a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0124] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0125] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a processor, such as a DSP, an ASIC, an FPGA, discrete circuitry, discrete logic, discrete hardware components, or other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0126] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0127] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a computer or processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0128] The description herein is presented to enable a person of ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method at a memory device, comprising: Perform one or more access operations at the memory device, each associated with a corresponding address among a plurality of addresses of the memory device; In a register comprising multiple fields in the memory device, for each of the one or more access operations, the value of each field in a set of multiple fields associated with the corresponding address is modified, wherein each of the multiple fields of the register is associated with a corresponding set of multiple addresses. Receive an information request associated with an access operation occurring at the memory device; as well as An indication from the memory device to transmit the corresponding value of at least one of the plurality of fields based on the information request.

2. The method of claim 1, wherein modifying the corresponding value of each field comprises: Based on the identifier of the first address associated with the first access operation in the one or more access operations, modify the value of the first field and the value of the second field in the plurality of fields; as well as Based on the identifier of the second address associated with the second access operation in the one or more access operations, the value of the first field and the value of the third field in the plurality of fields are modified.

3. The method of claim 1, wherein the number of the plurality of fields of the register is less than the number of the plurality of addresses.

4. The method of claim 1, further comprising: Receive a command to monitor the occurrence of access operations at the memory device, wherein the corresponding value of each field is modified based on the command.

5. The method of claim 4, wherein the command includes an indication of the number of fields in the register, an indication of the number of fields associated with each of the plurality of addresses, an indication of the duration of a monitoring access operation, an indication of the address range of the plurality of addresses, an indication of the periodicity of a monitoring access operation, or a combination thereof.

6. The method of claim 1, further comprising: For one of the plurality of addresses, determine the minimum value among the corresponding values ​​of the plurality of field sets associated with the address that satisfies the threshold. as well as Write the identifier of the address into the second field of the second register, which has multiple second fields.

7. The method of claim 6, further comprising: Receives an indication of the number of a second field in the second register, an indication of the threshold, or both, wherein the minimum value is determined to satisfy the threshold based on the command.

8. The method of claim 6, further comprising: Receive a second information request associated with an access operation occurring at the memory device; as well as Based on the second information request, an indication is given of the corresponding value of at least one of the plurality of second fields of the second register.

9. The method of claim 8, further comprising: Based on receiving the second information request, reset each field of the register and each second field of the second register.

10. The method of claim 6, wherein writing the identifier of the address into the second field of the second register comprises: Write the identifier of the address into the second field of the second register that is associated with the oldest value of the second register.

11. The method of claim 1, wherein the corresponding value of each field is modified based on performing the one or more access operations as a corresponding read operation, a corresponding write operation, or a combination of a corresponding read operation or a write operation.

12. The method of claim 1, wherein the corresponding value of each field is modified based on performing the one or more access operations as corresponding pre-cached operations.

13. The method of claim 1, wherein the corresponding value of each field is modified based on performing the one or more access operations as corresponding post-caching operations.

14. The method of claim 1, wherein a first subset of the plurality of addresses is associated with a first memory die of the memory device, and a second subset of the plurality of addresses is associated with a second memory die of the memory device.

15. A memory device comprising: One or more memory arrays; as well as One or more controllers coupled to the one or more memory arrays and configured to cause the memory device to: Each of the following operations is performed, each associated with a corresponding address among a plurality of addresses of the memory device; In a register comprising multiple fields, for each of the one or more access operations, the value of each field in a set of multiple fields associated with the corresponding address is modified, wherein each of the multiple fields of the register is associated with a corresponding set of multiple addresses. Receive an information request associated with an access operation occurring at the memory device; as well as Based on the information request, an indication is sent to transmit the corresponding value of at least one of the plurality of fields.

16. The memory device of claim 15, wherein, in order to modify the corresponding value of each field, the one or more controllers are configured to cause the memory device to: Based on the identifier of the first address associated with the first access operation in the one or more access operations, modify the value of the first field and the value of the second field among the plurality of fields; and Based on the identifier of the second address associated with the second access operation in the one or more access operations, the value of the first field and the value of the third field in the plurality of fields are modified.

17. The memory device of claim 15, wherein the one or more controllers are further configured to cause the memory device to: Receive a command to monitor the occurrence of access operations at the memory device, wherein the corresponding value of each field is modified based on the command.

18. The memory device of claim 15, wherein the one or more controllers are further configured to cause the memory device to: For one of the plurality of addresses, determine the minimum value among the corresponding values ​​of the plurality of field sets associated with that address that satisfies a threshold; and Write the identifier of the address into the second field of the second register, which has multiple second fields.

19. The memory device of claim 18, wherein the one or more controllers are further configured to cause the memory device to: Receive a second information request associated with an access operation occurring at the memory device; and Based on receiving the second information request, an indication is given to transmit the corresponding value of at least one of the plurality of second fields of the second register.

20. The memory device of claim 19, wherein the one or more controllers are further configured to cause the memory device to: Based on receiving the second information request, reset each field of the register and each second field of the second register.

21. The memory device according to claim 18, wherein, To write the identifier of the address into the second field of the second register, the one or more controllers are configured to cause the memory device to: Write the identifier of the address into the second field of the second register that is associated with the oldest value of the second register.

22. The memory device of claim 15, wherein the corresponding value of each field is modified based on performing the one or more access operations as a corresponding read operation, a corresponding write operation, or a combination of a corresponding read operation or a write operation.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: Each of the following operations is associated with a corresponding address among a plurality of addresses in the memory device; In a register comprising multiple fields in the memory device, for each of the one or more access operations, the value of each field in a set of multiple fields associated with the corresponding address is modified, wherein each of the multiple fields of the register is associated with a corresponding set of multiple addresses. Receive an information request associated with an access operation occurring at the memory device; as well as An indication from the memory device to transmit the corresponding value of at least one of the plurality of fields based on the information request.

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