A multilayer PCB structure for improving the pad impedance of copper traces

Abstract

The application discloses a multilayer PCB structure for improving the pad impedance of copper wires, which comprises three or more wiring layers and dielectric layers between the adjacent upper and lower wiring layers, wherein the topmost wiring layer is provided with a pad of copper wires for connecting transmission lines, and at least one wiring layer below the bottommost wiring layer is provided with a counter pad corresponding to the pad of the topmost wiring layer, characterized in that the dielectric layer below the wiring layer provided with the counter pad is provided with an array of dielectric holes located in the projection area of the counter pad above, and the dielectric holes are filled with a low dielectric constant filler, and the dielectric constant of the low dielectric constant filler is smaller than that of the dielectric layer. The structure of the application does not need to reduce the size of the pad or enlarge the pad spacing and the area of the counter pad to occupy more PCB area, so as to obtain good pad impedance matching of the copper wires, make the pad impedance of the copper wires closer to the impedance of the transmission lines, and improve various signal integrity problems caused by reflection.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of multilayer PCB structure for improving the pad impedance of copper wire. BACKGROUND

[0002] In the high-density layout of the current electronic industry field, the structure design of multilayer PCB (Printed Circuit Board), especially in the structure design of multilayer PCB applied to high-speed communication transmission module, since copper wire often needs to be connected with transmission line (also called signal line), at least one copper wire pad (copper wire is usually connected by soldering) is set on the top layer of the wiring layer of multilayer PCB for connecting transmission line.

[0003] But in actual operation, to ensure the reliability of connection, the above-mentioned copper wire pad is generally wide, and is often larger than the width of the transmission line itself, plus soldering, dispensing and other factors. This results in that the impedance at the copper wire pad is much lower than the impedance of the normal transmission line when referring to the same ground layer, and the problem of impedance mismatch is inevitable, which further causes serious reflection on the link and greatly affects the stable transmission of the signal.

[0004] In view of the above problems, the conventional optimization method is usually to reduce the size of the pad, increase the pad spacing, increase the area of the counter-pad on the adjacent wiring layer or adjacent and spaced wiring layer, etc., but there are some limitations, such as too small pad size will greatly increase the process difficulty of PCB and copper wire welding, and reduce the connection reliability. And blindly increasing the pad spacing, or expanding the area of the counter-pad on the adjacent wiring layer or adjacent and spaced wiring layer will excessively occupy the effective wiring area of the PCB, resulting in a great reduction in the actual wiring area and structural strength, and thus it is not worth the loss.

[0005] Specifically, the patent for invention with the authorized announcement number 205408280U discloses a copper wire pad impedance matching PCB structure, by setting a groove through the vertical projection of the pad in the first reference ground layer below the wiring layer where the copper wire and the pad are located, which is essentially setting a counter-pad.

[0006] For example, the patent for invention with the authorized announcement number 206559719U, a PCB board structure for increasing the area impedance of surface-mounted pad, its improvement feature is to set a hollow area with the same size as the pad on the signal layer adjacent to the pad, or even set a spaced layer hollow area, which is essentially also to set a counter-pad to increase the impedance of the pad area and reduce the signal integrity problem caused by impedance mismatch.

[0007] But obviously, as we have analyzed before, due to the fact that the pad pitch and the anti-pad area will be greatly limited under the current PCB production environment of increasingly high speed and high density wiring design, in the multi-layer PCB structure design, in order to improve the pad impedance, it cannot excessively rely on the single way of expanding the anti-pad area as in the prior art.

[0008] Based on this, we propose a new multi-layer PCB structure to improve the pad impedance of the copper wire, which does not need to reduce the pad size or expand the pad pitch and the anti-pad area to occupy more PCB area. SUMMARY

[0009] The purpose of the present application is to overcome the above problems existing in the prior art, and to provide a multi-layer PCB structure for improving the pad impedance of the copper wire, which does not need to reduce the pad size or expand the pad pitch and the anti-pad area to occupy more PCB area, so as to obtain good pad impedance matching of the copper wire, make it closer to the impedance of the transmission line, and improve various signal integrity problems caused by reflection.

[0010] The technical scheme of the present application is: a multi-layer PCB structure for improving the pad impedance of the copper wire, comprising three or more wiring layers and a dielectric layer located between the upper and lower adjacent wiring layers, wherein the topmost wiring layer is provided with a pad of the copper wire to connect the transmission line, and at least one wiring layer below the bottommost wiring layer is provided with an anti-pad corresponding to the pad of the topmost wiring layer, characterized in that the dielectric layer below the wiring layer provided with the anti-pad is provided with an array of dielectric holes located in the projection area of the anti-pad above, and the dielectric holes are filled with a low dielectric constant filler, and the dielectric constant of the low dielectric constant filler is less than the dielectric constant of the dielectric layer.

[0011] Further, the diameter of the dielectric hole in the array of dielectric holes in the present application is not less than 4 mil, and not less than 1.25 times the thickness of the thickest dielectric layer.

[0012] Further, the sum of the projection areas of all dielectric holes in the array of dielectric holes in the present application is not less than 0.5 times the area of the corresponding anti-pad projection area.

[0013] The lower the dielectric constant of the low dielectric constant filler in the dielectric hole compared to the dielectric constant of the material selected for the dielectric layer, the better the effect of reducing the equivalent dielectric constant of the medium between the pad of the surface copper wire and the wiring layer not provided with the anti-pad (i.e. the reference ground layer), and the better the effect of ultimately improving the pad impedance of the copper wire. For this reason, we have prepared a table of commonly used low dielectric constant fillers in the industry as follows:

[0014] Low dielectric constant fillers Relative dielectric constant @ 1 GHz Description FR4 4.0 Common PCB board material Panasonic Megatron 6 3.4 Common PCB board material Arlon AD250C 2.5 High frequency low dielectric constant board material Rogers RT / duroid 5880 2.2 High frequency low dielectric constant board material Teflon 2.1 High frequency low dielectric constant board material Air 1.0 Minimum dielectric constant

[0015] From the above table we can see that, in the premise of ensuring the strength of the medium layer structure, air has the smallest dielectric constant, so it is the optimal low dielectric constant filler choice. Of course, in actual implementation, according to the plate material of the medium layer, in order to balance its structural strength, we can also choose other low dielectric constant plate materials to implement the filling.

[0016] It should be noted that, as a common industry knowledge, in the PCB process, when the medium layer is laminated, the anti-pad area on the wiring layer will be squeezed and filled before the medium flows and solidifies, so the medium hole array punched on the medium layer is through the anti-pad; especially when the medium hole array is needed on both adjacent two medium layers, the medium holes of the two are connected through the anti-pad of the middle wiring layer.

[0017] Further, the topmost wiring layer in the present application is provided with a signal channel composed of a single solder pad, and / or a signal channel composed of a signal pair composed of two solder pads, and the projection area of the anti-pad corresponding to the solder pad of the signal pair on the topmost layer covers the two solder pads of the signal pair.

[0018] The advantages of the technical scheme of the present application are as follows:

[0019] 1. The present application further reduces the equivalent dielectric constant of the medium between the solder pad of the surface wiring layer copper line and the reference ground layer by setting the medium hole array corresponding to the projection area of the upper anti-pad on the medium layer adjacent to the wiring layer below the anti-pad and filling the low dielectric constant filler with a relative dielectric constant smaller than that of the medium layer in the medium hole, thereby further improving the solder pad impedance of the copper line based on the traditional increase of the solder pad impedance of the copper line through the anti-pad, making it closer to the impedance of the transmission line, improving various signal integrity problems caused by reflection, and improving the PCB signal transmission quality.

[0020] 2. The biggest feature of the present application is that it can obtain good solder pad impedance matching of the copper line without reducing the solder pad size or enlarging the solder pad spacing and anti-pad area to occupy more PCB area. Compared with the known PCB which only relies on enlarging the anti-pad area to increase the solder pad impedance of the copper line, it does not need to further occupy the effective wiring area of the PCB, so it is especially suitable for the design environment requirements of the current PCB production with increasing speed and high density wiring. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of the layer structure of a specific embodiment of the present application;

[0022] Figure 2 is Figure 1 a schematic diagram of the layer structure of a specific embodiment of the present application;

[0023] Figure 3 is adopted Figure 1 The differential signal pad impedance comparison chart of the PCB with the structure, the traditional optimized PCB (only the anti-pad is reserved without the medium hole array) and the unoptimized initial PCB (neither the anti-pad nor the medium hole array is set, the structure of the pad and the transmission line reference the same reference ground layer).

[0024] 1, transmission line; 2, pad; 3, anti-pad; 4, medium hole; 5, first wiring layer; 6, second wiring layer; 7, third wiring layer; 8, fourth wiring layer; 9, fifth wiring layer; 10, first medium layer; 11, second medium layer; 12, third medium layer; 13, fourth medium layer. DETAILED DESCRIPTION

[0025] Embodiment: The specific embodiment of the multi-layer PCB structure provided by the present application for improving the pad impedance of the copper line is described as follows in combination with Figures 1-3

[0026] In this embodiment, the structure is specifically applied to a five-layer PCB, which is formed by alternately stacking five independent wiring layers and four medium layers. For the convenience of description, we name the five wiring layers from top to bottom as the first wiring layer 5, the second wiring layer 6, the third wiring layer 7, the fourth wiring layer 8 and the fifth wiring layer 9, wherein the first wiring layer 5 is the topmost wiring layer (i.e. the surface wiring layer), and the fifth wiring layer 9 is the bottommost wiring layer. The copper line (the pad 2 in the copper line is omitted in the drawings, which is connected with the pad 2 by soldering) is connected with the pad 2 on the first wiring layer 5 to connect the transmission line 1, and as shown in Figure 1 Figure 2 , the two parallel and spaced pads 2 in this embodiment serve as a signal pair, which are respectively led out through the transmission line 1, and the specification of each pad 2 is 2.0*0.6mm, and the center distance between the two pads 2 is 1.0mm. Figure 2

[0027] Similarly, we name the four medium layers from top to bottom as the first medium layer 10, the second medium layer 11, the third medium layer 12 and the fourth medium layer 13. In the above-mentioned PCB, the anti-pads 3 corresponding to the topmost pads 2 are arranged on the second wiring layer 6, the third wiring layer 7 and the fourth wiring layer 8 (the projection area of the anti-pad 3 on the first wiring layer 5 covers the two pads 2 of the signal pair), and the specification of each anti-pad 3 is consistent, which is 2.25*1.85mm. The medium holes 4 array located in the projection area of the anti-pad 3 above are arranged on the medium layers adjacent to the above-mentioned wiring layers, i.e. the second medium layer 11, the third medium layer 12 and the fourth medium layer 13, and the medium holes 4 are filled with a low dielectric constant filler, and the dielectric constant of the low dielectric constant filler is less than the dielectric constant of the medium layer where the low dielectric constant filler is located. ​​​

[0028] Furthermore, it should be noted that, as is common knowledge in the industry, during PCB manufacturing, when the dielectric layer is laminated, it will be squeezed into and fill the anti-pad 3 area on each wiring layer before the dielectric flows and solidifies. Therefore, the dielectric vias 4 punched on the second dielectric layer 11, the third dielectric layer 12, and the fourth dielectric layer 13 are all interconnected through the anti-pad 3 between them, as detailed below. Figure 1 As shown.

[0029] In this embodiment, the five-layer PCB uses copper for the wiring layers and Panasonic Megatron 6 substrate for the dielectric layers, which has a relative permittivity of 3.4 at 1 GHz. The thicknesses of each layer are as follows:

[0030] The thickness of the first wiring layer 5 is 1.57mil (0.040mm), the thickness of the first dielectric layer 10 is 2.51mil (0.064mm), the thickness of the second wiring layer 6 is 1.38mil (0.035mm), the thickness of the second dielectric layer 11 is 2.86mil (0.073mm), the thickness of the third wiring layer 7 is 1.50mil (0.038mm), the thickness of the third dielectric layer 12 is 4.99mil (0.127mm), the thickness of the fourth wiring layer 8 is 0.59mil (0.015mm), the thickness of the fourth dielectric layer 13 is 2.01mil (0.051mm), and the thickness of the fifth wiring layer 9 is 0.59mil (0.015mm).

[0031] In this embodiment, the above-mentioned dielectric aperture 4 array is a rectangular array with uniform spacing of 9 rows and 11 columns. Figure 2 The dielectric via array shown is for illustrative purposes only and is not strictly drawn according to a 9×11 scale. There are a total of 99 dielectric vias 4. Each dielectric via 4 has a diameter of 7 mil (0.1778 mm), which is greater than 4 mil and greater than the thickness of the thickest third dielectric layer 12 (4.99 mil × 1.25 = 6.2375 mil (0.1584 mm). Furthermore, the sum of the projected areas of the dielectric vias 4 within the array is 2.45 mm². 2 It is greater than 0.5 times the projected area of ​​the anti-solder pad 3, which is 2.08 mm. 2 The low-dielectric-constant filler in dielectric hole 4 is air, with a relative permittivity of 1@1GHz, which is much smaller than the relative permittivity of the substrate material of the dielectric layer, 3.4@1GHz.

[0032] Figure 3 This indicates the adoption Figure 1The comparison chart of the differential signal pad impedance of the PCB with the structure of the present application, the traditional optimized PCB (only the anti-pad is reserved without the medium hole array) and the initial PCB without optimization (neither the anti-pad nor the medium hole array is made, and the pad and the transmission line refer to the same reference ground layer). The curve where m3 is located is the differential signal pad impedance curve of the PCB with the structure of the present application, wherein the point m3 represents the pad; the curve where m2 is located is the differential signal pad impedance curve of the traditional optimized PCB (only the anti-pad is reserved without the medium hole array), wherein the point m2 represents the pad; the curve where m1 is located is the differential signal pad impedance curve of the initial PCB without optimization (neither the anti-pad nor the medium hole array is made, and the pad and the transmission line refer to the same reference ground layer), wherein the point m1 also represents the pad.

[0033] From Figure 3 It can be seen that the impedance of the pad 2 of the copper line of the traditional optimized PCB is obviously improved compared with the initial PCB without optimization, and the impedance of the pad 2 of the PCB with the structure of the present application is further improved compared with the traditional optimized PCB. At about 120 ps, the impedance of the pad 2 is improved from 82.28 Ω to 88.66 Ω, and the improvement effect is very obvious.

[0034] Therefore, by arranging the medium hole array 4 corresponding to the projection area of the upper anti-pad 3 on the medium layer adjacent to the wiring layer below the anti-pad 3 and filling the low dielectric constant filler with a relative dielectric constant smaller than that of the medium layer in the medium hole 4, the equivalent dielectric constant of the medium between the pad 2 of the surface wiring layer copper line and the reference ground layer is further reduced, thereby further improving the impedance of the pad 2 of the copper line on the basis of the traditional increase of the impedance of the pad 2 of the copper line by the anti-pad 3, making it closer to the impedance of the transmission line 1, improving various signal integrity problems caused by reflection, and improving the PCB signal transmission quality.

[0035] Moreover, the greatest contribution of the structure of the present application to the PCB is that good pad impedance matching of the copper line can be achieved without reducing the size of the pad 2 or expanding the pad 2 spacing and the anti-pad 3 area to occupy more PCB area. Compared with the known PCB which only relies on expanding the anti-pad 3 area to increase the pad impedance of the copper line, the effective wiring area of the PCB is not further occupied, and therefore it is especially suitable for the design environment requirements of the current PCB production with increasing speed and high-density wiring.

[0036] Of course, the above is only a specific application example of the present application, and does not constitute any limitation on the protection scope of the present application. In addition to the above embodiments, the present application can also have other implementation manners. Any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of the present application.

Claims

1. A multilayer PCB structure for improving the pad impedance of a copper wire, comprising three or more wiring layers and a dielectric layer between the upper and lower adjacent wiring layers, wherein the topmost wiring layer is provided with a pad (2) of the copper wire for connecting a transmission line (1), and at least one wiring layer below the bottommost wiring layer is provided with a counter pad (3) corresponding to the pad (2) of the topmost wiring layer, characterized in that The lower dielectric layer adjacent to the wiring layer provided with the anti-pad (3) is provided with an array of dielectric holes (4) located in the projection area of the upper anti-pad (3), and the dielectric holes (4) are filled with a low dielectric constant filler, and the dielectric constant of the low dielectric constant filler is less than the dielectric constant of the dielectric layer.

2. The multi-layer PCB structure for improving the pad impedance of a copper trace according to claim 1, wherein, The aperture of the dielectric hole (4) in the array of dielectric holes (4) is not less than 4 mil, and not less than 1.25 times the thickness of the thickest dielectric layer.

3. The multi-layer PCB structure for improving the pad impedance of copper traces according to claim 1, wherein, The sum of the projection areas of all dielectric holes (4) in the array of dielectric holes (4) is not less than 0.5 times the area of the corresponding anti-pad (3) projection area.

4. The multi-layer PCB structure for improving the pad impedance of copper traces according to claim 1, wherein, The low dielectric constant filler is air.

5. The multilayer PCB structure for improving the pad impedance of a copper trace according to claim 1, wherein, The lower dielectric layer extrudes and fills the area of the upper anti-pad (3) so that the array of dielectric holes (4) passes through the anti-pad (3).

6. The multi-layer PCB structure for improving the pad impedance of copper traces according to claim 1 or 3, wherein, The topmost wiring layer is provided with a signal channel composed of a single solder pad (2), and / or a signal channel composed of a signal pair composed of two solder pads (2), and the projection area of the anti-pad (3) corresponding to the solder pads (2) of the signal pair covers the two solder pads (2) of the signal pair on the topmost layer.

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