Method for constructing overlay error model and overlay correction method

Abstract

The disclosure provides a method for constructing an overlay error model and a method for correcting overlay error, the method for correcting overlay error comprising: obtaining a first relative change rate a and a second relative change rate b, a first process margin M1 of a second film layer pattern relative to a first film layer pattern, a second process margin M2 of a third film layer pattern relative to the first film layer pattern, a third process margin M3 of the third film layer pattern relative to the second film layer pattern, initial values X0 and Y0 of a first overlay error and a second overlay error, and calculating an initial value Z0 of a third overlay error according to the X0 and Y0; obtaining a current value X1 of the first overlay error, and when X1≤M1, calculating a change amount DX1 of the first overlay error according to the X1 and X0; setting DZ1 equal to zero, determining a first expected change amount DY1 of the second overlay error according to the DX1, the a and the b; and when Y0+DY1≤M2, determining a correction value of a feedforward parameter corresponding to the second overlay error according to the DY1. The embodiment of the disclosure can correct the feedforward parameter of the overlay error in real time in a photolithography process.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and more specifically, to a method for constructing an overlay error model and a semiconductor device manufacturing method using the overlay correction method. Background Technology

[0002] In semiconductor memory technology, especially Dynamic Random Access Memory (DRAM), photolithography plays a crucial role in the patterning process. Overlay error (OVL), a key indicator in the photolithography process, is used to monitor the inline status of R&D / High Volume Manufacturing (HVM). By accurately measuring and calculating alignment / overlay marks, the actual overlay error between layers can be determined. Therefore, the immediacy and accuracy of overlay error feedback are critical to the manufacturing of semiconductor integrated circuits.

[0003] In related technologies, after a batch of wafers is manufactured, the overlay error of the next batch of wafers is usually corrected based on the measured overlay error of that batch. However, this feedback method is inefficient and it is difficult to remedy the overlay error of the batch of wafers before it is formed.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method for constructing an overlay error model and an overlay correction method, as well as a semiconductor device manufacturing method that applies the overlay correction method, to improve the problem of lag in the adjustment of overlay error feedforward parameters during integrated circuit manufacturing, thereby improving wafer yield.

[0006] According to a first aspect of this disclosure, a method for constructing an overlay error model is provided, comprising: acquiring first overlay error data of a second film pattern relative to a first film pattern and second overlay error data of a third film pattern relative to the first film pattern; calculating third overlay error data of the third film pattern relative to the second film pattern based on the second overlay error data and the first overlay error data; determining a first relative change ratio of the third overlay error to the first overlay error when the second overlay error remains unchanged, and a second relative change ratio of the third overlay error to the second overlay error when the first overlay error remains unchanged, based on the first overlay error data, the second overlay error data and the third overlay error data; and constructing an overlay error model as follows: DZ = DX*a + DY*b, where DX, DY, and DZ represent the change in the first overlay error, the change in the second overlay error, and the change in the third overlay error, respectively, and a and b represent the first relative change ratio and the second relative change ratio, respectively.

[0007] In an exemplary embodiment of this disclosure, determining a first relative change ratio between the third and first set-of errors when the second set-of error remains constant, and a second relative change ratio between the third and second set-of errors when the first set-of error remains constant, based on the first, second, and third set-of error data, includes: obtaining corresponding change data of the first, second, and third set-of errors based on the first, second, and third set-of error data and the first set-of error; fitting the change data of the first, second, and third set-of errors to synchronously obtain the first and second relative change ratios.

[0008] In an exemplary embodiment of this disclosure, determining a first relative change ratio between the third and first set-up errors when the second set-up error remains unchanged, and a second relative change ratio between the third and second set-up errors when the first set-up error remains unchanged, based on the first set-up error data, the second set-up error data, and the third set-up error data, includes: fitting the first and third set-up error data corresponding to the same second set-up error data to obtain the first relative change ratio; and fitting the second and third set-up error data corresponding to the same first set-up error data to obtain the second relative change ratio.

[0009] In one exemplary embodiment of this disclosure, the first set-in error, the second set-in error, and the third set-in error are all scalars or two-dimensional vectors.

[0010] In one exemplary embodiment of this disclosure, when the first overlay error, the second overlay error, and the third overlay error are all scalars, the first relative change ratio and the second relative change ratio are both scalars; when the first overlay error, the second overlay error, and the third overlay error are all two-dimensional vectors, the first relative change ratio and the second relative change ratio are both scalars or two-dimensional vectors.

[0011] According to a second aspect of this disclosure, an overlay correction method is provided, comprising: obtaining a first relative change rate a and a second relative change rate b determined according to the overlay error model construction method as described in any of the preceding claims; obtaining a first process allowance M1 of the second film pattern relative to the first film pattern, a second process allowance M2 of the third film pattern relative to the first film pattern, and a third process allowance M3 of the third film pattern relative to the second film pattern; obtaining an initial value X0 of the first overlay error and an initial value Y0 of the second overlay error, and calculating an initial value Z0 of the third overlay error based on the initial value X0 of the first overlay error and the initial value Y0 of the second overlay error, wherein X0 ≤ M1 Y0≤M2, Z0≤M3; Obtain the current value X1 of the first overlay error; When X1≤M1, calculate the change DX1 of the first overlay error based on the current value X1 and the initial value X0 of the first overlay error; Based on the change DX1 of the first overlay error, the first relative change rate a and the second relative change rate b, determine the first expected change DY1 of the second overlay error, wherein the expected change DZ1 of the third overlay error corresponding to the first expected change DY1 of the second overlay error is equal to zero; When Y0+DY1≤M2, determine the correction value of the feedforward parameter corresponding to the second overlay error based on the first expected change DY1 of the second overlay error.

[0012] In one exemplary embodiment of this disclosure, the method further includes: when Y0+DY1>M2, determining whether there exists a second expected change amount DY2 of the second overlay error based on the change amount DX1 of the first overlay error, the first relative change rate a, and the second relative change rate b, such that Y0+DY2≤M2 and Z0+DX1*a+DY2*b≤M3 are simultaneously true; if it exists, determining the correction value of the feedforward parameter corresponding to the second overlay error based on the second expected change amount DY2 of the second overlay error; if it does not exist, issuing a warning.

[0013] In an exemplary embodiment of the present disclosure, if there is a second expected change amount DY2 of the second overlay error, a correction value of the feedforward parameter corresponding to the second overlay error is determined according to the minimum value of the second expected change amount DY2 of the second overlay error.

[0014] In an exemplary embodiment of the present disclosure, M3 < M1 and M3 < M2.

[0015] In an exemplary embodiment of the present disclosure, both the first film layer pattern and the second film layer pattern are formed prior to the third film layer pattern.

[0016] In an exemplary embodiment of the present disclosure, the first film layer pattern is formed prior to the second film layer pattern; or, the second film layer pattern is formed prior to the first film layer pattern.

[0017] According to a third aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, including: forming a first film layer pattern and a second film layer pattern on a substrate using a lithography apparatus; correcting the feedforward parameter using a correction value of the feedforward parameter determined by the overlay correction method according to any one of the preceding items; and forming the third film layer pattern on the substrate using the lithography apparatus based on the corrected feedforward parameter.

[0018] In an exemplary embodiment of the present disclosure, the first film layer pattern and the second film layer pattern include overlay marks for measuring the first overlay error, the first film layer pattern and the third film layer pattern include overlay marks for measuring the second overlay error, and the second film layer pattern and the third film layer pattern do not include overlay marks for measuring the third overlay error.

[0019] In an exemplary embodiment of the present disclosure, the first film layer pattern includes an active layer, the second film layer pattern includes a buried word line layer, and the third film layer pattern includes a bit line contact structure layer.

[0020] According to a third aspect of the present disclosure, there is provided an electronic device, including: a memory; and a processor coupled to the memory, the processor being configured to execute the overlay correction method according to any one of the preceding items based on instructions stored in the memory.

[0021] According to a fourth aspect of the present disclosure, there is provided a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the overlay correction method according to any one of the preceding items is implemented.

[0022] This embodiment of the disclosure obtains the relative change ratio of overlay error between related film layers based on historical data. When the measured overlay error is obtained during the manufacturing process, the expected change amount of overlay error for each other film layer can be calculated based on the relationship between the related film layers. Thus, when manufacturing other film layers, the photolithography process feedforward parameters of the film layers that have not yet been manufactured can be adjusted according to the expected change amount, so as to realize the prediction and real-time adjustment of overlay error in the process, which helps to improve the yield of the batch of wafers.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 This is a flowchart of a method for constructing an overlay error model in an exemplary embodiment of this disclosure.

[0026] Figure 2 This is a schematic diagram of the overlay error relationship in one embodiment of this disclosure.

[0027] Figure 3 This is a flowchart of the overlay correction method provided in the embodiments of this disclosure.

[0028] Figure 4 This is a flowchart illustrating the determination of the correction value of the feedforward parameter corresponding to the second set of etching errors in one embodiment of this disclosure.

[0029] Figure 5 This is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this disclosure.

[0030] Figure 6 This is a schematic diagram of the film pattern and overlay error in one embodiment of this disclosure.

[0031] Figure 7 This is a schematic diagram illustrating the effect of the embodiments of this disclosure on the overlay marking tree.

[0032] Figure 8 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0034] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0036] In this embodiment of the disclosure, a relative relationship model of the overlay error between film layers can be established first.

[0037] Figure 1 This is a flowchart of a method for constructing an overlay error model in an exemplary embodiment of this disclosure.

[0038] refer to Figure 1 The method 100 for constructing the overlay error model may include:

[0039] Step S11: Obtain the first set of etching error data of the second film pattern relative to the first film pattern and the second set of etching error data of the third film pattern relative to the first film pattern.

[0040] Step S12: Calculate the third overlay error data of the third film pattern relative to the second film pattern based on the second overlay error data and the first overlay error data;

[0041] Step S13: Based on the first overlay error data, the second overlay error data, and the third overlay error data, determine the first relative change ratio of the third overlay error to the first overlay error when the second overlay error remains unchanged, and the second relative change ratio of the third overlay error to the second overlay error when the first overlay error remains unchanged.

[0042] Step S14, construct the overlay error model: DZ = DX*a + DY*b, where DX, DY, and DZ represent the change in the first overlay error, the change in the second overlay error, and the change in the third overlay error, respectively, and a and b represent the first relative change ratio and the second relative change ratio, respectively.

[0043] The following is combined Figure 2 right Figure 1 The method shown will be explained.

[0044] Figure 2 This is a schematic diagram of the overlay error relationship in one embodiment of this disclosure.

[0045] refer to Figure 2 The projections of the first film pattern 21, the second film pattern 22, and the third film pattern 23 are all arranged in the horizontal direction (i.e., the direction parallel to the surface of the wafer substrate). Each film pattern has an overlay mark corresponding to other benchmark film patterns. The overlay error between two film patterns can be calculated based on the corresponding overlay marks of the two film patterns.

[0046] It should be noted that, due to the layered processing characteristics of photolithography, the first film pattern 21, the second film pattern 22, and the third film pattern 23 may be located in different layers or in the same layer in the vertical direction (i.e., the direction perpendicular to the surface of the wafer substrate). However, the orthogonal projections of the overlay marks corresponding to the three film patterns on the wafer substrate are arranged in the horizontal direction. When calculating the overlay error, a two-dimensional coordinate system can be directly established based on the horizontal direction to obtain the two-dimensional coordinates of different overlay marks, and thus obtain the overlay error between different film layers.

[0047] like Figure 2 As shown, the first film pattern 21 has overlay marks 21A and 21B, the second film pattern 22 has overlay mark 22A, and the third film pattern 23 has overlay mark 23A. Each overlay mark has positioning coordinates, and the overlay marks in the same wafer use the same coordinate system to determine the positioning coordinates, such as a two-dimensional coordinate system established in the horizontal direction.

[0048] The overlay mark 22A of the second film pattern 22 corresponds to the overlay mark 21A of the first film pattern 21, and there is a first overlay error X (not shown) between 22A and 21A. The overlay mark 23A of the third film pattern 23 corresponds to the overlay mark 21B of the first film pattern 21, and there is a second overlay error Y (not shown) between 23A and 21B. However, due to limitations of wafer area / chip area and pre-designed overlay marks, there may not be an overlay mark between the third film pattern 23 and the second film pattern 22.

[0049] In this embodiment of the disclosure, in order to solve this problem, a third set of etching errors Z (not shown) between the third film pattern 23 and the second film pattern 22 is calculated based on the relative positional relationship between the film patterns, using the first set of etching errors X and the second set of etching errors Y.

[0050] In one embodiment, the first set of etching errors X, the second set of etching errors Y, and the third set of etching errors Z are all scalars or two-dimensional vectors. Taking X, Y, and Z as two-dimensional vectors as an example (e.g.) Figure 2 As shown), the following relationship can be obtained between vectors X, Y, and Z: Right now:

[0051]

[0052] Based on the batch historical manufacturing data of the wafers containing the first film pattern 21, the second film pattern 22, and the third film pattern 23, the historical data of the first set of etching errors X and the second set of etching errors Y can be obtained. Then, the historical data of the third set of etching errors Z can be obtained according to formula (1). Next, based on these historical data, the numerical variation correlation between the first set of etching errors X, the second set of etching errors Y, and the third set of etching errors Z can be obtained.

[0053] In step S23, based on the first set of etching error data, the second set of etching error data, and the third set of etching error data, the corresponding change data DX of the first set of etching error X, the change data DY of the second set of etching error Y, and the change data DZ of the third set of etching error Z can be obtained. Then, DX, DY, and DZ are fitted to simultaneously obtain the first relative change ratio a of the third set of etching error Z to the first set of etching error X when the second set of etching error Y remains unchanged, and the second relative change ratio b of the third set of etching error Z to the first set of etching error X when the first set of etching error X remains unchanged.

[0054] The process of obtaining DX, DY, and DZ can be achieved by calculating the differences between the measured and initial values ​​of the first set of etching errors X, the second set of etching errors Y, and the third set of etching errors Z for each (or batch) wafer. Each (or batch) wafer corresponds to a set of variations. Therefore, a fitting model can be established based on multiple sets of variation data from multiple (or batches) wafers, using the first relative variation ratio a and the second relative variation ratio b, and then constructing the following formula:

[0055] DZ=DX*a+DY*b (2)

[0056] Formula (2) represents the relative change relationship between the change data DX of the first set of etching error X, the change data DY of the second set of etching error Y, and the change data DZ of the third set of etching error Z.

[0057] In another embodiment, step S23 can also be performed by fitting the first and third sets of etching error data corresponding to the same second set of etching error data Y to obtain the first relative change ratio a; and by fitting the first and second sets of etching error data corresponding to the same first set of etching error data X to obtain the second relative change ratio b. That is, among multiple sets of etching error data (X, Y, Z), a set of etching error data (Xa, Y, Za), (Xb, Y, Zb), ... corresponding to a Y value can be found. Based on Xa, Za, Xb, Zb, ..., a correlation function Z = f(X) between the X value and the Z value can be established, and then the derivative can be used to obtain the first relative change ratio a between the change in Z DZ and the change in X DX. Similarly, among multiple sets of overlay error data (X, Y, Z), we can find overlay error data (X, Ya, Za), (X, Ya, Zb), ... corresponding to an X value. Based on Ya, Za, Yb, Zb, ..., we can establish a correlation function Z = g(Y) between the Y value and the Z value, and then differentiate it to obtain the second relative change ratio b between the change in Z DZ and the change in Y DY.

[0058] Alternatively, the first set of etching error data, the second set of etching error data, and the third set of etching error data can be directly fitted to establish the equation Z = f(X, Y), and the partial derivative can be obtained as DZ = a*DX + b*DY.

[0059] There are several other methods for obtaining the relative change ratio between changes based on historical data fitting, and those skilled in the art can choose the appropriate method based on the actual working conditions.

[0060] When the first set of etching errors X, the second set of etching errors Y, and the third set of etching errors Z are all scalars, the first relative change ratio a and the second relative change ratio b are both scalars; when the first set of etching errors X, the second set of etching errors Y, and the third set of etching errors Z are all two-dimensional vectors, the first relative change ratio a and the second relative change ratio b can both be scalars or two-dimensional vectors.

[0061] For example, when the overlay errors are all two-dimensional vectors in a coordinate system xoy established in the horizontal direction, the first relative change ratio a can include the change ratio ax in the x direction and the change ratio ay in the opposite y direction, and the second relative change ratio b can include the change ratio bx in the x direction and the change ratio by in the opposite y direction, thus:

[0062]

[0063] Wherein, DXx, DYx, and DZx are the changes in the x-direction of the first set of engraving errors X, the second set of engraving errors Y, and the third set of engraving errors Z, respectively, and DXy, DYy, and DZy are the changes in the y-direction of the first set of engraving errors X, the second set of engraving errors Y, and the third set of engraving errors Z, respectively.

[0064] By using Figure 1 The method shown calculates the first relative change ratio a and the second relative change ratio b, which can provide a data basis for real-time prediction of the expected change in overlay error in subsequent photolithography processes.

[0065] Figure 3 This is a flowchart of the overlay correction method provided in the embodiments of this disclosure.

[0066] refer to Figure 3 The overlay correction method 300 may include:

[0067] Step S31: Obtain the first relative rate of change a and the second relative rate of change b determined according to the construction method 100 of the overlay error model;

[0068] Step S32: Obtain the first process allowance M1 of the second film pattern relative to the first film pattern, the second process allowance M2 of the third film pattern relative to the first film pattern, and the third process allowance M3 of the third film pattern relative to the second film pattern.

[0069] Step S33: Obtain the initial value X0 of the first overlay error and the initial value Y0 of the second overlay error, and calculate the initial value Z0 of the third overlay error based on the initial value X0 of the first overlay error and the initial value Y0 of the second overlay error, wherein X0≤M1, Y0≤M2, Z0≤M3;

[0070] Step S34: Obtain the current value X1 of the first set of engraving errors;

[0071] Step S35: When X1≤M1, calculate the change DX1 of the first overlay error based on the current value X1 of the first overlay error and the initial value X0 of the first overlay error.

[0072] Step S36: Based on the change amount DX1 of the first overlay error, the first relative change rate a and the second relative change rate b, determine the first expected change amount DY1 of the second overlay error, wherein the expected change amount DZ1 of the third overlay error corresponding to the first expected change amount DY1 of the second overlay error is equal to zero.

[0073] Step S37: When Y0+DY1≤M2, determine the correction value of the feedforward parameter corresponding to the second set of etching errors based on the first expected change amount DY1 of the second set of etching errors.

[0074] Figure 3 The method shown is a way to determine the overlay error feedforward parameters of the unmanufactured film layer in real time. It can be understood that the feedforward parameters refer to various process / equipment parameters that can affect the overlay error of the second layer during the formation of the third mask layer, including but not limited to the alignment parameters of the mask and photolithography equipment.

[0075] exist Figure 3 In the illustrated embodiment, both the first and second film layer patterns are formed before the third film layer pattern. Specifically, the first film layer pattern is formed before the second film layer pattern; alternatively, the second film layer pattern may also be formed before the first film layer pattern. This disclosure does not limit the manufacturing order of the first and second film layer patterns.

[0076] The first process allowance M1 of the second film pattern relative to the first film pattern, the second process allowance M2 of the third film pattern relative to the first film pattern, and the third process allowance M3 of the third film pattern relative to the second film pattern are all system settings, representing the maximum allowable overlay error in the process. Overlay errors exceeding these process allowances are considered erroneous overlay errors and are determined to be uncompensable by adjusting the feedforward parameters of subsequent photolithography processes in real time.

[0077] Therefore, after the first and second film patterns are manufactured, and the current value X1 (i.e. the measured value) of the first overlay error is obtained in step S34, it is first determined whether X1 is less than or equal to the corresponding first process allowance M1. If so, the subsequent real-time adjustment process continues. If X1 > M1, it is determined that the overlay error is too large to be compensated, and a process warning is directly issued, or even the current wafer is deemed scrapped.

[0078] When the expected value of the second set of etching error Y1, i.e. Y1 = Y0 + DY1, is estimated in step S36, it is also necessary to immediately determine whether Y1 is less than or equal to the corresponding second process allowance M2. If so, the feedforward parameter corresponding to the second set of etching error Y is adjusted in real time according to the first expected change amount DY1, and the third film pattern is manufactured according to Y1 = Y0 + DY1, so that the first set of etching error of the third film pattern relative to the first film pattern is X1, and the second set of etching error of the third film pattern relative to the first film pattern is Y1. Even if the first set of etching error X deviates, the second set of etching error Y can be adjusted to Y1 within the second process allowance M2, so that the third set of etching error Z of the third film pattern relative to the second film pattern is not affected.

[0079] Figure 4 This is a flowchart illustrating the determination of the correction value of the feedforward parameter corresponding to the second set of etching errors in one embodiment of this disclosure.

[0080] Figure 4 The method shown continues Figure 3 Step S36 of the method shown.

[0081] refer to Figure 4 Step S36 is followed by:

[0082] Step S41: Determine whether Y0+DY1 is less than or equal to M2. If yes, proceed to step S37; otherwise, proceed to step S42.

[0083] In step S42, based on the change amount DX1 of the first overlay error, the first relative change rate a, and the second relative change rate b, it is determined whether there exists a second expected change amount DY2 of the second overlay error such that Y0+DY2≤M2 and Z0+DX1*a+DY2*b≤M3 are simultaneously true. If so, proceed to step S43, and determine the correction value of the feedforward parameter corresponding to the second overlay error based on the second expected change amount DY2 of the second overlay error. Otherwise, proceed to step S44 for warning.

[0084] If Y0 + DY1 > M2, meaning the expected value of the second set of etching errors, Y1, is greater than M2, then it is determined that adjusting only the second set of etching errors, Y, cannot prevent the third set of etching errors, Z, from being affected. In this case, it can be evaluated whether Y and Z can be adjusted simultaneously so that both Y and Z are within the corresponding process allowances M2 and M3, in order to compensate for the deviation caused by the change in the first set of etching errors, DX1.

[0085] In one embodiment, based on the change in the first set of etching error DX1, the first relative change rate a, and the second relative change rate b, it can be determined whether there exists a second expected change in the second set of etching error Y, DY2, such that Y0+DY2≤M2 and Z0+DX1*a+DY2*b≤M3 are simultaneously true.

[0086] That is, before manufacturing the third film layer pattern, the expected value of the second set of etching errors Y is calculated as Y2 = Y0 + DY2, and the expected value of the third set of etching errors Z is calculated as Z1 = Z0 + DX1*a + DY2*b. It is then determined whether there exists a DY2 such that both Y2 and Z1 are within the corresponding process allowances M2 and M3.

[0087] If it exists, then the correction value of the feedforward parameter corresponding to the second set of etching errors is determined according to the second expected change amount DY2 of the second set of etching errors; if it does not exist, then it is determined that the deviation caused by DX1 can no longer be compensated by adjusting Y in the range of M2 and adjusting Z in the range of M3, and a process warning is directly issued, or even the current wafer is judged to be scrapped.

[0088] exist Figure 4 In the illustrated embodiment, if there exists a second expected change amount DY2 for the second set of etching errors, the correction value of the feedforward parameter corresponding to the second set of etching errors can be determined based on the minimum value of the second expected change amount DY2. In an extreme case, the second expected change amount DY2 can be zero, thereby ensuring that the third set of etching errors does not exceed the third process allowance M3 without adjusting the second set of etching errors (i.e., the expected change amount DZ1 of the third set of etching errors caused by the change amount DX1 of the first set of etching errors is acceptable); in this case, the correction value of the feedforward parameter corresponding to the second set of etching errors is zero, that is, there is no need to correct the feedforward parameter corresponding to the second set of etching errors.

[0089] The above embodiments describe that, based on the first expected change amount DY1 or the second expected change amount DY2 of the second overlay error Y, when both overlay errors are two-dimensional vectors and the relative change rates are two-dimensional vectors, the overlay errors can be calculated according to the changes in the x and y directions in the two-dimensional coordinate system, as well as formula (3) in the x and y directions, which will not be elaborated here.

[0090] By determining the expected change amount DY1 or DY2 corresponding to the second set of etching errors in real time based on the current value X1 of the first set of etching errors, the third set of etching errors can be minimized or unaffected by adjusting only the second set of etching errors during the fabrication of the third film layer pattern. This allows for real-time mitigation of potential problems caused by the change amount DX1 of the first set of etching errors, eliminating the need to wait until the batch of wafers is completed before correcting the manufacturing coefficient. This can efficiently improve the yield rate of wafer manufacturing, reduce scrapped wafers, and save production costs.

[0091] Figure 5 This is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this disclosure. Figure 5 The method shown uses Figure 3 The overlay correction method shown performs real-time correction of the feedforward parameters.

[0092] refer to Figure 5 Method 500 includes:

[0093] Step S51: A first film pattern and a second film pattern are formed on the substrate using a photolithography device;

[0094] Step S52: Correct the feedforward parameter using the correction value of the feedforward parameter determined according to the overlay correction method 300;

[0095] Step S53: Based on the corrected feedforward parameters, the third film pattern is formed on the substrate using the photolithography equipment.

[0096] Figure 5 The method 500 shown can be used to manufacture a memory, wherein the first film pattern includes an active layer, the second film pattern includes an embedded word line layer, and the third film pattern includes a bit line contact structure layer.

[0097] In one embodiment, the first film pattern and the second film pattern include overlay marks for measuring the first overlay error, the first film pattern and the third film pattern include overlay marks for measuring the second overlay error, and the second film pattern and the third film pattern do not include overlay marks for measuring the third overlay error.

[0098] Figure 6 This is a schematic diagram of the film pattern and overlay error in one embodiment of this disclosure.

[0099] refer to Figure 6 In one embodiment, the first film pattern 61 includes an active layer AA, the second film pattern 62 includes an embedded word line layer BWL, and the third film pattern 63 includes a bit line contact structure layer BLC.

[0100] Figure 6 The left side shows a schematic diagram (top view) illustrating the horizontal positional relationship of the active layer AA, the embedded word line layer BWL, and the bit line contact structure layer BLC. Figure 6 The right side shows a schematic diagram (side view) illustrating the vertical positional relationship of the active layer AA, the embedded word line layer BWL, and the bit line contact structure layer BLC.

[0101] In actual production, the active layer AA and the buried word line layer BWL are manufactured before the bit line contact structure layer BLC. There is a first overlay error BWL-AA between the buried word line layer BWL and the active layer AA, a second overlay error BLC-AA between the bit line contact structure layer BLC and the active layer AA, and a third overlay error BLC-BWL between the bit line contact structure layer BLC and the buried word line layer BWL. The process margin M3 of the third overlay error is less than the process margin M2 of the second overlay error and also less than the process margin M1 of the first overlay error, that is, M3 < M1 and M3 < M2.

[0102] In actual production, usually only overlay marks for measuring the first overlay error BWL-AA and the second overlay error BLC-AA are set. Thus, when manufacturing the third film layer pattern 63, i.e., the bit line contact structure layer BLC, due to the lack of overlay marks corresponding to the third overlay error BLC-BWL, if the third film layer pattern 63 is manufactured according to the larger process margins of the first overlay error and the second overlay error, it may cause the third overlay error BLC-BWL to exceed the process margin M3, resulting in Figure 6 as shown on the left, a short circuit between the bit line contact structure BLC and the buried word line BWL.

[0103] Generally, to solve this problem, it is necessary to redesign the overlay marks and remanufacture the mask plate, which is costly. However, by the method provided in the embodiments of the present disclosure, when no overlay marks for measuring the third overlay error with a smaller process margin are set on the second film layer pattern and the third film layer pattern, it is possible to ensure that the third overlay error is within the process margin without redesigning the overlay marks and without remanufacturing the mask plate, thus saving production costs.

[0104] Figure 7 It is a schematic diagram of the influence of the embodiments of the present disclosure on the overlay mark tree.

[0105] Refer to Figure 7 , the overlay mark tree (OVL tree) is used to record the corresponding relationship of the overlay marks between each film layer pattern. In Figure 7In the upper part, the traditional overlay mark tree can only measure the overlay error between two films with corresponding overlay marks, such as the overlay error between film 2 and film 1, film 3 and film 1, film 4 and film 2, film 5 and film 2, film 6 and film 3, and film 7 and film 3. For films without corresponding overlay marks, it is impossible to measure their overlay error. For example, it is impossible to measure the error between film 6 and film 1. In the actual manufacturing process, even if the overlay error between film 3 and film 1 changes, or the overlay error between film 6 and film 3 changes, as long as the overlay error between film 3 and film 1 and the overlay error between film 6 and film 3 are within the corresponding process allowance, no warning will be issued. However, it is very likely that the wafer will be scrapped because the overlay error between film 6 and film 1 far exceeds the expected value.

[0106] However, due to the limitations of wafer area, it is not possible to set corresponding overlay marks for every two film layer patterns.

[0107] The method provided by this disclosure eliminates the need for additional overlay marks on the second and third film layer patterns for measuring the third overlay error, saving wafer area. Similarly, this disclosure can also be applied to the fabrication of other film layer patterns with relative positional relationships. It eliminates the need for overlay error marks between every two layers; the expected value of the overlay error between any two layers can be calculated simply based on the relative positional relationship between the film layer patterns. Figure 7 In the lower part, before manufacturing film layer 6, it is only necessary to calculate the expected value of the overlay error between film layer 6 and film layer 1, as well as the expected value of the overlay error between film layer 6 and film layer 3. Based on the relationship between the expected value of each overlay error and the corresponding process allowance, the feedforward parameters of film layer manufacturing are corrected in real time. This can ensure that even if there is no corresponding overlay mark between any two film layers, there can still be an overlay error within the process allowance range, which greatly improves the yield of wafer fabrication, saves wafer area, and saves production costs.

[0108] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0109] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0110] The following reference Figure 8 To describe an electronic device 800 according to this embodiment of the present invention. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0111] like Figure 8 As shown, the electronic device 800 is manifested in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, and a bus 830 connecting different system components (including storage unit 820 and processing unit 810).

[0112] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 810 can perform the method shown in the embodiments of this disclosure.

[0113] Storage unit 820 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 8201 and / or a cache memory unit 8202, and may further include a read-only memory unit (ROM) 8203.

[0114] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0115] Bus 830 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0116] Electronic device 800 can also communicate with one or more external devices 900 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0117] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0118] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0119] The program product for implementing the above-described method according to embodiments of the present invention may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0120] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0121] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0122] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0123] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0124] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0125] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0126] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method for constructing an overlay error model, characterized in that, include: Acquire the first set of etching error data of the second film pattern relative to the first film pattern and the second set of etching error data of the third film pattern relative to the first film pattern; Based on the second set error data and the first set error data, calculate the third set error data of the third film pattern relative to the second film pattern; Based on the first overlay error data, the second overlay error data, and the third overlay error data, determine a first relative change ratio between the third overlay error and the first overlay error when the second overlay error remains constant, and a second relative change ratio between the third overlay error and the second overlay error when the first overlay error remains constant; and The overlay error model is constructed as follows: DZ = DX*a + DY*b Wherein, DX, DY, and DZ represent the changes in the first set of engraving errors, the second set of engraving errors, and the third set of engraving errors, respectively, and a and b represent the first relative change ratio and the second relative change ratio, respectively.

2. The method as described in claim 1, characterized in that, Based on the first overlay error data, the second overlay error data, and the third overlay error data, a first relative change ratio between the third overlay error and the first overlay error is determined when the second overlay error remains unchanged, and a second relative change ratio between the third overlay error and the second overlay error is determined when the first overlay error remains unchanged, including: Based on the first set of engraving error data, the second set of engraving error data, and the third set of engraving error data, the change data of the first set of engraving error, the change data of the second set of engraving error, and the change data of the third set of engraving error are obtained; The data on the changes in the first set of engraving errors, the data on the changes in the second set of engraving errors, and the data on the changes in the third set of engraving errors are fitted to obtain the first relative change ratio and the second relative change ratio simultaneously.

3. The method as described in claim 1, characterized in that, Based on the first overlay error data, the second overlay error data, and the third overlay error data, a first relative change ratio between the third overlay error and the first overlay error is determined when the second overlay error remains unchanged, and a second relative change ratio between the third overlay error and the second overlay error is determined when the first overlay error remains unchanged, including: The first set of etching error data and the third set of etching error data corresponding to the same second set of etching error data are fitted to obtain the first relative change ratio; The second relative change ratio is obtained by fitting the second set of etching error data and the third set of etching error data corresponding to the same first set of etching error data.

4. The method as described in claim 1, characterized in that, The first set of engraving errors, the second set of engraving errors, and the third set of engraving errors are all scalars or two-dimensional vectors.

5. The method as described in claim 1, characterized in that, When the first set of lithography errors, the second set of lithography errors, and the third set of lithography errors are all scalars, both the first relative change ratio and the second relative change ratio are scalars; when the first set of lithography errors, the second set of lithography errors, and the third set of lithography errors are all two-dimensional vectors, both the first relative change ratio and the second relative change ratio are scalars or two-dimensional vectors.

6. A method for overlay correction, characterized in that, Comprising: Obtaining a first relative change rate a and a second relative change rate b determined according to the method for constructing a lithography error model according to any one of claims 1-5; Obtaining a first process margin M1 of the second film layer pattern relative to the first film layer pattern, a second process margin M2 of the third film layer pattern relative to the first film layer pattern, and a third process margin M3 of the third film layer pattern relative to the second film layer pattern; Obtaining an initial value X0 of the first set of lithography errors and an initial value Y0 of the second set of lithography errors, and calculating an initial value Z0 of the third set of lithography errors according to the initial value X0 of the first set of lithography errors and the initial value Y0 of the second set of lithography errors, where X0 ≤ M1, Y0 ≤ M2, and Z0 ≤ M3; Obtaining a current value X1 of the first set of lithography errors; When X1 ≤ M1, calculating a change amount DX1 of the first set of lithography errors according to the current value X1 of the first set of lithography errors and the initial value X0 of the first set of lithography errors; Determining a first expected change amount DY1 of the second set of lithography errors according to the change amount DX1 of the first set of lithography errors, the first relative change rate a, and the second relative change rate b, where the expected change amount DZ1 of the third set of lithography errors corresponding to the first expected change amount DY1 of the second set of lithography errors is equal to zero; When Y0 + DY1 ≤ M2, determining a correction value of the feedforward parameter corresponding to the second set of lithography errors according to the first expected change amount DY1 of the second set of lithography errors.

7. The overlay correction method as described in claim 6, characterized in that, Further comprising: When Y0 + DY1 > M2, determining whether there is a second expected change amount DY2 of the second set of lithography errors such that Y0 + DY2 ≤ M2 and Z0 + DX1 * a + DY2 * b ≤ M3 hold simultaneously according to the change amount DX1 of the first set of lithography errors, the first relative change rate a, and the second relative change rate b, If it exists, determining a correction value of the feedforward parameter corresponding to the second set of lithography errors according to the second expected change amount DY2 of the second set of lithography errors; If it does not exist, giving an early warning.

8. The overlay correction method as described in claim 7, characterized in that, If there is a second expected change amount DY2 of the second set of lithography errors, determining a correction value of the feedforward parameter corresponding to the second set of lithography errors according to the minimum value of the second expected change amount DY2 of the second set of lithography errors.

9. The overlay correction method as described in claim 6, characterized in that, M3 < M1 and M3 < M2.

10. The overlay correction method as described in claim 6, characterized in that, Both the first film layer pattern and the second film layer pattern are formed prior to the third film layer pattern.

11. The overlay correction method as described in claim 6, characterized in that, The first film layer pattern is formed prior to the second film layer pattern; or, the second film layer pattern is formed prior to the first film layer pattern.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Using a lithography apparatus to form a first film layer pattern and a second film layer pattern on a substrate; The feedforward parameter is corrected using the correction value of the feedforward parameter determined by the overlay correction method according to any one of claims 6-11; Based on the corrected feedforward parameters, the third film pattern is formed on the substrate using the photolithography equipment.

13. The method as described in claim 12, characterized in that, The first film pattern and the second film pattern include overlay marks for measuring the first overlay error, the first film pattern and the third film pattern include overlay marks for measuring the second overlay error, and the second film pattern and the third film pattern do not include overlay marks for measuring the third overlay error.

14. The method as described in claim 12, characterized in that, The first film pattern includes an active layer, the second film pattern includes an embedded word line layer, and the third film pattern includes a bit line contact structure layer.

15. An electronic device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the overlay correction method as described in any one of claims 6-11 based on instructions stored in the memory.

16. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the overlay correction method as described in any one of claims 6-11.

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