Level Embedded Capacitor PCB Layout Structure for Reducing Parasitic Inductance of GaN Devices

Abstract

The present invention discloses a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices, which relates to the technical field of power converters and includes: a printed circuit board; a first GaN device and a second GaN device located on one side of the printed circuit board; a decoupling capacitor horizontally embedded in the printed circuit board; wherein, the first GaN device, the second GaN device and the decoupling capacitor form a power loop, so that the area of the power loop can be effectively reduced, and further the purpose of reducing the parasitic inductance can be achieved by reducing the self-inductance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power converters, and particularly relates to a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices. Background Art

[0002] Currently, due to the demand for high power density and high efficiency of converters, the power density is often increased by increasing the switching frequency, and then the volume of the output capacitance and inductance is reduced. However, the performance of Si-based devices has reached the theoretical limit with the development of technology, and the switching speed is not sufficient to support the high-frequency switching requirements of converters. The third-generation semiconductor GaN devices have faster switching frequencies, lower on-resistances, and higher breakdown voltages, and are widely used in the field of power converters.

[0003] In DC-DC converters, there are still some challenges for GaN devices. First, GaN devices have a high switching speed, so they are very sensitive to parasitic parameters such as parasitic inductance. A very small parasitic inductance will cause large voltage spikes and resonances in the circuit, which will in turn cause greater switching losses and EMI (Electromagnetic Interference) in GaN devices, and even lead to the breakdown of GaN devices, affecting the efficiency and performance of the entire circuit. Second, the tolerance of the gate drive voltage is small. For example, the gate breakdown voltage of the enhanced GaN device of EPC company is only 6V, 5V is the optimal turn-on voltage of the device, and only 1V of overshoot is allowed. That is to say, the parasitic inductance of the drive loop must be strictly controlled, otherwise the gate is easily broken down, resulting in damage to the GaN device. Third, the threshold voltage of GaN is low, so the parasitic inductance easily causes the gate voltage to exceed the threshold voltage, causing the GaN device to turn on erroneously.

[0004] In the related art, those skilled in the art mostly adopt horizontal or vertical circuit layout methods, in which the area of the power loop is large, resulting in a large parasitic inductance. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices, including:

[0007] A printed circuit board;

[0008] A first GaN device and a second GaN device located on one side of the printed circuit board;

[0009] Decoupling capacitors horizontally embedded in a printed circuit board;

[0010] Wherein, the first GaN device, the second GaN device and the decoupling capacitor form a power loop.

[0011] In an embodiment of the present invention, a plurality of decoupling capacitors are included;

[0012] The printed circuit board includes three layers of copper-clad laminates. Each layer of copper-clad laminate includes a base layer, and a copper foil is covered on the base layer. FR-4 epoxy resin is provided between adjacent two layers of copper-clad laminates. Wherein, the plurality of decoupling capacitors are located on the second layer of copper-clad laminate of the printed circuit board.

[0013] In an embodiment of the present invention, the plurality of decoupling capacitors are arranged at intervals along a first direction;

[0014] Wherein, the plane formed by the thickness direction of the printed circuit board and the first direction is perpendicular to the plane where the printed circuit board is located.

[0015] In an embodiment of the present invention, both the first GaN device and the second GaN device are in a land grid array (LGA) package. The side of the first GaN device close to the printed circuit board includes a plurality of first source electrodes and first drain electrodes arranged alternately along the first direction. The side of the second GaN device close to the printed circuit board includes a plurality of second source electrodes and second drain electrodes arranged alternately along the first direction.

[0016] In an embodiment of the present invention, the first drain electrode of the first GaN device and the second source electrode of the second GaN device are correspondingly arranged in the first direction, and the first source electrode of the first GaN device and the second drain electrode of the second GaN device are correspondingly arranged in the first direction.

[0017] In an embodiment of the present invention, the first drain electrode of the first GaN device is connected to the second source electrode of the second GaN device through a via hole, and the first source electrode of the first GaN device is connected to the second drain electrode of the second GaN device through a decoupling capacitor.

[0018] In an embodiment of the present invention, the first drain electrode includes: D 11 , D 12 , D 13 and D 14 , the first source electrode includes S 11 , S 12 , S 13 and S 14 , the second drain electrode includes: D 21 , D 22 , D 23 and D 24 , the second source electrode includes S 21, S 22 , S 23 and S 24 , the multiple decoupling capacitors include: C bus1 , C bus2 , C bus3 and C bus4 ; wherein,

[0019] D 11 is connected to S 21 , D 12 is connected to S 22 , D 13 is connected to S 23 , D 14 is connected to S 24 through vias, S 11 is connected to D 21 , S 12 is connected to D 22 , S 13 is connected to D 23 , S 14 is connected to D 24 respectively through C bus1 , C bus2 , C bus3 and C bus4 connected, S 11 , C bus1 , D 21 , S 21 and D 11 forms a first power loop, S 12 , C bus2 , D 22 , S 22 and D 12 forms a second power loop, S 13 , C bus3 , D 23 , S 23 and D 13 forms a third power loop, S 14 , C bus4 , D 24 , S 24 and D 14 forms a fourth power loop.

[0020] In an embodiment of the present invention, the via is filled with metallic copper.

[0021] In an embodiment of the present invention, the copper foil of the third layer of copper clad laminate in the printed circuit board is grounded.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] The present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices, including: a printed circuit board; a first GaN device and a second GaN device located on one side of the printed circuit board; a decoupling capacitor horizontally embedded in the printed circuit board; wherein, the first GaN device, the second GaN device and the decoupling capacitor form a power loop, which can effectively reduce the area of the power loop, and further reduce the parasitic inductance by reducing the self-inductance.

[0024] The following will further describe the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0025] Figure 1 is a schematic diagram of the parasitic inductance of a Buck converter in the related art;

[0026] Figure 2 is a schematic diagram of a traditional horizontal circuit layout;

[0027] Figure 3 is a schematic diagram of a traditional vertical circuit layout;

[0028] Figure 4 is a PCB layout structure diagram for reducing the parasitic inductance of GaN devices provided by an embodiment of the present invention;

[0029] Figure 5 is a sectional view taken along the line AA' of the PCB layout diagram provided by an embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of the power loop in the horizontal circuit layout provided by an embodiment of the present invention;

[0031] Figure 7 is a sectional view taken along the line BB' of the PCB layout diagram provided by an embodiment of the present invention;

[0032] Figure 8 is a partial schematic diagram of the printed circuit board provided by an embodiment of the present invention;

[0033] Figure 9 is an equivalent circuit diagram of multiple parallel current loops provided by an embodiment of the present invention;

[0034] Figure 10a is a schematic diagram of current filaments in the case of strong coupling provided by an embodiment of the present invention;

[0035] Figure 10b is a schematic diagram of current filaments in the case of weak coupling provided by an embodiment of the present invention;

[0036] Figure 10c is a schematic diagram of current filaments in the case of reverse coupling provided by an embodiment of the present invention;

[0037] Figure 11a It is another schematic diagram of current filaments in strong coupling provided by an embodiment of the present invention;

[0038] Figure 11b It is another schematic diagram of current filaments in weak coupling provided by an embodiment of the present invention;

[0039] Figure 11c It is another schematic diagram of current filaments in reverse coupling provided by an embodiment of the present invention;

[0040] Figure 12 It is a schematic diagram of the magnetic flux of a single energized loop provided by an embodiment of the present invention;

[0041] Figure 13 It is a simulation diagram of the traditional horizontal circuit layout method provided by an embodiment of the present invention;

[0042] Figure 14 It is a simulation result diagram of the traditional horizontal circuit layout method provided by an embodiment of the present invention;

[0043] Figure 15 It is a simulation diagram of the horizontal embedded capacitor PCB layout structure provided by an embodiment of the present invention;

[0044] Figure 16 It is the simulation result of the horizontal embedded capacitor PCB layout structure provided by an embodiment of the present invention. Detailed implementation manners

[0045] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0046] Figure 1 It is a schematic diagram of the parasitic inductance of a Buck converter in the related art. Taking the buck converter Buck as an example, the parasitic inductance is analyzed. As Figure 1 shown, there are three parasitic inductances that will have a substantial impact on the Buck converter, namely: the common-source inductance L S , the power loop inductance L Loop and the drive loop inductance L G . Among them, the common-source inductance Ls is mainly the parasitic inductance caused by device packaging, and the power loop inductance L Loop and the drive loop inductance L G are determined by device packaging and circuit layout.

[0047] It should be noted that the above analysis process is also applicable to boost converters, half-bridges, full-bridges, and other topologies.

[0048] Currently, those skilled in the art mostly adopt the horizontal circuit layout method or the vertical circuit layout method. Figure 2It is a schematic diagram of the traditional horizontal circuit layout method. Specifically, as Figure 2 shown, in the horizontal circuit layout method, all components and wirings are on the same side of the printed circuit board (PCB), generally on the top layer. Although the decoupling capacitor will be placed as close as possible to the GaN device during implementation, the area of the power loop is still large in this layout method. Therefore, the power loop inductor L Loop is large, which also results in a large parasitic inductor.

[0049] Figure 3 It is a schematic diagram of the traditional vertical circuit layout method. As Figure 3 shown, in another vertical circuit layout method, the device and the decoupling capacitor C in are respectively arranged on the top layer and the bottom layer of the PCB board, and the device and the decoupling capacitor C in are connected through vias. Compared with the horizontal circuit layout method shown in Figure 2 , to a certain extent, it reduces the area of the power loop, reduces the trace length of the power loop, and thus reduces the power loop inductor. In addition, since the current flow directions on the top layer and the bottom layer are opposite, the magnetic fields can cancel each other out, further reducing the power loop inductor.

[0050] It can be seen that the vertical circuit layout method mainly depends on the thickness of the PCB board. The thicker the PCB board, the larger the area of the power loop and the larger the power loop inductor L Loop will be. However, due to process limitations, the design of an extremely thin PCB board is very difficult.

[0051] In view of this, the present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductor of GaN devices.

[0052] Figure 4 It is a PCB layout structure diagram for reducing the parasitic inductor of GaN devices provided by an embodiment of the present invention, Figure 5 and it is a sectional view taken along AA' of the PCB layout diagram provided by an embodiment of the present invention. Please refer to Figures 4-5 . An embodiment of the present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductor of GaN devices, including:

[0053] Printed circuit board 1;

[0054] The first GaN device Q1 and the second GaN device Q2 located on one side of the printed circuit board 1;

[0055] The decoupling capacitor C bus horizontally embedded in the printed circuit board 1;

[0056] Among them, the first GaN device Q1, the second GaN device Q2 and the decoupling capacitor C bus form a power loop.

[0057] In this embodiment, the horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices includes: a printed circuit board 1, a first GaN device Q1, a second GaN device Q2 and a decoupling capacitor C bus , where the first GaN device Q1 and the second GaN device Q2 are arranged side by side on the same side of the printed circuit board 1, and the decoupling capacitor C bus is horizontally embedded in the printed circuit board 1. The so-called horizontal embedding means that the plane where the decoupling capacitor C bus is located is parallel to the plane where the printed circuit board 1 is located. In this way, the first GaN device Q1, the second GaN device Q2 and the decoupling capacitor can form a power loop.

[0058] It should be understood that the circuit layout method will affect the magnitude of the parasitic inductance. In this embodiment, the decoupling capacitor C bus is horizontally embedded in the printed circuit board 1, then the area of the power loop is as shown by the dotted closed figure in Figure 5 . Obviously, at this time, the size of the power loop area is related to the vertical distance between the position where the decoupling capacitor C bus is located and the first-layer copper foil of the PCB board. Figure 6 is a schematic diagram of the power loop in the horizontal circuit layout method provided by the embodiment of the present invention. For the horizontal circuit layout method in the prior art, the area of the power loop is as shown by the closed quadrilateral in Figure 6 . Since the thickness of the PCB board is much smaller than the length of the horizontal wiring, the area of the power loop in this embodiment is also smaller than the area of the power loop in the horizontal layout method, thereby achieving the purpose of reducing the parasitic inductance.

[0059] Furthermore, in another existing vertical circuit layout method, the area of the power loop is as shown by the closed quadrilateral in Figure 3 . However, in the vertical circuit layout method, the decoupling capacitor C in and the GaN device are located on both sides of the printed circuit board respectively, while in this embodiment, the decoupling capacitor is embedded in the printed circuit board 1. Therefore, the area of the power loop in this embodiment is also smaller than the area of the power loop in the vertical circuit layout method. It can be seen that this embodiment reduces the size of the power loop, thereby effectively reducing the parasitic inductance.

[0060] In addition, in Figure 3 , Figures 5-6 , the arrows all indicate the direction of current flow.

[0061] Figure 7 is the BB' sectional view of the PCB layout diagram provided by the embodiment of the present invention, Figure 8It is a partial schematic diagram of the printed circuit board provided by an embodiment of the present invention. As Figures 7-8 shown, the above-mentioned horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices includes a plurality of decoupling capacitors C bus ;

[0062] The printed circuit board 1 includes three layers of copper-clad laminates. Each layer of copper-clad laminate includes a base layer, and a copper foil is covered on the base layer. FR-4 epoxy resin is between adjacent two layers of copper-clad laminates. Among them, a plurality of decoupling capacitors C bus are located on the second layer of copper-clad laminate of the printed circuit board 1.

[0063] Specifically, the printed circuit board 1 includes three layers of copper-clad laminates. In Figure 8 the shown perspective, the first GaN device Q1 and the second GaN device Q2 are located on the top layer (the first layer) of copper-clad laminate, and a plurality of decoupling capacitors C bus are located on the second layer of copper-clad laminate. Therefore, the power loop area in this horizontal embedded capacitor PCB layout structure mainly depends on the distance between the first layer of copper-clad laminate and the second layer of copper-clad laminate. According to the process standard, this distance is only about 0.05 mm, greatly reducing the power loop area.

[0064] Optionally, please continue to refer to Figures 4-5 , a plurality of decoupling capacitors C bus are arranged at intervals along the first direction;

[0065] Among them, the plane formed by the thickness direction of the printed circuit board 1 and the first direction is perpendicular to the plane where the printed circuit board 1 is located.

[0066] In this embodiment, a plurality of decoupling capacitors C bus are all embedded on the copper foil of the second layer of copper-clad laminate, and they are arranged at equal intervals in the first direction. Considering that the decoupling capacitor C bus is a cuboid and requires a certain space when placed, the distance of about 0.8 mm between the second layer of copper-clad laminate and the third layer of copper-clad laminate can also be used to accommodate the decoupling capacitor C bus .

[0067] Optionally, as Figure 4 shown, both the first GaN device Q1 and the second GaN device Q2 are grid array LGA packages. One side of the first GaN device Q1 close to the printed circuit board 1 includes a plurality of first source electrodes and first drain electrodes arranged alternately along the first direction, and one side of the second GaN device Q2 close to the printed circuit board 1 includes a plurality of second source electrodes and second drain electrodes arranged alternately along the first direction.

[0068] It should be noted that in this embodiment, the first drain of the first GaN device Q1 and the second source of the second GaN device Q2 are correspondingly arranged in the first direction, and the first source of the first GaN device Q1 and the second drain of the second GaN device Q2 are correspondingly arranged in the first direction.

[0069] Optionally, the first drain of the first GaN device Q1 and the second source of the second GaN device Q2 are connected through vias, and the first source of the first GaN device Q1 and the second drain of the second GaN device Q2 are connected through a decoupling capacitor C bus .

[0070] Specifically, as Figure 4 shown, the first drain includes: D 11 , D 12 , D 13 and D 14 , the first source includes S 11 , S 12 , S 13 and S 14 , the second drain includes: D 21 , D 22 , D 23 and D 24 , the second source includes S 21 , S 22 , S 23 and S 24 , the multiple decoupling capacitors C bus include: C bus1 , C bus2 , C bus3 and C bus4 ; where

[0071] D 11 is connected to S 21 , D 12 is connected to S 22 , D 13 is connected to S 23 , D 14 is connected to S 24 through vias, and S 11 is connected to D 21 , S 12 is connected to D 22 , S 13 is connected to D 23 , S 14 is connected to D 24 respectively through C bus1 , C bus2 , C bus3 and C bus4 , and S 11 , C bus1 , D 21 , S21 and D 11 form the first power loop, S 12 , C bus2 , D 22 , S 22 and D 12 form the second power loop, S 13 , C bus3 , D 23 , S 23 and D 13 form the third power loop, S 14 , C bus4 , D 24 , S 24 and D 14 form the fourth power loop.

[0072] Optionally, the via is filled with metallic copper.

[0073] It should be noted that for a single current loop, the magnetic energy in the magnetic field of space, the loop inductance expression is:

[0074]

[0075] In the formula, W m represents the magnetic energy stored in space, and I represents the current flowing through the loop.

[0076] Figure 9 is the equivalent circuit diagram of multiple parallel current loops provided by the embodiments of the present invention. As Figure 9 shown, for multiple parallel current loops, each loop has self-inductance, and there is mutual inductance between the loops. Therefore, the magnetic energy generated by the self-inductance and mutual inductance constitutes the total magnetic energy:

[0077]

[0078] In the formula, I i represents the current of the i-th loop, L i represents the self-inductance of the i-th loop, M ij represents the mutual inductance between the i-th loop and the j-th loop, and N represents the number of loops.

[0079] Furthermore, for multiple parallel current loops, Figure 5 is its equivalent circuit, then the total loop inductance of the circuit is:

[0080]

[0081] It can be seen from formula (3) that the total loop inductance can be reduced by reducing the mutual inductance.

[0082] Figure 10 is a schematic diagram of current filaments under different coupling degrees, where,Figure 10a It is a schematic diagram of current filaments in strong coupling provided by an embodiment of the present invention. Figure 10b It is a schematic diagram of current filaments in weak coupling provided by an embodiment of the present invention. Figure 10c It is a schematic diagram of current filaments in reverse coupling provided by an embodiment of the present invention. Further, a single current loop can be assumed to be composed of multiple parallel current loop filaments. For example, Figure 10a As shown, since the distance between different current filaments is infinitesimal, it can be regarded as full coupling, and the current directions in each current filament are the same. Then the full-coupling mutual inductance is expressed as:

[0083]

[0084] In the formula, L1 and L2 respectively represent the inductances of two types of current filaments, k represents the coupling coefficient, and M represents the mutual inductance between two types of current filaments.

[0085] When the two current filaments are fully coupled, the coupling coefficient k = 1, and the inductance of each current filament is L0. Therefore, the mutual inductance M between two current filaments ij = L0. Then the total inductance of a single current loop can be simplified as:

[0086]

[0087] When the current filaments are separated into the weak-coupling form as Figure 10b shown, the mutual inductance between the current filaments will decrease as the distance between the current filaments increases, resulting in a decrease in the total inductance. And when the current filaments are in the Figure 10c shown reverse-coupling state, by reversing the current of adjacent current filaments, the magnetic field will be cancelled due to reverse coupling, and thus the total inductance will be further reduced. Optionally, the width and length of the matrix loop corresponding to each current filament are respectively denoted as w and l, and the distance between different matrix loops is denoted as d. As Figure 10b shown, the mutual inductance between two matrix loops is:

[0088]

[0089] In the formula, μ0 represents the vacuum permeability.

[0090] Figure 11 is another schematic diagram of current filaments under different coupling degrees provided by an embodiment of the present invention. Among them, Figure 11a It is another schematic diagram of current filaments in strong coupling provided by an embodiment of the present invention. Figure 11b It is another schematic diagram of current filaments in weak coupling provided by an embodiment of the present invention. Figure 11c It is another schematic diagram of current filaments in reverse coupling provided by an embodiment of the present invention. Further, the current filaments are separated into Figure 11bThe weakly coupled state shown, where the current filaments are slightly separated, and the mutual inductance between the current filaments will decrease. If the current loop is extended into a plane as shown in Figure 11c and a staggered structure is formed, the mutual inductance will be further reduced. Therefore, the inductance of the staggered structure will be lower than that of a single loop.

[0091] Exemplarily, the mutual inductance between the current filaments after being extended into a plane is:

[0092]

[0093] In the formula, K represents a coefficient in M, f(·) represents a coefficient in K, Z i represents the impedance of the i-th energized loop, and r j represents the radius of the j-th energized loop.

[0094] Figure 12 is the magnetic flux schematic diagram of a single energized loop provided by an embodiment of the present invention. As shown in Figure 12 , for a single energized loop, according to the right-hand rule, the current will generate a magnetic flux density B that passes through the surface enclosed by the current. The total magnetic flux through the loop is:

[0095]

[0096] In the formula, s represents the area of a single energized loop.

[0097] The rate of change of magnetic flux will generate an electromotive force around the loop:

[0098]

[0099] The voltage across the inductor can be expressed as:

[0100]

[0101] Then

[0102] Obviously, when the area of the power loop decreases, the magnetic flux decreases, and thus the inductance L will also decrease accordingly.

[0103] Then, combining the foregoing analysis, since the decoupling capacitor C in this embodiment bus is horizontally embedded in the PCB, the area occupied by the power loop is reduced, thereby reducing the self-inductance of the power loop and ultimately achieving the purpose of reducing the parasitic inductance.

[0104] Generally, the parasitic inductance includes the self-inductance in each power loop and the mutual inductance between different loops. Please refer to Figure 4 , S 11 , C bus1 , D 21 , S21 and D 11 form the first power loop, S 12 , C bus2 , D 22 , S 22 and D 12 form the second power loop, S 13 , C bus3 , D 23 , S 23 and D 13 form the third power loop, S 14 , C bus4 , D 24 , S 24 and D 14 form the fourth power loop, and D 11 and S 21 form the first trace, D 12 and S 22 form the second trace, D 13 and S 23 form the third trace, D 14 and S 24 form the fourth trace. Taking the first trace as an example, the current flow direction is opposite to that of the trace formed by S 11 , D 21 . That is, the magnetic fields with opposite directions generated by the two traces can cancel each other out; similarly, the same applies to the second trace, the third trace, and the fourth trace. In this embodiment, the mutual inductance is eliminated by making the magnetic fields generated by the two-by-two traces cancel each other out, further reducing the parasitic inductance.

[0105] In this embodiment, the copper foil of the third-layer copper clad laminate in the printed circuit board 1 is grounded.

[0106] Specifically, in this embodiment, by grounding the copper foil of the third-layer copper clad laminate, a copper metal shielding layer can be formed. Then, when the magnetic flux generated after the power loop is energized passes through the copper metal shielding layer, eddy currents will be generated in the copper metal shielding layer, and then the eddy currents will generate magnetic fluxes opposite to the original magnetic flux, and the two magnetic fluxes cancel each other out, which is beneficial to further reducing the parasitic inductance.

[0107] Next, the horizontal embedded capacitor PCB layout structure provided by the present invention for reducing the parasitic inductance of GaN devices will be further described through simulation experiments.

[0108] Figure 13 is the simulation diagram of the traditional horizontal circuit layout method provided by the embodiment of the present invention, Figure 14 is the simulation result diagram of the traditional horizontal circuit layout method provided by the embodiment of the present invention. As Figures 13-14As shown, the lateral circuit layout method in the prior art is simulated, and the parasitic inductance obtained from the simulation is 0.9323 nh.

[0109] Figure 15 is a simulation diagram of the horizontal embedded capacitor PCB layout structure provided by an embodiment of the present invention. Figure 16 is the simulation result of the horizontal embedded capacitor PCB layout structure provided by an embodiment of the present invention. As Figures 15-16 shown, the horizontal embedded capacitor PCB layout structure provided by the present invention for reducing the parasitic inductance of GaN devices is simulated, and the obtained parasitic inductance is 0.04031 nh.

[0110] Obviously, compared with the existing lateral circuit layout method, the parasitic inductance of the horizontal embedded capacitor PCB layout structure provided by the present invention for reducing the parasitic inductance of GaN devices is reduced by about 0.89 nh, reducing the parasitic inductance by 96%.

[0111] From the above embodiments, it can be seen that the beneficial effects of the present invention are as follows:

[0112] The present invention provides a horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices, including: a printed circuit board; a first GaN device and a second GaN device located on one side of the printed circuit board; a decoupling capacitor horizontally embedded in the printed circuit board; wherein, the first GaN device, the second GaN device and the decoupling capacitor form a power loop, which can effectively reduce the area of the power loop, and further reduce the parasitic inductance by reducing the self-inductance.

[0113] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0114] The description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0115] Although the present application has been described in connection with various embodiments, however, in the process of implementing the claimed present application, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims.

[0116] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices, characterized in that, Comprising: A printed circuit board; A first GaN device and a second GaN device located on one side of the printed circuit board; Decoupling capacitors horizontally embedded in the printed circuit board; Wherein, the first GaN device, the second GaN device and the decoupling capacitors form a power loop; The horizontally embedded capacitor PCB layout structure includes a plurality of decoupling capacitors arranged at intervals along a first direction. Both the first GaN device and the second GaN device are in land grid array (LGA) packages. One side of the first GaN device close to the printed circuit board includes a plurality of first source electrodes and first drain electrodes arranged alternately along the first direction. One side of the second GaN device close to the printed circuit board includes a plurality of second source electrodes and second drain electrodes arranged alternately along the first direction. The first drain electrode of the first GaN device and the second source electrode of the second GaN device are correspondingly arranged in the first direction. The first source electrode of the first GaN device and the second drain electrode of the second GaN device are correspondingly arranged in the first direction. Each of the decoupling capacitors is respectively located between the first source electrode of the first GaN device and the second drain electrode of the second GaN device. The plane formed by the thickness direction of the printed circuit board and the first direction is perpendicular to the plane where the printed circuit board is located.

2. The horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices according to claim 1, wherein, The printed circuit board includes three layers of copper-clad laminates. Each layer of copper-clad laminate includes a base layer, and a copper foil is covered on the base layer. FR-4 epoxy resin is between adjacent two layers of copper-clad laminates. Among them, a plurality of decoupling capacitors are located on the second layer of copper-clad laminate of the printed circuit board.

3. The horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices according to claim 1, wherein The first drain electrode of the first GaN device is connected to the second source electrode of the second GaN device through a via hole. The first source electrode of the first GaN device is connected to the second drain electrode of the second GaN device through a decoupling capacitor.

4. The horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices according to claim 3, characterized in that The first drain includes: D 11 , D 12 , D 13 and D 14 , the first source includes S 11 , S 12 , S 13 and S 14 , the second drain includes: D 21 , D 22 , D 23 and D 24 , the second source includes S 21 , S 22 , S 23 and S 24 , a plurality of decoupling capacitors include: C bus1 , C bus2 , C bus3 and C bus4 ; wherein, D 11 is connected to S 21 、D 12 is connected to S 22 、D 13 is connected to S 23 、D 14 is connected to S 24 through a via. S 11 is connected to D 21 、S 12 is connected to D 22 、S 13 is connected to D 23 、S 14 is connected to D 24 respectively through C bus1 、C bus2 、C bus3 and C bus4 to form a first power loop. S 11 、C bus1 、D 21 、S 21 and D 11 to form a second power loop. S 12 、C bus2 、D 22 、S 22 and D 12 to form a third power loop. S 13 、C bus3 、D 23 、S 23 and D 13 to form a fourth power loop. S 14 、C bus4 、D 24 、S 24 and D 14 to form a fourth power loop.

5. The horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices according to claim 3, wherein The via hole is filled with metallic copper.

6. The horizontal embedded capacitor PCB layout structure for reducing the parasitic inductance of GaN devices according to claim 2, wherein The copper foil of the third layer of copper-clad laminate in the printed circuit board is grounded.

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