Circuit device aging assessment and compensation

Abstract

In one aspect, the present disclosure relates to an apparatus (100) comprising: a group of one or more receivers (115-1 to 115-N); a first replica circuit (155) that is a substantial replica of at least a portion of one of the group of one or more receivers; a first control circuit (140) that generates an output signal (Vsas) selectively coupled to an input of the first replica circuit; a second replica circuit (160) that is a substantial replica of at least a portion of one of the group of one or more receivers; a comparator (170) that includes a first input coupled to a first output (VI) of the first replica circuit, a second input coupled to a second output (V2) of the second replica circuit, and an output; and a second control circuit (180) that includes an input coupled to an output (Vcomp) of the comparator, and coupled to the first replica circuit (155) and (Aging CSB) coupled to an output (Aging CS) of the group of one or more receivers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional patent application No. 17 / 339,195, filed on June 4, 2021, which is assigned to the assignee of the present application and is expressly incorporated by reference into this application for all applicable purposes (as fully set forth below). Technical Field

[0003] Aspects of the present disclosure relate generally to integrated circuits (ICs) or discrete circuits, and more particularly, to apparatus and methods for circuit device aging assessment and compensation. Background Art

[0004] Typically, the performance of circuit devices such as field effect transistors (FETs) is not constant throughout their operational life cycle. For example, when a varying gate-source voltage (Vgs) is applied to operate the FET for a period of time depending on the operation in which the FET is used, carriers are injected into the gate oxide of the FET and are trapped in the oxide. Carriers trapped in the FET oxide typically increase the threshold Vth of the FET, thereby requiring a larger Vgs drive voltage to achieve the same drain current through the FET. If such FET aging effects of an integrated circuit (IC) are not corrected, the IC may operate below its specifications, or may even fail to operate. Summary of the invention

[0005] In order to provide a basic understanding of such implementations, a brief summary of one or more implementations is presented below. This summary is not an extensive overview of all contemplated implementations, and is neither intended to identify key or important elements of all implementations nor to delimit the scope of any or all implementations. Its sole purpose is to set forth some concepts of one or more implementations in a simplified form, so as to serve as a prelude to a more detailed description set forth later.

[0006] One aspect of the present disclosure relates to an apparatus. The apparatus includes: a group of one or more receivers; a first replica circuit that is a substantial replica of at least a portion of one of the group of one or more receivers; a first control circuit that generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit that is a substantial replica of at least a portion of one of the group of one or more receivers; a comparator that includes: an output, a first input coupled to the first output of the first replica circuit, and a second input coupled to the second output of the second replica circuit; and a second control circuit that includes: an input coupled to the output of the comparator, and an output coupled to the first replica circuit and coupled to the group of one or more receivers.

[0007] Another aspect of the present disclosure relates to a method. The method includes providing one of a data signal and a clock signal to a receiver; in an aging mode: providing an aging signal to a first replica circuit substantially simultaneously with providing one of the data signal and the clock signal to the receiver, the first replica circuit being a substantial replica of the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than one of the data signal and the clock signal causes the receiver to operate, and keeping a second replica circuit disabled, the second replica circuit being a substantial replica of the receiver; in a calibration mode: enabling the second replica circuit; stopping providing the aging signal to the first replica circuit; applying an input voltage to inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit generate a first output voltage and a second output voltage, respectively, based on the input voltage; generating a compensation voltage based on a difference between a first output voltage of the first replica circuit and a second output voltage of the second replica circuit; and calibrating the receiver and the first replica circuit based on the compensation voltage.

[0008] Another aspect of the present disclosure relates to an apparatus. The apparatus includes: a component for providing one of a data signal and a clock signal to a receiver; in an aging mode: a component for providing an aging signal to a first replica circuit substantially simultaneously with providing one of the data signal and the clock signal to the receiver, the first replica circuit being a substantial replica of the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than one of the data signal and the clock signal causes the receiver to operate, and a component for keeping a second replica circuit disabled, the second replica circuit being a substantial replica of the receiver; in a calibration mode: a component for enabling the second replica circuit; a component for stopping providing the aging signal to the first replica circuit; a component for applying an input voltage to inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit generate a first output voltage and a second output voltage, respectively, based on the input voltage; a component for generating a compensation voltage based on a difference between a first output voltage of the first replica circuit and a second output voltage of the second replica circuit; and a component for calibrating the receiver and the first replica circuit based on the difference between the first output voltage and the second output voltage.

[0009] Another aspect of the present disclosure relates to an automobile control system. The automobile control system includes a group of automobile control signal transmitters; a group of automobile control signal receivers, respectively coupled to the group of automobile control signal transmitters via a group of transmission lines; and an aging compensation circuit. The aging compensation circuit includes a first replica circuit, which is a substantial replica of one of the automobile control signal receivers in the group of automobile control signal receivers; a first control circuit, including an output selectively coupled to an input of the first replica circuit; a second replica circuit, which is a substantial replica of one of the automobile control signal receivers in the group of automobile control signal receivers; a comparator, including: a first input coupled to the first output of the first replica circuit, and a second input coupled to the second output of the second replica circuit; a second control circuit, including: an input coupled to the output of the comparator, and an output coupled to the first replica circuit and the group of automobile control signal receivers.

[0010] To achieve the foregoing and related ends, one or more implementations include the features fully described below and particularly pointed out in the claims. The following description and drawings set forth in detail certain exemplary aspects of one or more implementations. However, these aspects are only indicative of a small portion of the various ways in which the principles of various implementations may be employed, and the description of the implementations is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram of an exemplary apparatus including an exemplary aging compensation circuit according to an aspect of the present disclosure is illustrated.

[0012] Figure 2 A block diagram of another exemplary apparatus including another exemplary aging compensation circuit according to another aspect of the disclosure is illustrated.

[0013] Figure 3 A block diagram of yet another exemplary apparatus including yet another exemplary aging compensation circuit according to another aspect of the present disclosure is illustrated.

[0014] Figure 4 A schematic diagram of an exemplary aging compensation circuit according to another aspect of the present disclosure is illustrated.

[0015] Figure 5 A schematic diagram of a portion of an exemplary aging compensation circuit according to another aspect of the present disclosure is illustrated.

[0016] Figure 6 A schematic diagram of another portion of an exemplary aging compensation circuit according to another aspect of the present disclosure is illustrated.

[0017] Figure 7 A flow chart of an exemplary method for compensating for aging effects of a receiver according to another aspect of the present disclosure is illustrated.

[0018] Figure 8 A block diagram of an exemplary vehicle control system according to another aspect of the present disclosure is illustrated. DETAILED DESCRIPTION

[0019] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The specific description includes specific details for providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid blurring these concepts.

[0020] The present disclosure relates to an aged replica circuit of a target circuit (e.g., a receiver) to be compensated for aging effects, and an unaged replica circuit of the target circuit. At the beginning of the operating life (start-up) of the circuit, the aged replica circuit (not aged at this time) and the unaged replica circuit are calibrated to generate substantially the same output voltage. During the operating life of the circuit, the aged replica circuit operates in a manner similar to the target circuit, so that the aging of the aged replica circuit is substantially the same as or more severe than the aging of the target circuit. The unaged replica circuit is disabled for most of the operating life of the circuit and is enabled periodically or in some time-based manner to evaluate the aging of the aged replica circuit, then compensate for the aging effects of the aged replica circuit, and then compensate for the target circuit.

[0021] Figure 1 A block diagram of an exemplary apparatus 100 including an exemplary aging compensation circuit 130 according to an aspect of the present disclosure is illustrated. The apparatus 100 includes a data transmission component 105, which may be a double data rate (DDR) memory data transmission component or a low power DDR (LPDDR) memory data transmission component, etc. The data transmission component 105 includes a group of one or more transmitters (Tx) 110-1 to 110-N, a group of one or more receivers (Rx) 115-1 to 115-N, and a group of one or more transmission media 120-1 to 120-N coupling the group of one or more transmitters 110-1 to 110-N to the group of one or more receivers 115-1 to 115-N.

[0022] Each of these transmitters 110-1 to 110-N can be configured to transmit a data signal DQ or a clock (CLK) to a corresponding receiver 115-1 to 115-N via a corresponding transmission medium 120-1 to 120-N. Typically, one of the transmitters (e.g., 110-N) is configured to transmit a clock (CLK), while the remaining transmitters (e.g., 110-1 to 110-N-1) are configured to transmit data signals DQ1 to DQN-1, respectively. As shown, the group of transmitters 110-1 to 110-N is configured to transmit data signals DQ1 to DQN-1 and a clock (CLK) to the group of receivers 115-1 to 115-N via the group of transmission media 120-1 to 120-N. Each transmission medium can be configured as one or more metallized lines or traces on a printed circuit board (PCB), such as a differential transmission line pair of each transmitter-receiver pair.

[0023] The aging compensation circuit 130 includes an aging control circuit 140, a voltage generator 145, a first multiplexer 150, an aged replica circuit 155, an unaged replica circuit 160 (e.g., which may be referred to as a “golden reference”), a second multiplexer 165, a comparator 170, and a calibration control circuit 180. The aging compensation circuit 130 may also include a controller 190 configured to generate a mode signal to control an operating mode of the aging compensation circuit 130. As described in further detail herein, the operating modes may include a startup mode, an aging mode, and a calibration mode.

[0024] The aging control circuit 140 is configured to generate an analog aging signal or voltage V SAS , to operate or work the aged replica circuit 155 substantially the same as or more heavily than the data signal DQ1 or the clock signal (CLK) operates or works the target circuit (e.g., any one of the set of receivers 115-1 to 115-N). In this example, the receiver enable signal V EN_RX is coupled to the group of receivers 115-1 to 115-N and the aging control circuit 140. When the receiver enable signal V EN RX When the receiver enable signal V is asserted, the group of receivers 115-1 to 115-N receive data signals DQ1 to DQN-1 and clock signals from the group of transmitters 110-1 to 110-N via the group of transmission media 120-1 to 120-N. EN_RX When not asserted, no data or clock signals are transmitted between the transmitters 110 - 1 to 110 -N and the receivers 115 - 1 to 115 -N.

[0025] Similarly, when the receiver enable signal V EN_RXWhen asserted, the aging control circuit 140 operates to generate an analog aging signal or voltage V SAS , thereby causing the aged replica circuit 155 to operate or work in a manner substantially the same as or more heavily than the data signals DQ1 to DQN-1 and the clock signal (CLK) cause the group of receivers 115-1 to 115-N to operate or work. When the receiver enable signal V EN_RX When not asserted, the aging control circuit 140 may be disabled (eg, not generating V SAS ) to save power.

[0026] The aging control circuit 140 includes an output coupled to a first input of a multiplexer 150. The voltage generator 145 includes at least one output coupled to a second input of the multiplexer 150 via an associated or integrated single pole double throw (SPDT) switch 146. The multiplexer 150 includes a select input configured to receive a mode signal generated by the controller 190. The multiplexer 150 includes an output coupled to a first input of an aging replica circuit 155. As an example, if the mode signal indicates an aging mode, the multiplexer 150 will simulate the aging signal or voltage V SAS is passed to the first input of the aged replica circuit 155. If the mode signal indicates a start-up or calibration mode, the multiplexer 150 receives the voltage V received from the voltage generator 145 via the SPDT 146. IN is passed to the first input of the aged replica circuit 155. As an example, where the aged replica circuit 155 (and the set of receivers 115-1 to 115-N) are configured as differential circuits, the voltage V IN Can be the common mode voltage V CM .

[0027] Optionally, there may be an operating mode that disables the aged replica circuit 155 in order to save power; in this case, the voltage generator 145 may be configured to generate a disable voltage V DSB In this mode, the multiplexer 150 receives the disable voltage V from the voltage generator 145 via the SPDT 146. DSB , and will disable the voltage V DSB is passed to the first input of the aged replica circuit 155, which effectively disables the aged replica circuit 155. It should be appreciated that the voltage generator 145 may generate other voltages including the lower voltage rail potential Vss, which may be configured as a ground potential for other operations or applications.

[0028] The aged replica circuit 155 may be a substantial copy of at least a portion of one of the group of receivers 115-1 to 115-N. For example, the group of receivers 115-1 to 115-N may include a preamplifier stage, an equalizer, a clock and data recovery (CDR) circuit, a deserializer, etc., respectively. The aged replica circuit 155 may be a substantial copy of the preamplifier stage rather than other components of the receiver. In addition, the aged replica circuit 155 need not be an exact copy of the preamplifier stage, but may include more (one or more) components or fewer (one or more) components, which does not substantially affect the similar aging effects between the receivers 115-1 to 115-N and the aged replica circuit 155. Alternatively or additionally, the aged replica circuit 155 may be a smaller scale version (e.g., using transistors of 10x (or other ratio) smaller size) of at least a portion of one of the group of receivers 115-1 to 115-N. As shown, the aging replica circuit 155 includes a second input for receiving an aging control signal (AGING CS) and an output configured to generate a first output voltage V1 (eg, a direct current (DC) voltage).

[0029] The second multiplexer 165 includes a first input and a second input that may also be coupled to the voltage generator 145. For example, the first input of the second multiplexer 165 may be configured to receive a disable signal V from the voltage generator 145. DSB Similarly, the second input of the second multiplexer 165 can be configured to receive the voltage V from the voltage generator 145. IN The second multiplexer 165 additionally includes a select input configured to receive a mode signal generated by the controller 190 . Furthermore, the second multiplexer 165 includes an output coupled to the unaged replica circuit 160 .

[0030] Similar to the aged replica circuit 155, the unaged replica circuit 160 may be a substantial replica of at least a portion of one of the group of receivers 115-1 to 115-N. For example, the unaged replica circuit 160 may be a substantial replica of the pre-amplification stage of one of the group of receivers 115-1 to 115-N but not other components of the receiver (e.g., equalizer, CDR, deserializer, etc.). In addition, the unaged replica circuit 160 also need not be an exact copy of the pre-amplification stage, but may include more (one or more) components or fewer (one or more) components. As described, the unaged replica circuit 160 may be a smaller-scale version (e.g., using transistors of a smaller size of 10x (or other ratio)) of at least a portion of one of the group of receivers 115-1 to 115-N. For example, the unaged replica circuit 160 may be a substantial replica of the aged replica circuit 155. As shown, the unaged replica circuit 160 includes an output that is configured to generate a second output voltage V2 (e.g., a DC voltage).

[0031] The comparator 170 includes a first input and a second input coupled to the outputs of the aged replica circuit 155 and the unaged replica circuit 160, respectively. Thus, the comparator 170 is configured to receive the first output voltage V1 and the second output voltage V2 at its first input and second input, respectively. The comparator 170 includes an output configured to generate a compensation voltage V based on the difference between the first output voltage V1 and the second output voltage V2. COMP .

[0032] The calibration control circuit 180 includes a first input coupled to the output of the comparator 170. Thus, the first input of the calibration control circuit 180 is configured to receive the compensation voltage V COMP The calibration control circuit 180 includes a second input configured to receive a mode signal generated by the controller 190, and a first output configured to generate an aging control signal (AGINGCS). The first output of the calibration control circuit 180 is coupled to a second input of the aged replica circuit 155. The calibration control circuit 180 also includes a second output configured to generate a broadcast aging control signal (AGINGCS). B ). The second outputs are coupled to the inputs of the group of receivers 115-1 to 115-N, respectively.

[0033] At startup, the group of receivers 115-1 to 115-N, the aged replica circuit 155, and the unaged replica circuit 160 are not aged, or may be aged negligibly due to testing or other preliminary operations. At startup, the aged replica circuit 155 is calibrated to generate a first output voltage V1 that is substantially equal to a second output voltage V2 generated by the unaged replica circuit 160.

[0034] In this case, the controller 190 sets the operation mode to the startup mode. In this mode, the first multiplexer 150 and the second multiplexer 165 respectively set the voltage V IN The inputs of the aged replica circuit 155 and the unaged replica circuit 160 are transmitted. In response, the aged replica circuit 155 and the unaged replica circuit 160 are based on the input voltage V IN The comparator 170 generates a compensation voltage V based on the difference between the first output voltage V1 and the second output voltage V2. COMP The calibration control circuit 180 is based on the compensation voltage V COMP (For example, V COMP =0 volts (V)) generates an aging control signal (AGING CS) to adjust the aged replica circuit 155 so that its output is substantially equal to the first output voltage V1 and the second output voltage V2. Since both the aged replica circuit 155 and the unaged replica circuit 160 are substantially unaged at startup, the equal magnitude of the first output voltage V1 and the second output voltage V2 indicates that these circuits are at the same aging level.

[0035] After the startup mode, the aging compensation circuit 130 operates in the aging mode. In this mode, the first multiplexer 150 and the second multiplexer 165 convert the voltage V SAS and V DSB Delivered to the inputs of the aged replica circuit 155 and the unaged replica circuit 160, respectively. The disable voltage V delivered to the unaged replica circuit 160 DSB The unaged replica circuit 160 is effectively disabled. This is done so that in the aging mode, the unaged replica circuit 160 does not age, so as to maintain the aging of the unaged replica circuit 160 to a minimum or very low level. The analog aging signal or voltage V delivered to the aged replica circuit 155 is SAS The aged replica circuit 155 operates or functions substantially the same as or more heavily than the data signals DQ1 to DQN-1 and the clock signal (CLK) operate or functions corresponding to a group of receivers 115-1 to 115-N. EN_RX When asserted, the receivers 115-1 to 115-N are operating or operative by the signals received therefrom; in response to the asserted enable signal V EN_RX The aging control circuit 140 simulates the aging signal V SAS The aged replica circuit 155 is enabled or operated.

[0036] The aging compensation circuit 130 operates periodically or in some time-based manner in a calibration mode (e.g., a calibration mode indicated by a mode signal generated by the controller 190). In the calibration mode, the aging effect of the aging replica circuit 155 is evaluated based on the change of the first output voltage V1. For example, for a specific implementation of the aging replica circuit 155, the first output voltage V1 has a tendency to decrease with aging. Then, the comparator 170 generates a compensation voltage V based on the difference between the first output voltage V1 and the second output voltage V2. COMP , to indicate the aging of the aging replica circuit 155. Then, the calibration control circuit 180 generates or adjusts the aging control signal (AGING CS) to make the first output voltage V1 substantially equal to the second output voltage V2. Therefore, in this case, the aging replica circuit 155 has compensated for aging. Then, the final aging control signal (AGING CS) of each calibration cycle is broadcast (AGING CS B ) to the group of receivers 115-1 to 115-N in order to compensate for receiver aging.

[0037] In more detail, in the calibration mode, the first multiplexer 150 and the second multiplexer 165 respectively convert the voltage V IN is passed to the inputs of the aged replica circuit 155 and the unaged replica circuit 160. Therefore, in the calibration mode, the aging control circuit 140 is decoupled from the aged replica circuit 155. Therefore, the aged replica circuit 155 stops receiving the analog aging signal V SAS In addition, in calibration mode, the voltage V DSB is not coupled to the unaged replica circuit 160; instead, V IN is applied to the unaged replica circuit 160. In response to receiving the input voltage V IN , the aged replica circuit 155 and the unaged replica circuit 160 are based on the input voltage V IN The comparator 170 generates a compensation voltage V based on the difference between the first output voltage V1 and the second output voltage V2. COMP The calibration control circuit 180 adjusts the aging control signal (AGING CS) to cause the aged replica circuit 155 to generate the first output voltage V1 so that the first output voltage is substantially equal to the second output voltage V2. In response to V1 and V2 being substantially equal, the calibration control circuit 180 broadcasts the final aging signal (AGING CS) of each calibration cycle to the group of receivers 115-1 to 115-N. B ) in order to compensate for receiver aging.

[0038] The frequency of the calibration cycle may be based on a metric or function related to the usage of the data transmission component 105. If the usage frequency of the data transmission component 105 is relatively high, the frequency of the calibration cycle should also be relatively high. Conversely, if the usage frequency of the data transmission component 105 is relatively low, the frequency of the calibration cycle should also be relatively low. As an example, if the device 100 is used in an automotive application, the usage frequency of the data transmission component 105 may be higher than if the data transmission component 105 is used in a cellular telephone application. When the unaged replica circuit 160 is enabled during the calibration cycle, the frequency of the calibration cycle should be kept low enough so as not to significantly age the unaged replica circuit 160.

[0039] Figure 2 A block diagram of another exemplary device 200 including another exemplary aging compensation circuit 230 according to another aspect of the present disclosure is illustrated. Device 200 is an example of a more specific implementation of device 100 in that the aging control circuit 140 of device 100 can be configured as an oscillator such as a voltage controlled oscillator (VCO). Elements of device 200 that are the same or common to device 100 are denoted by the same reference numerals, except that their most significant bit (MSD) is "2" instead of "1". Details of these common elements have been described with reference to device 100.

[0040] As described, the aging control circuit 140 of the device 100 may be implemented as an oscillator or VCO 240 in the device 200. Thus, the VCO 240 is configured to generate an analog aging signal or voltage V SAS As an oscillation signal, it can also be a substantially periodic oscillation signal. SAS The frequency of the oscillation signal V may be consistent with the data rate of the data signals DQ1 to DQN-1 or the frequency of the clock signal (CLK) provided to the group of receivers 215-1 to 215-N. SAS The frequency of the oscillation signal V may be within an expected or specified range of the data rate of the data signals DQ1 to DQN-1 or the frequency of the clock signal (CLK). According to another embodiment, the oscillation signal V SAS The frequency may be on the high side or higher than the expected or specified range of the data rate of the data signals DQ1 to DQN-1 or the frequency of the clock signal (CLK). This may be because it may be more beneficial to evaluate the aging of the group of receivers 215-1 to 215-N higher than the actual aging of the receivers.

[0041] Therefore, in the aging mode, when the receiver makes the signal V EN_RX When the VCO 240 is asserted (indicating that the receivers 215-1 to 215-N are receiving the data signals DQ1 to DQN-1 and the clock signal (CLK)), the VCO 240 generates the oscillation aging signal V SAS, the oscillation aging signal is transmitted by the multiplexer 250 to the aging replica circuit 255. Therefore, the oscillation aging signal V SAS The aged replica circuit 255 operates or functions substantially the same as or more heavily than the data signals DQ1 to DQN-1 and the clock signal (CLK) operate or functions of the group of receivers 215-1 to 215-N. When the receiver enable signal V EN_RX When not asserted (indicating that the receivers 215 - 1 to 215 -N are not receiving the data signals DQ1 to DQN- 1 and the clock signal (CLK)), the VCO 240 is disabled by the de-asserted receiver enable signal VEN_RX.

[0042] Figure 3 1 shows a block diagram of another exemplary device 300 including another exemplary aging compensation circuit 330 according to another aspect of the present disclosure. Similarly, the device 300 is an example of a more specific implementation of the device 100, in that the aging control circuit 140 of the device 100 can be coupled to the output of one of the receivers in the group so that the simulated aging signal V SAS is an analog aging signal based on a data signal or clock signal received by the receiver. Elements of the apparatus 300 that are identical or common to the apparatus 100 are denoted by the same reference numerals except that their MSD is "3" instead of "1". Details of these common elements have been described with reference to the apparatus 100.

[0043] In the device 300, the aging control circuit 340 can be implemented as a voltage level shifter or a current mode logic (CML) circuit. In this example, the voltage level shifter or CML circuit 340 is differential, but can also be single-ended. The voltage level shifter or CML circuit 340 includes a differential input coupled to the differential output of one of the receivers in the group of receivers (e.g., receiver 315-1). As described above, the differential input of the voltage level shifter or CML circuit 340 can be coupled to the differential output of the first amplifier stage of the receiver 315-1 because the receiver 315-1 can include additional stages such as an equalizer, CDR, deserializer, etc. The voltage level shifter or CML circuit 340 then receives the differential data signal DQ1 or the clock signal (CLK) from the differential output (OUT-1) of the receiver 315-1, and voltage level shifts the differential signal to generate an analog aging signal or voltage V at a voltage level suitable for the input of the aging replica circuit 355. SAS Since the simulated aging signal V SAS is an analog aging signal based on the data signal DQ1 or the clock signal (CLK), and thus can cause the aging replica circuit 355 to operate substantially the same as the data signal DQ1 or the clock signal (CLK) causes the receiver 315 - 1 to operate.

[0044] Therefore, in the aging mode, when the receiver 315-1 receives the data signal DQ1 or the clock signal (CLK), the voltage level shifter or CML 340 generates an analog aging signal V SAS . Simulated aging signal V SAS is passed to the aging replica circuit 355 by the multiplexer 350. Therefore, the analog aging signal V SAS The aged replica circuit 355 is operated or operates substantially the same as the data signal DQ1 or the clock signal (CLK) causes the receiver 315-1 to operate or operate. When the receiver 315-1 is not receiving the data signal DQ1 or the clock signal (CLK), the voltage level shifter or CML 340 is effectively disabled because it is not generating the analog aged signal V SAS .

[0045] Figure 4 A schematic diagram of an exemplary aging compensation circuit 400 according to another aspect of the present disclosure is illustrated. The aging compensation circuit 400 may be an example of a more detailed implementation of the aging compensation circuit 230 described above.

[0046] Specifically, the aging compensation circuit 400 includes a calibration control circuit 410, a voltage controlled oscillator (VCO) 420, a first multiplexer 430, an aged replica circuit 440, an unaged replica circuit 450, a comparator 460, and a controller 490. Starting with the VCO 420, it includes a set of cascaded differential buffers or inverters 422-1 to 422-4. In this example, the VCO 420 includes four (4) buffers or inverters 422-1 to 422-4. However, it should be understood that the VCO 420 may include a different number of cascaded differential buffers or inverters. For the purpose of feedback oscillation, the last buffer or inverter 422-4 includes a complementary output that is cross-coupled to the complementary input of the first buffer or inverter 422-1. As described above, the VCO 420 is configured to receive the receiver enable signal V EN_RX , to enable VCO 420 when the set of receivers 215-1 to 215-N are enabled to receive data signals DQ1 to DQN-1 and a clock signal (CLK) to generate a differential analog aging signal or voltage V SAS ; otherwise VCO 420 is disabled as described above.

[0047] The first multiplexer 430 includes a pair of tri-state buffers 432 and 434 and a pair of switch devices SW1 to SW2 (which may be configured as field effect transistors (FETs)). The tri-state buffers 432 and 434 include inputs coupled to the differential outputs of the last buffer or inverter 422-4 of the VCO 420 (also the differential inputs of the first buffer or inverter 422-1). The switch devices SW1 and SW2 are coupled between a voltage generator (e.g., voltage generator 245) and the outputs of the tri-state buffers 432 and 434. To achieve flexibility, the voltage generator may apply separate or the same voltages, such as different common-mode voltages V to the switch devices SW1 and SW2. CMA and V CMB , Disable voltage V DSB (which can be at Vdd potential, V at the source of FETs M1 and M2 CSA potential, Vss or ground.

[0048] The tri-state buffers 432 and 434 and the switch devices SW1 and SW2 include control inputs configured to receive a mode signal generated by the controller 490. For example, if the mode signal indicates a startup mode or a calibration mode, the tri-state buffers 432 and 434 are tri-stated and the switch devices SW1 and SW2 are in their closed states. If the mode signal indicates an aging mode, the tri-state buffers 432 and 434 will differentially convert the analog aging signal V SAS Passed to the aged replica circuit 440, the switching devices SW1 and SW2 are in their off states.

[0049] As discussed, the aged replica circuit 440 can be a substantial replica of at least a portion of any of the receivers 215-1 to 215-N (e.g., a front-end differential amplifier stage of each receiver). As an example, the aged replica circuit 440 includes a variable current source 442, an input differential FET pair M1 and M2 (e.g., implemented as p-channel metal oxide semiconductor FETs (PMOS FETs), respectively), and a pair of output resistors R1 and R2. On the negative side of the differential implementation, the current source 442, FET M1, and resistor R1 are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). On the positive side of the differential implementation, the current source 442, FET M2, and resistor R2 are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). FET M1 and FET M2 include gates coupled to the outputs of the tri-state buffers 432 and 434, respectively.

[0050] Additionally, as described, the unaged replica circuit 450 can be a substantial replica of at least a portion of any of the receivers 215-1 to 215-N (e.g., a front-end differential amplifier stage of each receiver). For example, the unaged replica circuit 450 includes a variable current source 452, an input differential FET pair M3 and M4 (e.g., implemented as PMOS FETs, respectively), and a pair of output resistors R3 and R4. On the negative side of the differential implementation, the current source 452, FET M3, and resistor R3 are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). On the positive side of the differential implementation, the current source 452, FET M4, and resistor R4 are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). FETs M3 and M4 include gates coupled to the outputs of multiplexers 454 and 456, respectively.

[0051] Referring to the aging compensation circuit 230, multiplexers 454 and 456 may correspond to multiplexer 265 (and in this embodiment, multiplexers 454 and 456 are illustrated as part of the unaged replica circuit 450). Multiplexers 454 and 456 are located on the negative and positive sides of the differential implementation, respectively, and include a circuit configured to receive a disable voltage V DSB The corresponding first input of the CM As mentioned above, the disable voltage V DSB The unaged replica circuit 450 is disabled by turning off FETs M3 and M4 when it is applied to the gates of FETs M3 and M4. Since FETs M3 and M4 are PMOS FETs, the disable voltage V DSB can be at Vdd potential or V at the sources of FETs M3 and M4 CSB Potential (so that the gate-source voltage V GS Substantially zero or less than the threshold voltage of FETs M3 and M4). Optionally, when the unaged replica circuit 450 is to be disabled, the switching device can be implemented to short the gate and source of FETs M3 and M4 together. Multiplexers 454 and 456 include a select input that is configured to receive a mode signal generated by controller 490.

[0052] For fine resolution offset cancellation during startup mode as further described herein, the unaged replica circuit 450 includes a first variable current source 458 coupled between an upper voltage rail Vdd and a node between the drain of a PMOS FET M3 and an output resistor R3 (e.g., a negative output) of the unaged replica circuit 450. Additionally, the unaged replica circuit 450 includes a second variable current source 452 coupled between an upper voltage rail Vdd and a node between the drain of a PMOS FET M4 and an output resistor R4 (e.g., a positive output) of the unaged replica circuit 450.

[0053] The comparator 460 includes a first multiplexer 462, a second multiplexer 464, and a differential amplifier 466. The first multiplexer 462 includes a first input coupled to a negative output of the aged replica circuit 440. The first multiplexer 462 includes a second input coupled to a positive output of the unaged replica circuit 450. The second multiplexer 464 includes a first input coupled to a negative output of the unaged replica circuit 450. The second multiplexer 464 includes a second input coupled to a positive output of the aged replica circuit 440. The first multiplexer 462 and the second multiplexer 464 include select inputs configured to receive a select signal SEL generated by the controller 490.

[0054] The differential amplifier 466 includes a first input (eg, a negative input) coupled to the output of the first multiplexer 462, a second input (eg, a positive input) coupled to the output of the second multiplexer 464, and a differential amplifier configured to generate a compensation voltage V COMP As further described herein, the compensation voltage V COMP The negative output voltage V of the unaged replica circuit 450 may be based on the difference between: (1) the negative output voltage V 2- and the negative output voltage V of the aging replica circuit 440 1- (If the select signal SEL selects the respective first inputs of multiplexers 462 and 464) (e.g., SEL=0; VCOMP=V 2- -V 1- ); or (2) the positive output voltage V of the aging replica circuit 440 1+ and the positive output voltage V of the unaged replica circuit 450 2+ (If the select signal SEL selects the corresponding second input of multiplexers 462 and 464) (e.g., SEL=1; V COMP =V 1+ -V 2+ ). In both cases, the compensation voltage V COMP An indication of the aging of the aged replica circuit 440 and, by extension, the set of receivers 215 - 1 through 215 -N is provided.

[0055] The calibration control circuit 410 includes a digital encoder 412, a first control circuit 414, a second control circuit 418, and a third control circuit 416. The digital encoder 412 can be implemented as a thermometer encoder or an analog-to-digital converter (ADC). The digital encoder 412 includes an output coupled to the comparator 460 and is configured to receive the compensation voltage V therefrom. COMP The digital encoder 412 is configured to be based on the compensation voltage V COMP Generating a Digital Code The digital encoder 412 includes an output at which a digital code is generated, which is coupled to inputs of the first control circuit 414 , the second control circuit 418 , and the third control circuit 416 , and to an input of the controller 490 .

[0056] As described in further detail herein, the first control circuit 414 is configured to generate a first current source control signal or voltage V based on the code CS1 The first current source control signal or voltage V CS1 is an example of the above-mentioned aging control signal AGING CS. The first control circuit 414 is also configured to generate a broadcast aging control signal (AGING CS) for the group of receivers 215-1 to 215-N. B ). Therefore, the first control circuit 414 includes a first output at which a control voltage V CS1 , which is coupled to a control input of a variable current source 442 of an aging replica circuit 440. The first control circuit 414 includes a second output at which a broadcast control signal AGING CS is generated. B , the second outputs are respectively coupled to the control inputs of the corresponding variable current sources of the group of receivers 215 - 1 to 215 -N.

[0057] The second control circuit 418 is configured to generate a second current source control signal or voltage V based on the code CS2 The second control circuit 418 includes an output at which a control voltage V CS2 , which is coupled to the control input of the variable current source 452 of the unaged replica circuit 450. The third control circuit 416 is configured to generate a current control signal or voltage V based on the code CS3 and V CS4 The third control circuit 416 includes an output at which a control voltage V CS3 and V CS4 , which is coupled to the control inputs of current sources 458 and 460 of the unaged replica circuit 450 .

[0058] The operation of the aging compensation circuit 400 is as follows: During startup, the aged replica circuit 440 and the unaged replica circuit 450 are not actually aged or are at substantially the same aging level. Therefore, the compensation voltage V COMP should be 0V to indicate that the aged replica circuit 440 and the unaged replica circuit 450 are at substantially the same aging level. However, due to process variations, the compensation voltage V COMP Therefore, during startup, the aged replica circuit 440 and the unaged replica circuit 450 are calibrated so that based on V 2- -V 1- and / or V 1+ -V 2+ The compensation voltage V COMP Basically equal to 0V.

[0059] For example, the controller 490 sets the mode signal to the startup mode. In response to the startup mode signal, the tri-state buffers 432 and 434 are tri-stated, and the switch devices SW1 and SW2 are in a closed state. The voltage regulator 245 can provide a common mode voltage V to the gates of the PMOS FETs M1 and M2 via the closed switch devices SW1 and SW2, respectively. CMA The voltage regulator 245 may also provide a common-mode voltage V to the second inputs of the multiplexers 454 and 456 of the unaged replica circuit 450. CMA In response to the mode signal indicating the start-up mode, the multiplexers 454 and 456 pass the common mode voltage VCMA to the gates of the PMOS FETs M3 and M4, respectively.

[0060] The controller 490 may first select V 2- -V 1- , to calibrate the aged replica circuit 440 and the unaged replica circuit 450. Initially, the compensation voltage V COMP may not be at 0V, which means that the aged replica circuit 440 and the unaged replica circuit 450 have not been calibrated. The digital encoder 412 is based on the compensation voltage V COMP Generate code. Control circuits 414, 418 and 416 adjust the current control voltage V CS1 、V CS2 and V CS3 , to adjust the current generated by current sources 442, 452, and 458 until the code indicates that the compensation voltage V COMP Basically at 0V.

[0061] Then, the controller 490 can select V 1+ -V 2+ Initially, based on V 1+ -V 2+The compensation voltage V COMP may not be at 0V, which means that the aged replica circuit 440 and the unaged replica circuit 450 are not fully calibrated. The digital encoder 412 is based on the compensation voltage V COMP Generate code. The control circuit 416 adjusts the current control voltage V CS4 , to regulate the current generated by current source 460 until the code indicates that the compensation voltage V COMP After the startup calibration, the control circuits 418 and 416 maintain the current control voltage V CS2 -V CS4 Basically constant.

[0062] Then, the controller 490 sets the mode signal to the aging mode. In response to the aging mode, the tri-state buffers 432 and 434 are not tri-stated, and the switch devices SW1 and SW2 are in the off state. When the VCO 420 is activated by the asserted receiver enable signal VEN_RX When enabled, tri-state buffers 432 and 434 will differentially convert the analog aging signal V SAS is passed to the gates of the PMOS FETs M1 and M2 of the aged replica circuit 440. Thus, the aged replica circuit 440 ages in substantially the same or more severe manner than the set of receivers 215-1 through 215-N.

[0063] The disable voltage V is set by multiplexers 454 and 456. DSB is passed to the gates of PMOS FETs M3 and M4 to turn off these devices and effectively disable the unaged replica circuit 450 in the aging mode. In addition, in response to the aging mode, the control circuit 418 can configure the current control voltage V CS2 , to turn off the variable current source 452. The control circuit 416 can also configure the current control voltage V CS3 and V CS4 , to turn off the variable current sources 458 and 460, respectively. This is done to effectively keep the unaged replica circuit 450 unaged during the aging mode. This mode occupies the majority of the time associated with the operation of the aging compensation circuit 400. In addition, in the aging mode, the comparator 460 is effectively disabled. The control circuit 414 of the calibration control circuit 410 turns off the variable current source 442 for the aged replica circuit 440 and the broadcast aging compensation signal (AGING CS) based on the final code determined during the previous calibration cycle. B ) of the current control voltage V CS1 Keep it basically constant.

[0064] As described, the controller 490 sets the mode signal to indicate the calibration mode periodically or in other time-based manner. As the unaged replica circuit 440 and the set of receivers 215-1 to 215-N are aged in the aging mode, for the same gate-source voltage V GS The conductivity of the PMOS FETs M1 and M2 and the corresponding PMOS FETs in the receivers 215-1 to 215-N is reduced. Therefore, the differential output voltage V 1+ and V 1- tends to decrease with aging. Therefore, in the calibration mode, the aging compensation circuit 400 adjusts the differential output voltage V 1+ and V 1- , making it equal to the differential output voltage V of the unaged replica circuit 450 2+ and V 2- Basically equal.

[0065] Therefore, in response to the calibration mode, the tri-state buffers 432 and 434 are tri-stated, and the switch devices SW1 and SW2 are in a closed state. The voltage regulator 245 can provide the common mode voltage V to the gates of the PMOS FETs M1 and M2 respectively via the closed switch devices SW1 and SW2. CMA The voltage regulator 245 may also provide a common-mode voltage V to the second inputs of the multiplexers 454 and 456 of the unaged replica circuit 450. CMA In response to the mode signal indicating the calibration mode, multiplexers 454 and 456 convert the common mode voltage V CMA are respectively delivered to the gates of PMOS FETs M3 and M4. In addition, in response to the calibration mode, control circuits 418 and 416 generate current control voltages V according to the code finally determined during the startup mode. CS2 -V CS4 .

[0066] The controller 490 can select V 2- -V 1- , to calibrate the aged replica circuit 440 and the unaged replica circuit 450. Under the effect of aging, the compensation voltage V COMP may no longer be substantially at 0V, which means that the aged replica circuit 440 has aged compared to the unaged replica circuit 450. The digital encoder 412 is based on the compensation voltage V COMP Generate code. The control circuit 414 adjusts the current control voltage V CS1 , to adjust the current generated by the variable current source 442 until the code indicates that the compensation voltage V COMP is substantially at 0V. The controller 490 may optionally select V 1+ -V 2+ To determine V2- -V 1- Does the calibration also cause V 1+ -V 2+ It is substantially at 0V. It should be understood that the controller 490 can select V 1+ -V 2+ As the basis for its calibration, V is then optionally selected via the selection signal SEL=0 2- -V 1- to determine whether calibration also causes V 2- -V 1- The control circuit 414 then broadcasts an aging compensation signal (AGING CS) for the group of receivers 215-1 to 215-N based on the final code that arrived during the calibration cycle. B Once the calibration cycle is completed, the controller 490 configures the aging compensation circuit 400 in the aging mode.

[0067] Figure 5 FIG. 5 is a schematic diagram of a portion of an exemplary aging compensation circuit 500 according to another aspect of the present disclosure. The aging compensation circuit 500 may include an offset voltage cancellation circuit 570 configured to substantially remove an output voltage V generated by the aging replica circuit 540. 1+ and V 1- The offset voltage cancellation circuit 570 may perform offset voltage cancellation based on a coarser (lower) resolution than the offset voltage cancellation circuit that may be implemented by the current sources 458 and 460 of the unaged replica circuit 450 described above. As an example, the coarse offset cancellation circuit 570 may cancel V 1+ and V 1- The approximately 6.5 millivolt (mV) offset voltage between 450 and 460 can be eliminated by the fine offset voltage cancellation that can be achieved by the current sources 458 and 460 of the unaged replica circuit 450. 2+ and V 2- There is an offset voltage of approximately 1.25mV between them.

[0068] More specifically, the aging compensation circuit 500 includes the above-mentioned aging replica circuit 540, which includes a variable current source 542, a pair of input differential PMOS FETs M1 and M2, and differential output resistors R1 and R2. For offset calibration, the common mode voltage V CM can be applied to the gates of the differential FET pair M1 and M2.

[0069] The coarse offset cancellation circuit 570 includes a variable current source 572, an input differential PMOS FET pair M5 and M6, a first multiplexer 574, a second multiplexer 576, an offset control circuit 580, and a digital encoder 590. On the negative side, the current source 572 and the PMOS FET M5 are coupled in series between the upper voltage rail Vdd and a node between the drain of the PMOS FET M1 of the aged replica circuit 540 and the output resistor R1 (negative output). On the positive side, the current source 572 and the PMOS FET M6 are coupled in series between the upper voltage rail Vdd and a node between the drain of the PMOS FET M2 of the aged replica circuit 540 and the output resistor R2 (positive output).

[0070] The first multiplexer 574 includes a first input and a second input, each configured to receive a disable voltage V DSB (For example, V dd or V CSO ) and the common-mode voltage V CM The first multiplexer 574 includes a select input configured to receive a select signal SEL generated by the offset control circuit 580. A , and an output coupled to the gate of the PMOS FET M5. Similarly, the second multiplexer 576 includes a first input and a second input, each configured to receive a disable voltage V DSB and common mode voltage V CM ; Select input, configured to receive the select signal SEL generated by the offset control circuit 580 B ; and an output coupled to the gate of PMOS FET M6. At the same time, the offset control circuit 580 is configured to receive an offset code generated by the digital encoder 590 (which may be based on the voltage V 1+ With V 1- The difference between the offset code and the offset code is calculated, and a current control signal or code DCS5 is generated for the variable current source 572 based on the offset code.

[0071] The offset cancellation works as follows: The offset control circuit 580 receives the offset code from the digital encoder 590 and determines the voltage V 1+ and V 1- If the offset is positive (which means V 1+ >V 1- ) (as indicated by the offset code), the offset control circuit 580 selects the signal SEL A Set to pass common mode voltage V CM , to turn on PMOS FET M5 and select signal SEL B Set to pass disable voltage VDS B, to turn off the PMOS FET M6. Then, the offset control circuit 580 generates a current control code D CS5 , to increase the current generated by current source 572, thereby generating additional current flowing through resistor R1. 1- , until it is substantially equal to V 1+ , as indicated by the offset code. If the offset is negative (meaning V 1+ <V 1- ) (as indicated by the offset code), the offset control circuit 580 respectively selects the signal SEL A Set to pass disable voltage V DSB , to turn off the PMOS FET M5 and set the selection signal SEL B Set to pass common mode voltage V CM , to turn on the PMOS FET M6. Then, the offset control circuit 580 generates a current control code D CS5 , to increase the current generated by current source 572, thereby generating additional current flowing through resistor R2. 1+ , until it is substantially equal to V 1- , as shown in the offset code.

[0072] Figure 6 FIG. 6 is a schematic diagram of a portion of an exemplary aging compensation circuit 600 according to another aspect of the present disclosure. The aging compensation circuit 600 may include an offset voltage cancellation circuit 670 configured to substantially remove an output voltage V generated by the aging replica circuit 650. 2+ and V 2- The offset voltage cancellation circuit 670 may perform offset voltage cancellation based on a coarser (lower) resolution than the offset voltage cancellation circuit that may be implemented by the current sources 658 and 660 of the unaged replica circuit 650. As an example, the coarse offset cancellation circuit 670 may cancel V 2+ and V 2- The approximately 6.5 millivolt (mV) offset voltage between 650 and 660 can be eliminated by the fine offset voltage cancellation that can be achieved by the current sources 658 and 660 of the unaged replica circuit 650. 2+ and V 2- There is an offset voltage of approximately 1.25mV between them.

[0073] More specifically, the aging compensation circuit 600 includes the above-mentioned aging replica circuit 650, which includes a variable current source 652, an input differential PMOS pair FETs M3 and M4, differential output resistors R3 and R4, and a fine offset voltage calibration circuit including variable current sources 658 and 660. For coarse offset calibration, the common mode voltage V CM Can be applied to the gates of a pair of differential FETs M3 and M4.

[0074] The coarse offset cancellation circuit 670 includes a variable current source 672, a pair of input differential PMOS FETs M7 and M8, a first multiplexer 674, a second multiplexer 676, an offset control circuit 680, and a digital encoder 690. On the negative side, the current source 672 and the PMOS FET M7 are coupled in series between the upper voltage rail Vdd and a node between the drain of the PMOS FET M3 of the aged replica circuit 650 and the output resistor R3 (negative output). On the positive side, the current source 672 and the PMOS FET M8 are coupled in series between the upper voltage rail Vdd and a node between the drain of the PMOS FET M4 of the aged replica circuit 650 and the output resistor R4 (positive output).

[0075] The first multiplexer 674 includes a first input and a second input, which are respectively configured to receive a disable voltage V DSB (For example, Vdd or V CSO ) and the common-mode voltage V CM The first multiplexer 674 includes a select input configured to receive a select signal SEL generated by the offset control circuit 680. C , and an output coupled to the gate of the PMOS FET M7. Similarly, the second multiplexer 676 includes a first input and a second input, which are respectively configured to receive the disable voltage V DSB and common mode voltage V CM ; Select input, configured to receive the select signal SEL generated by the offset control circuit 680 D ; and an output coupled to the gate of PMOSFET M8. Additionally, the offset control circuit 680 is configured to receive an offset code generated by a digital encoder 690 (which may be based on the voltage V 2+ With V 2- The difference between the offset code and the current control signal or code D for the variable current source 672 is generated based on the offset code. CS6 .

[0076] The offset cancellation operation is as follows: The offset control circuit 680 receives the offset code from the digital encoder 690 and determines the voltage V 2+ and V 2- If the offset is positive (which means V 2+ >V 2- ) (as indicated by the offset code), the offset control circuit 680 selects the signal SEL C Set to pass common mode voltage V CM , to turn on PMOS FET M7 and select signal SEL D Set to pass disable voltage VDS B, to turn off the PMOS FET M8. Then, the offset control circuit 680 generates a current control code D CS6 , to increase the current generated by current source 672, thereby generating additional current flowing through resistor R3. 2- Until it is substantially equal to V 2+ , as indicated by the offset code. If the offset is negative (which means V 2+ <V 2- ) (as indicated by the offset code), the offset control circuit 680 selects the signal SEL C Set to pass disable voltage VDS B , to turn off PMOS FETM7 and set the selection signal SEL D Set to pass common mode voltage V CM , to turn on PMOS FET M8. Then, the offset control circuit 680 generates a current control code D CS6 , to increase the current generated by current source 672, thereby generating additional current flowing through resistor R4. 2+ , until it is substantially equal to V 2- , as shown in the offset code.

[0077] Figure 7 A flow chart of an exemplary method 700 for compensating for aging effects of a receiver according to another aspect of the present disclosure is illustrated. The method 700 includes providing one of a data signal and a clock signal to a receiver (block 710). Examples of components for providing one of a data signal and a clock signal to a receiver include any of the transmitters and transmission media described herein.

[0078] The method 700 also includes, in an aging mode (block 720), providing an aging signal to a first replica circuit that is a substantial replica of the receiver substantially simultaneously with providing one of the data signal and the clock signal to the receiver, wherein the aging signal operates the first replica circuit substantially the same as or more heavily than one of the data signal and the clock signal operates the receiver (sub-block 720A). Examples of components for providing the aging signal to the first replica circuit substantially simultaneously with providing one of the data signal and the clock signal to the receiver include an aging control circuit 140, a VCO 240, and a voltage level shifter or CML 340. At the same time, the method 700 includes maintaining a second replica circuit that is a substantial replica of the receiver disabled (sub-block 720B). Examples of components for maintaining the second replica circuit disabled include setting a disable voltage V DSB Applied to any one of the voltage generators and multiplexers of any one of the unaged replica circuits.

[0079] The method 700 also includes, in the calibration mode (block 730): enabling the second replica circuit (sub-block 730A). Examples of components for enabling the second replica circuit include any one of a voltage generator and a multiplexer that applies a common-mode voltage to any one of the unaged replica circuits. The method 700 also includes stopping providing an aging signal to the first replica circuit (sub-block 730B). Examples of components for stopping providing an aging signal to the first replica circuit include multiplexers 150, 250, and 350 and tri-state buffers 432 and 434. In addition, the method 700 includes applying an input voltage to inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit generate a first output voltage and a second output voltage, respectively, based on the input voltage (sub-block 730C). Examples of components for applying an input voltage to the inputs of the first replica circuit and the second replica circuit include any one of a voltage generator and a multiplexer that applies a common-mode voltage V CM The signals are routed to either the aged replica circuit or the non-aged replica circuit respectively.

[0080] At the same time, the method 700 includes a component for generating a compensation voltage based on a difference between a first output voltage of the first replica circuit and a second output voltage of the second replica circuit (sub-block 730D). Examples of components for generating a compensation voltage based on a difference between the first output voltage of the first replica circuit and the second output voltage of the second replica circuit include any of the comparators described herein. The method 700 also includes calibrating the receiver and the first replica circuit based on the compensation voltage (sub-block 730E). Examples of components for calibrating the receiver and the first replica circuit based on the compensation voltage include any of the calibration control circuits described herein.

[0081] The method 700 also includes, in a startup mode, applying an input voltage to an input of a first replica circuit and a second replica circuit, wherein the first replica circuit and the second replica circuit generate a third output voltage and a fourth output voltage, respectively, based on the input voltage. Examples of components for applying the input voltage to the first replica circuit and the second replica circuit include any one of a voltage generator and a multiplexer that applies a common mode voltage to any one of the unaged replica circuits. The method 700 may additionally include applying a current to the second replica circuit to adjust the difference between the first output voltage and the second output voltage. Examples of components for applying a current to the second replica circuit to adjust the difference between the first output voltage and the second output voltage include a fine offset cancellation current source. In addition, the method 700 may include calibrating at least one other receiver based on the difference between the first output voltage and the second output voltage. Examples of components for calibrating at least one other receiver based on the difference between the first output voltage and the second output voltage include any one of the calibration control circuits described herein.

[0082] Figure 8 A block diagram of an exemplary automotive control system 800 according to another aspect of the present disclosure is illustrated. The automotive control system 800 includes an automatic control system (ACS) integrated circuit (IC) 810, such as a system on a chip (SOC). The ACS SOC 810 includes a set of receivers RX-1 to RX-N and an aging compensation circuit 820. The aging compensation circuit 820 can be implemented in accordance with any aging compensation circuit described herein. In this example, the aging compensation circuit 820 is coupled to the receiver RX-1 to receive the receiver enable signal V according to the aging compensation circuit 230. EN_RX , or receives data or clock signals from an intermediate node or output of the receiver RX-1 according to the aging compensation circuit 330. The aging compensation circuit 820 is also coupled to the group of receivers RX-1 to RX-N to provide them with the above-mentioned broadcast aging control signal (AGING CS B ).

[0083] The automotive control system 800 also includes an ACS sensor 850, which includes a sensor data and clock source 860 and a group of transmitters TX-1 to TX-N. The sensor data and data clock source 860 is coupled to the group of transmitters TX-1 to TX-N to provide a group of data signals and clocks to the group of transmitters TX-1 to TX-N. The data signals may belong to different automotive parameters sensed by the ACS sensor 850 (e.g., engine parameters, autonomous / assisted driving parameters, passenger comfort / entertainment parameters, etc.). The group of transmitters TX-1 to TX-N are coupled to the group of receivers RX-1 to RX-N via a group of transmission metallization lines 892-1 to 892-N formed on a printed circuit board (PCB) 890. The data / clock signals are transmitted from the group of transmitters TX-1 to TX-N to the group of receivers RX-1 to RX-N, respectively, via the group of transmission lines 892-1 to 892-N. Although not shown, the ACS SOC 810 may include one or more data signal processing cores to process data signals from the ACS sensor 850 according to a specific automatic control application.

[0084] The following provides an overview of various aspects of the present disclosure:

[0085] Aspect 1: A device comprising: a group of one or more receivers; a first replica circuit, which is a substantial replica of at least a portion of one of the group of one or more receivers; a first control circuit, generating an output signal selectively coupled to an input of the first replica circuit; a second replica circuit, which is a substantial replica of at least a portion of one of the receivers in the group of one or more receivers; a comparator, comprising: an output, a first input coupled to the first output of the first replica circuit, and a second input coupled to the second output of the second replica circuit; and a second control circuit, comprising: an input coupled to the output of the comparator, and an output coupled to the first replica circuit and coupled to the group of one or more receivers.

[0086] Aspect 2: The apparatus according to aspect 1, wherein the first control circuit comprises an oscillator.

[0087] Aspect 3: The apparatus according to aspect 1 or 2, further comprising an enable signal coupled to the group of one or more receivers and the first control circuit.

[0088] Aspect 4: The apparatus of any one of aspects 1-3, further comprising a voltage generator comprising an output coupled to an input of the first replica circuit.

[0089] Aspect 5: The apparatus according to aspect 4 further comprises a multiplexer comprising: a first input coupled to the output of the first control circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the first replica circuit.

[0090] Aspect 6: The apparatus of any of aspects 1-5, wherein the first control circuit comprises an input coupled to an output of a receiver in the group of one or more receivers.

[0091] Aspect 7: The apparatus of aspect 6, wherein the first control circuit comprises one of a voltage level shifter and a current mode logic (CML) circuit.

[0092] Aspect 8: The apparatus of aspect 7, further comprising a voltage generator comprising an output selectively coupled to an input of the first replica circuit.

[0093] Aspect 9: The apparatus according to Aspect 8 further includes a multiplexer, the multiplexer comprising: a first input, a second input and an output, the first input being coupled to the output of one of the voltage level shifter and the CML circuit, the second input being coupled to the output of the voltage generator, and the output being coupled to the input of the first replica circuit.

[0094] Aspect 10: The apparatus of any of Aspects 1-9, further comprising: a voltage generator comprising an output selectively coupled to an input of the second replica circuit; and a receiver disable signal selectively coupled to the input of the second replica circuit.

[0095] Aspect 11: The apparatus of aspect 10, further comprising a multiplexer comprising a first input coupled to the output of the voltage generator, a second input coupled to the output of the receiver disable signal, and an output coupled to the input of the second replica circuit.

[0096] Aspect 12: An apparatus according to any one of Aspects 1-11, wherein: the first replica circuit includes a first current source, a first field effect transistor (FET), and a first resistor coupled in series between a first voltage rail and a second voltage rail; and the second replica circuit includes a second current source, a second FET, and a second resistor coupled in series between the first voltage rail and the second voltage rail.

[0097] Aspect 13: The apparatus according to Aspect 12, wherein an output of the second control circuit is coupled to a first current source of the first replica circuit and a second current source of the second replica circuit, respectively.

[0098] Aspect 14: An apparatus according to Aspect 13, wherein the second control circuit comprises: a digital encoder; and a first controller comprising: an input coupled to the output of the digital encoder, a first output coupled to the first current source of the first replica circuit, and a second output of a group of one or more corresponding current sources respectively coupled to a group of one or more receivers.

[0099] Aspect 15: The apparatus according to aspect 14, wherein the second control circuit further comprises a second controller, the second controller comprising: an input selectively coupled to the first output of the first controller, and an output coupled to the second current source of the second replica circuit.

[0100] Aspect 16: The apparatus of any of Aspects 12-15, further comprising a receiver disable signal coupled to the second current source and the second FET of the second replica circuit.

[0101] Aspect 17: The apparatus of any of Aspects 12-16, wherein the second replica circuit comprises a third current source coupled between the first voltage rail and the second resistor.

[0102] Aspect 18: The apparatus according to any one of Aspects 12-17 further includes: a first offset cancellation circuit coupled to a first node between a first FET and a first resistor of the first replica circuit; and a second offset cancellation circuit coupled to a second node between a second FET and a second resistor of the second replica circuit.

[0103] Aspect 19: The apparatus of aspect 18, further comprising a voltage generator coupled to the first offset cancellation circuit and the second offset cancellation circuit.

[0104] Aspect 20: An apparatus according to any one of Aspects 1-19, wherein the first replica circuit comprises: a first current source, a first differential pair of field effect transistors (FETs), and a first resistor pair, respectively coupled in series between a first voltage rail and a second voltage rail; the second replica circuit comprises: a second current source, a second differential pair of FETs, and a second resistor pair, respectively coupled in series between the first voltage rail and the second voltage rail; the comparator comprises: a first multiplexer, comprising: a first input and a second input, the first input and the second input are respectively coupled to one resistor in the first resistor pair and one resistor in the second resistor pair; a second multiplexer, comprising: a first input and a second input, the first input and the second input are respectively coupled to another resistor in the first resistor pair and another resistor in the second resistor pair; and a differential amplifier, comprising inputs respectively coupled to outputs of the first multiplexer and the second multiplexer.

[0105] Aspect 21: A method comprising: providing one of a data signal and a clock signal to a receiver; in an aging mode: providing an aging signal to a first replica circuit, which is a substantial replica of the receiver, substantially simultaneously with providing one of the data signal and the clock signal to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than one of the data signal and the clock signal causes the receiver to operate, and keeping a second replica circuit disabled, which is a substantial replica of the receiver; in a calibration mode: enabling the second replica circuit; stopping providing the aging signal to the first replica circuit; applying an input voltage to inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit generate a first output voltage and a second output voltage, respectively, based on the input voltage; generating a compensation voltage based on a difference between the first output voltage of the first replica circuit and the second output voltage of the second replica circuit; and calibrating the receiver and the first replica circuit based on the compensation voltage.

[0106] Aspect 22: The method according to Aspect 21, wherein the aging signal comprises an oscillation signal having a frequency within the range of or higher than one of a data rate of the data signal and a frequency of the clock signal.

[0107] Aspect 23: The method according to aspect 21 or 22, wherein the aging signal is an aging signal based on one of a data signal and a clock signal.

[0108] Aspect 24: A device comprising a component for providing one of a data signal and a clock signal to a receiver; in an aging mode: a component for providing an aging signal to a first replica circuit substantially simultaneously with providing one of the data signal and the clock signal to the receiver, the first replica circuit being a substantial replica of the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than one of the data signal and the clock signal causes the receiver to operate, and a component for keeping a second replica circuit disabled, the second replica circuit being a substantial replica of the receiver; in a calibration mode: a component for enabling the second replica circuit; a component for stopping providing the aging signal to the first replica circuit; a component for applying an input voltage to inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit respectively generate a first output voltage and a second output voltage based on the input voltage, respectively; a component for generating a compensation voltage based on a difference between a first output voltage of the first replica circuit and a second output voltage of the second replica circuit; and a component for calibrating the receiver and the first replica circuit based on the difference between the first output voltage and the second output voltage.

[0109] Aspect 25: The apparatus according to Aspect 24, wherein the aging signal comprises an oscillating signal having a frequency within the range of or higher than one of a data rate of the data signal and a frequency of the clock signal.

[0110] Aspect 26: The apparatus of aspect 24 or 25, wherein the aging signal is an aging signal based on one of a data signal and a clock signal.

[0111] Aspect 27: An automobile control system, comprising: a group of automobile control signal transmitters; a group of automobile control signal receivers, respectively coupled to the group of automobile control signal transmitters via a group of transmission lines; and an aging compensation circuit, comprising: a first replica circuit, which is a substantial replica of one of the automobile control signal receivers in the group of automobile control signal receivers; a first control circuit, comprising an output selectively coupled to an input of the first replica circuit; a second replica circuit, which is a substantial replica of one of the automobile control signal receivers in the group of automobile control signal receivers; a comparator, comprising: a first input coupled to the first output of the first replica circuit, and a second input coupled to the second output of the second replica circuit; and a second control circuit, comprising: an input coupled to the output of the comparator, and an output coupled to the first replica circuit and the group of automobile control signal receivers.

[0112] Aspect 28: The automotive control system according to Aspect 27, wherein the first control circuit comprises an oscillator.

[0113] Aspect 29: The automotive control system of aspect 27 or 28, wherein the first control circuit comprises an input coupled to an output of a receiver in the group of one or more receivers.

[0114] Aspect 30: The vehicle control system according to any one of Aspects 27-29, wherein the set of vehicle control signal transmitters and the set of vehicle control signal receivers are part of a low power double data rate (LPDDR) interface.

[0115] The above description of the present disclosure is provided to enable those skilled in the art to prepare or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present invention is not intended to be limited to the embodiments described herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for circuit device aging assessment and compensation, comprising: a group of one or more receivers; an aged replica circuit that is a substantial replica of at least a portion of one of the receivers in the group of one or more receivers; a first control circuit generating an output signal selectively coupled to an input of the aged replica circuit; an unaged replica circuit that is a substantial replica of at least a portion of one of the receivers in the group of one or more receivers; a comparator comprising: an output, a first input coupled to the first output of the aged replica circuit, and a second input coupled to the second output of the unaged replica circuit; and A second control circuit includes an input coupled to the output of the comparator and an output coupled to the aged replica circuit and to the set of one or more receivers.

2. The apparatus of claim 1, wherein the first control circuit comprises an oscillator. 3 . The apparatus of claim 1 , further comprising an enable signal coupled to the group of one or more receivers and to the first control circuit.

4. The apparatus of claim 1, further comprising a voltage generator including an output coupled to the input of the aged replica circuit.

5. The apparatus of claim 4, further comprising a multiplexer, the multiplexer comprising: A first input coupled to the output of the first control circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the aged replica circuit.

6. The apparatus of claim 1, wherein the first control circuit comprises an input coupled to an output of a receiver in the group of one or more receivers. 7 . The device of claim 6 , wherein the first control circuit comprises one of a voltage level shifter and a current mode logic (CML) circuit.

8. The apparatus of claim 7, further comprising a voltage generator including an output selectively coupled to the input of the aged replica circuit.

9. The apparatus of claim 8, further comprising a multiplexer, the multiplexer comprising: a first input coupled to the output of the one of the voltage level shifter and the CML circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the aged replica circuit.

10. The apparatus according to claim 1, further comprising: a voltage generator including an output selectively coupled to an input of the unaged replica circuit; as well as A receiver disable signal is selectively coupled to the input of the unaged replica circuit.

11. The apparatus of claim 10, further comprising a multiplexer, the multiplexer comprising: A first input coupled to the output of the voltage generator, a second input coupled to the output of the receiver disable signal, and an output coupled to the input of the unaged replica circuit.

12. The device according to claim 1, wherein: The aging replica circuit includes a first current source, a first field effect transistor FET, and a first resistor coupled in series between a first voltage rail and a second voltage rail; and The unaged replica circuit includes a second current source, a second FET, and a second resistor coupled in series between the first voltage rail and the second voltage rail.

13. The apparatus of claim 12, wherein the output of the second control circuit is coupled to the first current source of the aged replica circuit and the second current source of the unaged replica circuit, respectively.

14. The apparatus according to claim 13, wherein the second control circuit comprises: Digital encoder; as well as A first controller includes an input coupled to the output of the digital encoder, a first output coupled to the first current source of the aged replica circuit, and a second output of a group of one or more corresponding current sources respectively coupled to the group of one or more receivers.

15. The device according to claim 14, wherein the second control circuit further comprises a second controller, wherein the second controller comprises: An input is selectively coupled to the first output of the first controller and to an output of the second current source of the unaged replica circuit.

16. The apparatus of claim 12, further comprising a receiver disable signal coupled to the second current source and the second FET of the unaged replica circuit.

17. The apparatus of claim 12, wherein the unaged replica circuit comprises a third current source coupled between the first voltage rail and the second resistor.

18. The apparatus according to claim 12, further comprising: a first offset cancellation circuit coupled to a first node between the first FET and the first resistor of the aged replica circuit; as well as A second offset cancellation circuit is coupled to a second node between the second FET and the second resistor of the unaged replica circuit.

19. The apparatus of claim 18, further comprising a voltage generator coupled to the first offset cancellation circuit and the second offset cancellation circuit.

20. The device according to claim 1, wherein: The aging replica circuit comprises: a first current source, a first differential pair of field effect transistors FET, and a first resistor pair respectively coupled in series between a first voltage rail and a second voltage rail; The unaged replica circuit includes: a second current source, a second differential pair of FETs, and a second resistor pair respectively coupled in series between the first voltage rail and the second voltage rail; The comparator comprises: A first multiplexer comprising: a first input and a second input, the first input and the second input being coupled to one resistor of the first resistor pair and one resistor of the second resistor pair, respectively; a second multiplexer comprising: a first input and a second input, the first input and the second input being coupled to the other resistor of the first resistor pair and the other resistor of the second resistor pair, respectively; and A differential amplifier includes inputs coupled to the outputs of the first multiplexer and the second multiplexer, respectively.

21. An automobile control system, comprising: A set of vehicle control signal transmitters; a group of vehicle control signal receivers, respectively coupled to the group of vehicle control signal transmitters via a group of transmission lines; as well as Aging compensation circuit for circuit device aging evaluation and compensation, including: an aged replica circuit, the aged replica circuit being a substantial replica of one of the group of vehicle control signal receivers; a first control circuit including an output selectively coupled to an input of the aged replica circuit; an unaged replica circuit, the unaged replica circuit being a substantial replica of one of the group of vehicle control signal receivers; a comparator comprising: a first input coupled to the first output of the aged replica circuit, and a second input coupled to the second output of the unaged replica circuit; and A second control circuit includes an input coupled to the output of the comparator and an output coupled to the aged replica circuit and the set of vehicle control signal receivers.

22. The automotive control system of claim 21, wherein the first control circuit comprises an oscillator.

23. The automotive control system of claim 21, wherein the first control circuit includes an input coupled to an output of a receiver in the group of one or more receivers.

24. The vehicle control system of claim 21, wherein the set of vehicle control signal transmitters and the set of vehicle control signal receivers are part of a low power double data rate (LPDDR) interface.

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